Motorola DSP56012 Manuel d'utilisateur

DSP56012UM/DRev. 0Published 11/98 DSP56012 24-Bit Digital Signal ProcessorUser’s Manual Motorola, IncorporatedSemiconductor Products SectorDSP Divisi

x Motorola 8.3 DAX FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . 8-58.4 DAX PROGRAMMING MODEL . . . . . . . . . . . . . . . . . .

4-20 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)4.4.4.6 DSP InterruptsThe HI interface can request interrupt service f

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-214.4.4.7 HI Usage Considerations—DSP SideSynchronization is a common pr

4-22 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)transfers. The 32-bit MC68020 host processor can use its dynamic bus s

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-23Figure 4-10 Host Processor Programming Model–Host SideInterrupt Vecto

4-24 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)4.4.5.3 Interrupt Control Register (ICR)The Interrupt Control Register

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-25In DMA modes, TREQ must be set or cleared by software to select the di

4-26 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)Figure 4-12 HSR and HCR Operation4.4.5.3.5 ICR HI Flag 1 (HF1)—Bit 4T

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-27When both HM1 and HM0 are cleared, the DMA mode is disabled, and the T

4-28 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)Using the INIT bit to initialize the HI hardware may or may not be nec

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-29counter is not automatically updated, and, as a result, the DMA counte

Motorola xi B.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3B.2 PERIPHERAL ADDRESSES . . . . . . . . . . . .

4-30 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)4.4.5.5.2 CVR Reserved—Bit 6This reserved bit is unused and read by th

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-314.4.5.6.2 ISR Transmit Data Register Empty (TXDE)—Bit 1The Transmit Da

4-32 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)4.4.5.6.7 ISR DMA Status (DMA)—Bit 6The DMA status (DMA) bit indicates

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-33Receive Low (RXL). These three registers receive data from the high by

4-34 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)Table 4-5 HI Registers after Reset (Host Side) RegisterNameRegister

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-354.4.6 HI SignalsThe fifteen HI signals are described here for convenie

4-36 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)transfer request pin of a DMA controller, or a control input of extern

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-374.4.7 Servicing the HIThe HI can be serviced by using one of the follo

4-38 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)3. strobes the data transfer using HEN. When data is being written to

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-395. DMA = 1, signifying the HI is currently being used for DMA transfer

xii Motorola

4-40 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)Figure 4-15 Interrupt Vector Register Read TimingFigure 4-16 HI Inte

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-414.4.7.5 Servicing DMA InterruptsWhen HM0 ≠ 0 and/or HM1 ≠ 0, HOREQ wil

4-42 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)4.4.8 Host Interface Application ExamplesThe following paragraphs desc

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-43Figure 4-19 HI Initialization—DSP SideX:$FFE8Host Control Register (H

4-44 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)Figure 4-20 HI Initialization—Host Side, Interrupt ModeReserved; writ

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-454.4.8.2 Polling/Interrupt Controlled Data TransferHandshake flags are

4-46 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)10The basic data transfer process from the host processor’s view (see

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-475. Assert HEN to enable the HI.6. When HEN is deasserted, the data can

4-48 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)Figure 4-25 Bits Used for Host-to-DSP Transfer0 0 Interrupt Mode (DMA

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-494.4.8.2.1 Host to DSP—Data TransferFigure 4-26 on page 4-50 shows the

Motorola xiii List of Figures Figure 1-1 DSP56012 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9Figure 2-1 DSP56012 Si

4-50 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)Figure 4-26 Data Transfer from Host to DSPTRANSFER$2INTERRUPT STATUSR

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-51The MAIN PROGRAM initializes the Host and then hangs in a wait loop wh

4-52 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)Figure 4-27 Host Command$17—DEFAULTVIEW FROM HOST VIEW FROM DSP560121

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-53The process to execute an HC (see Figure 4-28) is as follows:1. The ho

4-54 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)4.4.8.2.3 Host to DSP—Bootstrap Loading Using the HIThe circuit shown

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-55The actual code used in the bootstrap program is provided in Appendix

4-56 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)4.4.8.2.4 DSP to Host—Data TransferData transfers from the DSP to the

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-57Figure 4-32 Bits Used for DSP to Host TransferHOST DSP56012RXDF—RECEI

4-58 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)Figure 4-33 Data Transfer from DSP to HostVIEW FROM HOSTX:$FFE8HOST C

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-59The code shown in Figure 4-34 is essentially the same as the MAIN PROG

xiv Motorola Figure 4-13 Command Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-29Figure 4-14 Host Processor Transfer Ti

4-60 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)Figure 4-35 HI Hardware–DMA Mode+5 VDMACONTROLLERTRANSFER REQUESTTRAN

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-614.4.8.3.1 Host to DSP—Internal ProcessingThe following procedure outli

4-62 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)When the transfer to HORX occurs within the HI, HRDF is set. Assuming

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-63Figure 4-37 Host to DSP DMA ProcedureWRITE ICRHOST PROCESSORX:$FFE8HO

4-64 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)The HOREQ will be active immediately after initialization is completed

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-654.4.8.3.4 DSP to Host—DMA ProcedureThe following procedure outlines th

4-66 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)4.4.8.4.2 Overwriting Transmit Byte RegistersThe host programmer shoul

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-67uncertainties of pipelined interrupt processing. For this reason, the

4-68 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)

MOTOROLA DSP56012 User’s Manual 5-1 SECTION 5SERIAL HOST INTERFACE

Motorola xv Figure 4-36 DMA Transfer and HI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .4-61Figure 4-37 Host to DSP DMA Procedure . .

5-2 DSP56012 User’s Manual MOTOROLASerial Host Interface5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35.2

Serial Host InterfaceIntroduction MOTOROLA DSP56012 User’s Manual 5-35.1 INTRODUCTIONThe Serial Host Interface (SHI) is a serial I/O interface that p

5-4 DSP56012 User’s Manual MOTOROLASerial Host InterfaceSerial Host Interface Internal Architecture5.2 SERIAL HOST INTERFACE INTERNAL ARCHITECTURETh

Serial Host InterfaceSHI Clock Generator MOTOROLA DSP56012 User’s Manual 5-55.3 SHI CLOCK GENERATORThe SHI clock generator generates the serial clock

5-6 DSP56012 User’s Manual MOTOROLASerial Host InterfaceSerial Host Interface Programming ModelFigure 5-4 SHI Programming Model—DSP Side815 14 13 1

Serial Host InterfaceSerial Host Interface Programming Model MOTOROLA DSP56012 User’s Manual 5-7The interrupt vector table for the Serial Host Interf

5-8 DSP56012 User’s Manual MOTOROLASerial Host InterfaceSerial Host Interface Programming Model5.4.1 SHI Input/Output Shift Register (IOSR)—Host Sid

Serial Host InterfaceSerial Host Interface Programming Model MOTOROLA DSP56012 User’s Manual 5-95.4.3 SHI Host Receive Data FIFO (HRX)—DSP SideThe 24

5-10 DSP56012 User’s Manual MOTOROLASerial Host InterfaceSerial Host Interface Programming ModelNote: The maximum-allowed internally generated bit c

Serial Host InterfaceSerial Host Interface Programming Model MOTOROLA DSP56012 User’s Manual 5-11used in conjunction with the CPOL bit to select the

xvi Motorola Figure 6-11 Transmitter Left/Right Selection (TLRS) Programming . . . . . . .6-19Figure 6-12 Transmitter Clock Polarity (TCKP) Program

5-12 DSP56012 User’s Manual MOTOROLASerial Host InterfaceSerial Host Interface Programming Modelprescaler is operational. HRS is ignored when the SH

Serial Host InterfaceSerial Host Interface Programming Model MOTOROLA DSP56012 User’s Manual 5-13in noisy environments; the bit-rate transfer is stri

5-14 DSP56012 User’s Manual MOTOROLASerial Host InterfaceSerial Host Interface Programming Modelreset be generated (HEN cleared) before changing HI2

Serial Host InterfaceSerial Host Interface Programming Model MOTOROLA DSP56012 User’s Manual 5-15recommended that an SHI individual reset be generate

5-16 DSP56012 User’s Manual MOTOROLASerial Host InterfaceSerial Host Interface Programming Modelsuspended before transmitting an ACK. While HIDLE is

Serial Host InterfaceSerial Host Interface Programming Model MOTOROLA DSP56012 User’s Manual 5-17Note: HRIE[1:0] are cleared by hardware and software

5-18 DSP56012 User’s Manual MOTOROLASerial Host InterfaceSerial Host Interface Programming ModelCPHA = 0, HTDE is set after the end of the data word

Serial Host InterfaceCharacteristics Of The SPI Bus MOTOROLA DSP56012 User’s Manual 5-195.4.6.18 HCSR Host Busy (HBUSY)—Bit 22The read-only status bi

5-20 DSP56012 User’s Manual MOTOROLASerial Host InterfaceCharacteristics Of The I2C Bus5.6 CHARACTERISTICS OF THE I2C BUSThe I2C serial bus consists

Serial Host InterfaceCharacteristics Of The I2C Bus MOTOROLA DSP56012 User’s Manual 5-21• Data valid—The state of the data line represents valid data

Motorola xvii List of Tables Table 1-1 High True / Low True Signal Conventions. . . . . . . . . . . . . . . . . . 1-6Table 1-2 DSP56012 Internal Mem

5-22 DSP56012 User’s Manual MOTOROLASerial Host InterfaceCharacteristics Of The I2C Busgeneration of the stop event. Handshaking may also be accompl

Serial Host InterfaceSHI Programming Considerations MOTOROLA DSP56012 User’s Manual 5-23Note: The first data byte in a write-bus cycle can be used as

5-24 DSP56012 User’s Manual MOTOROLASerial Host InterfaceSHI Programming Considerationsoccurred, the contents of HTX are not transferred to IOSR, so

Serial Host InterfaceSHI Programming Considerations MOTOROLA DSP56012 User’s Manual 5-25HBIE bit is also set, the SHI issues a request to the DSP int

5-26 DSP56012 User’s Manual MOTOROLASerial Host InterfaceSHI Programming ConsiderationsWhen the SHI is enabled and configured in the I2C Slave mode,

Serial Host InterfaceSHI Programming Considerations MOTOROLA DSP56012 User’s Manual 5-275.7.3.2 Transmit Data In I2C Slave ModeA transmit session is

5-28 DSP56012 User’s Manual MOTOROLASerial Host InterfaceSHI Programming Considerations• SCK/SCL is the SCL serial clock output.• MISO/SDA is the SD

Serial Host InterfaceSHI Programming Considerations MOTOROLA DSP56012 User’s Manual 5-29DSPs, one operating as an I2C master device and the other as

5-30 DSP56012 User’s Manual MOTOROLASerial Host InterfaceSHI Programming Considerationscomplete number of words. Remember that for this purpose, the

MOTOROLA DSP56012 User’s Manual 6-1SECTION 6SERIAL AUDIO INTERFACE

xviii Motorola Table 3-5 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17Table 4-1 HI Registers after

6-2 DSP56012 User’s Manual MOTOROLASerial Audio Interface6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36.2

Serial Audio InterfaceIntroduction MOTOROLA DSP56012 User’s Manual 6-36.1 INTRODUCTIONThe DSP communicates with data sources and sinks through its Se

6-4 DSP56012 User’s Manual MOTOROLASerial Audio InterfaceSerial Audio Interface Internal Architecture• User programmable to support a wide variety o

Serial Audio InterfaceSerial Audio Interface Internal Architecture MOTOROLA DSP56012 User’s Manual 6-56.2.2 Receive Section OverviewThe receive secti

6-6 DSP56012 User’s Manual MOTOROLASerial Audio InterfaceSerial Audio Interface Internal Architecture6.2.3 SAI Transmit Section OverviewThe transmit

Serial Audio InterfaceSerial Audio Interface Internal Architecture MOTOROLA DSP56012 User’s Manual 6-7.The transmitter section data path consists of

6-8 DSP56012 User’s Manual MOTOROLASerial Audio InterfaceSerial Audio Interface Programming Model6.3 SERIAL AUDIO INTERFACE PROGRAMMING MODELThe Ser

Serial Audio InterfaceSerial Audio Interface Programming Model MOTOROLA DSP56012 User’s Manual 6-96.3.1 Baud Rate Control Register (BRC)The serial cl

6-10 DSP56012 User’s Manual MOTOROLASerial Audio InterfaceSerial Audio Interface Programming Model6.3.1.1 Prescale Modulus select (PM[7:0])—Bits 7–0

Serial Audio InterfaceSerial Audio Interface Programming Model MOTOROLA DSP56012 User’s Manual 6-11which is equivalent to the individual reset state.

Motorola xix Table B-2 Interrupt Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . . B-6Table B-3 Instruction Set Summary (S

6-12 DSP56012 User’s Manual MOTOROLASerial Audio InterfaceSerial Audio Interface Programming Modeldiscarded according to the Receiver Data Word Trun

Serial Audio InterfaceSerial Audio Interface Programming Model MOTOROLA DSP56012 User’s Manual 6-136.3.2.8 RCS Receiver Clock Polarity (RCKP)—Bit 8Th

6-14 DSP56012 User’s Manual MOTOROLASerial Audio InterfaceSerial Audio Interface Programming Model6.3.2.10 RCS Receiver Data Word Truncation (RDWT)—

Serial Audio InterfaceSerial Audio Interface Programming Model MOTOROLA DSP56012 User’s Manual 6-156.3.2.11 RCS Receiver Interrupt Enable (RXIE)—Bit

6-16 DSP56012 User’s Manual MOTOROLASerial Audio InterfaceSerial Audio Interface Programming Model6.3.2.13 RCS Receiver Left Data Full (RLDF)—Bit 14

Serial Audio InterfaceSerial Audio Interface Programming Model MOTOROLA DSP56012 User’s Manual 6-176.3.3 SAI Receive Data Registers (RX0 and RX1)The

6-18 DSP56012 User’s Manual MOTOROLASerial Audio InterfaceSerial Audio Interface Programming Model6.3.4.3 TCS Transmitter 2 Enable (T2EN)—Bit 2The r

Serial Audio InterfaceSerial Audio Interface Programming Model MOTOROLA DSP56012 User’s Manual 6-196.3.4.7 TCS Transmitter Left Right Selection (TLRS

6-20 DSP56012 User’s Manual MOTOROLASerial Audio InterfaceSerial Audio Interface Programming Model6.3.4.9 TCS Transmitter Relative Timing (TREL)—Bit

Serial Audio InterfaceSerial Audio Interface Programming Model MOTOROLA DSP56012 User’s Manual 6-21register, the last bit is transmitted eight times.

DSP56012UM/DRev. 0Published 11/98 This document (and other documents) can be viewed on the World WideWeb at http://www.motorola-dsp.com.This manual i

xx Motorola

6-22 DSP56012 User’s Manual MOTOROLASerial Audio InterfaceSerial Audio Interface Programming ModelTo clear TLDE or TRDE during left or right channel

Serial Audio InterfaceSerial Audio Interface Programming Model MOTOROLA DSP56012 User’s Manual 6-23condition. TLDE is cleared by hardware reset and s

6-24 DSP56012 User’s Manual MOTOROLASerial Audio InterfaceProgramming Considerations6.4 PROGRAMMING CONSIDERATIONSThis section discusses some import

Serial Audio InterfaceProgramming Considerations MOTOROLA DSP56012 User’s Manual 6-25When operating in the Master mode, the following initialization

6-26 DSP56012 User’s Manual MOTOROLASerial Audio InterfaceProgramming ConsiderationsAs a result, when the WSR/WST transition appears earlier than ex

MOTOROLA DSP56012 User’s Manual 7-1SECTION 7GPIO

7-2 DSP56012 User’s Manual MOTOROLAGPIO7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37.2 GPIO PROGRAMMING

GPIOIntroduction MOTOROLA DSP56012 User’s Manual 7-37.1 INTRODUCTIONThe General Purpose Input/Output (GPIO) pins are used for control and handshake f

7-4 DSP56012 User’s Manual MOTOROLAGPIOGPIO Register (GPIOR)7.3.1 GPIOR Data Bits (GD[7:0])—Bits 7–0The read/write GPIO Data bits (GD[7:0]) are used

GPIOGPIO Register (GPIOR) MOTOROLA DSP56012 User’s Manual 7-5• When the GCx bit is cleared and the GDDx bit is cleared (the pin is defined as an inpu

MOTOROLA DSP56012 User’s Manual 1-1 SECTION 1OVERVIEW

7-6 DSP56012 User’s Manual MOTOROLAGPIOGPIO Register (GPIOR)

MOTOROLA DSP56012 User’s Manual 8-1SECTION 8DIGITAL AUDIO TRANSMITTER

8-2 DSP56012 User’s Manual MOTOROLADigital Audio Transmitter8.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital Audio TransmitterOverview MOTOROLA DSP56012 User’s Manual 8-38.1 OVERVIEWThe Digital Audio Transmitter (DAX) is a serial audio interface modu

8-4 DSP56012 User’s Manual MOTOROLADigital Audio TransmitterDAX Signals8.2 DAX SIGNALSThe DAX has two signal lines:• DAX Digital Audio Output (ADO)—

Digital Audio TransmitterDAX Functional Overview MOTOROLA DSP56012 User’s Manual 8-58.3 DAX FUNCTIONAL OVERVIEWThe DAX consists of:• Audio Data Regis

8-6 DSP56012 User’s Manual MOTOROLADigital Audio TransmitterDAX Programming ModelThe second sub-frame transmission (Channel B) starts with the pream

Digital Audio TransmitterDAX Internal Architecture MOTOROLA DSP56012 User’s Manual 8-78.5.1 DAX Audio Data Registers A and B (XADRA/XADRB)XADRA and X

8-8 DSP56012 User’s Manual MOTOROLADigital Audio TransmitterDAX Internal Architecture8.5.3 DAX Audio Data Shift Register (XADSR)The XADSR is a 27-bi

Digital Audio TransmitterDAX Internal Architecture MOTOROLA DSP56012 User’s Manual 8-98.5.4.4 DAX Clock Input Select (XCS[1:0])—Bits 3–4The XCS[1:0]

1-2 DSP56012 User’s Manual MOTOROLA Overview 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31.1.1 Manual O

8-10 DSP56012 User’s Manual MOTOROLADigital Audio TransmitterDAX Internal Architecture8.5.4.10 DAX Channel B User Data (XUB)—Bit 14The value of the

Digital Audio TransmitterDAX Internal Architecture MOTOROLA DSP56012 User’s Manual 8-11Note: The XAUR bit is cleared by reading the XSTR register wit

8-12 DSP56012 User’s Manual MOTOROLADigital Audio TransmitterDAX Internal Architecture8.5.6 DAX Non-Audio Data Buffer (XNADBUF)The XNADBUF is a 3-bi

Digital Audio TransmitterDAX Internal Architecture MOTOROLA DSP56012 User’s Manual 8-13There is no programmable control for the preamble selection. T

8-14 DSP56012 User’s Manual MOTOROLADigital Audio TransmitterDAX Programming ConsiderationsNote: For proper operation of the DAX, the DSP core clock

Digital Audio TransmitterDAX Programming Considerations MOTOROLA DSP56012 User’s Manual 8-158.6.4 DAX Operation During StopThe DAX operation cannot c

8-16 DSP56012 User’s Manual MOTOROLADigital Audio TransmitterDAX Programming Considerations

MOTOROLA DSP56012 User’s Manual A-1APPENDIX ABOOTSTRAP ROM CONTENTS10 00011011010 00011011010 000110110010010100101101010101010101101101010101010010

A-2 DSP56012 User’s Manual MOTOROLABootstrap ROM ContentsA.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3A.2

Bootstrap ROM Contents MOTOROLA DSP56012 User’s Manual A-3A.1 INTRODUCTIONThis section presents the bootstrap programs (ROM code) contained in the DS

OverviewIntroduction MOTOROLA DSP56012 User’s Manual 1-3 1.1 INTRODUCTION This manual describes in detail the DSP56012 24-bit Digital Signal Proces

A-4 DSP56012 User’s Manual MOTOROLABootstrap ROM ContentsA.3 BOOTSTRAP PROGRAM LISTING; BOOTSTRAP CODE FOR DSP56012—(C) Copyright 1997 Motorola Inc.

Bootstrap ROM Contents MOTOROLA DSP56012 User’s Manual A-5bcr equ $fffe ; BCR Registerpbc equ $ffec

A-6 DSP56012 User’s Manual MOTOROLABootstrap ROM Contents; “shild” is the routine that loads from the Serial Host Interface.; MC:MB:MA = 101—bootstr

MOTOROLA DSP56012 User’s Manual B-1APPENDIX BPROGRAMMING REFERENCE

B-2 DSP56012 User’s Manual MOTOROLAProgramming ReferenceB.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3B.2

Programming Reference MOTOROLA DSP56012 User’s Manual B-3B.1 INTRODUCTIONThis section has been compiled as a reference for programmers. It contains a

B-4 DSP56012 User’s Manual MOTOROLAProgramming ReferenceFigure B-1 On-chip Peripheral Memory Map23 16 15 8 7 0X:$FFFF Interrupt Priority Register (

Programming Reference MOTOROLA DSP56012 User’s Manual B-5Table B-1 Interrupt Starting Addresses and Sources InterruptStarting AddressIPL Interrupt

B-6 DSP56012 User’s Manual MOTOROLAProgramming ReferenceP: $004A 0–2 SAI Receiver Exception if RXIL = 1P: $004C Available for Host Command::P: $004E

Programming Reference MOTOROLA DSP56012 User’s Manual B-7Levels 0, 1, 2 (Maskable)HighestLowestIRQAIRQBSAI Receiver ExceptionSAI Transmitter Exceptio

1-4 DSP56012 User’s Manual MOTOROLA OverviewIntroduction 1.1.1 Manual Organization This manual includes the following sections:• Section 1—Overview

B-8 DSP56012 User’s Manual MOTOROLAProgramming ReferenceTable B-3 Instruction Set Summary (Sheet 1 of 7)Mnemonic Syntax Parallel Moves Instructio

Programming Reference MOTOROLA DSP56012 User’s Manual B-9BTST #n,X:<aa> 1+ea 4+mvb - * - - - - - ?#n,X:<pp>#n,X:<ea>#n,Y:<aa>

B-10 DSP56012 User’s Manual MOTOROLAProgramming Reference#n,S,xxxxJMP xxxx 1+ea 4+jx --------eaJScc xxxx 1+ea 4+jx --------eaJSCLR #n,X:<ea>,x

Programming Reference MOTOROLA DSP56012 User’s Manual B-11MAC (+)S2,S1,D (parallel move) 1+mv 2+mv *******-(+)S1,S2,D (parallel move)(+)S,#n,D (no pa

B-12 DSP56012 User’s Manual MOTOROLAProgramming ReferenceRegister and Y memorydata move(...)S1,D1 Y:<ea>,D2 mv mv * * - - - - - -(...)S1,D

Programming Reference MOTOROLA DSP56012 User’s Manual B-13X:<pp>,Y:<ea>X:<pp>,P:<ea>S,X:<pp>#xxxxxx,X:<pp>X:<e

B-14 DSP56012 User’s Manual MOTOROLAProgramming ReferenceY:<aa>S#xxxRESET 1 4 --------RND D (parallel move) 1+mv 2+mv *******-ROL D (parallel

Programming Reference MOTOROLA DSP56012 User’s Manual B-15CENTRAL PROCESSORApplication:Date:Programmer:Sheet 1 of 4CarryOverflowZeroNegativeUnnormali

B-16 DSP56012 User’s Manual MOTOROLAProgramming ReferenceApplication:Date:Programmer:Sheet 2 of 4 CENTRAL PROCESSOR* = Reserved, write as 0SAL1 SAL0

Programming Reference MOTOROLA DSP56012 User’s Manual B-17Application:Date:Programmer:Sheet 3 of 4 CENTRAL PROCESSOROperating ModeRead/WriteReset = $

OverviewIntroduction MOTOROLA DSP56012 User’s Manual 1-5 1.1.2 Manual Conventions The following conventions are used in this manual:• The word “res

B-18 DSP56012 User’s Manual MOTOROLAProgramming ReferenceApplication:Date:Programmer:Sheet 4 of 4 CENTRAL PROCESSOR1514131211109876543210DF3 DF2 MF1

Programming Reference MOTOROLA DSP56012 User’s Manual B-19HISheet 1 of 5Application:Date:Programmer:Port B15PBC1 PBC065432101098714 13 12 1123* = Res

B-20 DSP56012 User’s Manual MOTOROLAProgramming ReferenceSheet 2 of 5Application:Date:Programmer:Host Status Register (HSR)HTDEHCP HRDFHF1 HF0654321

Programming Reference MOTOROLA DSP56012 User’s Manual B-21Sheet 3 of 5Application:Date:Programmer:TREQHMO RREQHF1 HF065432107* = Reserved, write as 0

B-22 DSP56012 User’s Manual MOTOROLAProgramming ReferenceSheet 4 of 5Application:Date:Programmer:TXDETRDY RXDFHF3 HF265432107* = Reserved, write as

Programming Reference MOTOROLA DSP56012 User’s Manual B-23Sheet 5 of 5Application:Date:Programmer:700707Receive High Byte Not UsedReceive Middle Byte

B-24 DSP56012 User’s Manual MOTOROLAProgramming ReferenceApplication:Date:Programmer:Sheet 1 of 3 S.H.I.* = Reserved, write as 015141312111098765432

Programming Reference MOTOROLA DSP56012 User’s Manual B-25Application:Date:Programmer:Sheet 2 of 3 S.H.I.1514131211109876543210SHI Host TransmitX:$FF

B-26 DSP56012 User’s Manual MOTOROLAProgramming Reference S.H.I.* = Reserved, write as 01514131211109876543210HRQE0 HFIF0 HM1 HM0 HI2C HENSHI Contro

Programming Reference MOTOROLA DSP56012 User’s Manual B-27Application:Date:Programmer:Sheet 1 of 4S.A.I.1514131211109876543210Receiver Control/Status

1-6 DSP56012 User’s Manual MOTOROLA OverviewDSP56012 Features 1.2 DSP56012 FEATURES • Digital Signal Processing Core– Efficient, object-code compa

B-28 DSP56012 User’s Manual MOTOROLAProgramming ReferenceApplication:Date:Programmer:Sheet 2 of 4S.A.I.1514131211109876543210Transmitter Control/X:$

Programming Reference MOTOROLA DSP56012 User’s Manual B-29Application:Date:Programmer:Sheet 3 of 4S.A.I.1514131211109876543210SAI Receive DataX:$FFE2

B-30 DSP56012 User’s Manual MOTOROLAProgramming ReferenceApplication:Date:Programmer:Sheet 4 of 4S.A.I.1514131211109876543210SAI Transmit DataX:$FFE

Programming Reference MOTOROLA DSP56012 User’s Manual B-31Application:Date:Programmer:Sheet 1 of 1GPIO1514131211109876543210GD3 GD2 GD1 GD0GPIO Contr

B-32 DSP56012 User’s Manual MOTOROLAProgramming ReferenceApplication:Date:Programmer:Sheet 1 of 1DAX15 14 13 1211109876543210DAX ControlX:$FFDEReset

IndexMotorola I-1AAddress Buses 1-12Address Generation Unit 1-11AES/EBU 8-3Bbootstrap loading using the HI 4-54Bootstrap Program Listing A-4bootstrap

I-2 MotorolaCircuit Diagram 7-5Control/Data Register 7-3GPIORControl Bits 7-4Data Bits 7-4Data Direction Bits 7-4Pin Definition 7-4Programming Model 7

Motorola I-3Host Mode Control bits (HM1–HM0) 4-26host portusage considerations 2-10host registers after resetas seen by host processor 4-33Host Reques

I-4 MotorolaLLow Power Divider 1-12MManual Conventions 1-5MEC Format 1-19, 6-3Memories 1-13Memory — See Section 3Memory Maps 1-17MF0-MF11 (PLL Multipl

Motorola I-5Programming Model 6-8RCSReceiver 0 Enable 6-10Receiver 1 Enable 6-11Receiver Clock Polarity 6-13Receiver Data Shift Direction 6-12Receiver

OverviewDSP56012 Features MOTOROLA DSP56012 User’s Manual 1-7 – PLL-based clocking with a wide range of frequency multiplications (1 to 4096) and p

I-6 MotorolaHCSRBus Error 5-18Host Busy 5-19Host Receive FIFO Full 5-18Host Receive FIFO Not Empty 5-18Host Receive Overrun Error 5-18Host Transmit Da

1-8 DSP56012 User’s Manual MOTOROLAOverviewDSP56012 Architectural Overview• Two sets of SAI interrupt vectors– SHI features:• Single master capabili

OverviewDSP56012 Architectural Overview MOTOROLA DSP56012 User’s Manual 1-9The DSP56000 core is dual-natured in that there are two independent data m

Motorola iii Table of Contents 1.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31.1.1 Manual Organization. . .

1-10 DSP56012 User’s Manual MOTOROLAOverviewDSP56012 Architectural Overview1.3.1 Peripheral ModulesThe following peripheral modules are included on

OverviewDSP56012 Architectural Overview MOTOROLA DSP56012 User’s Manual 1-111.3.2.1 Data Arithmetic and Logic Unit (Data ALU)The Data Arithmetic and

1-12 DSP56012 User’s Manual MOTOROLAOverviewDSP56012 Architectural OverviewAGU registers may be read from or written to via the Global Data Bus as 1

OverviewDSP56012 Architectural Overview MOTOROLA DSP56012 User’s Manual 1-131.3.2.7 On-Chip Emulation (OnCE) PortThe On-Chip Emulation (OnCE) port pr

1-14 DSP56012 User’s Manual MOTOROLAOverviewDSP56012 Architectural OverviewP:$000E ReservedP:$0010 0–2 SAI Left Channel Transmitter if TXIL = 0P:$00

OverviewDSP56012 Architectural Overview MOTOROLA DSP56012 User’s Manual 1-151.3.3.2 X Data MemoryThe on-chip X data memory shown in Table 1-4 is 24 b

1-16 DSP56012 User’s Manual MOTOROLAOverviewDSP56012 Architectural Overview1.3.3.5 Memory Configuration BitsThrough the use of bits PEA and PEB in t

OverviewDSP56012 Architectural Overview MOTOROLA DSP56012 User’s Manual 1-17Table 1-5 On-chip Peripheral Memory Map Address RegisterX:$FFFF Interru

1-18 DSP56012 User’s Manual MOTOROLAOverviewDSP56012 Architectural Overview1.3.4.1 Parallel Host Interface (HI)The parallel Host Interface (HI) is a

OverviewDSP56012 Architectural Overview MOTOROLA DSP56012 User’s Manual 1-191.3.4.3 Serial Audio Interface (SAI)The DSP can communicate with other de

iv Motorola 2.6 HOST INTERFACE (HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102.7 SERIAL HOST INTERFACE (SHI) . . . . . . . . . . .

1-20 DSP56012 User’s Manual MOTOROLAOverviewDSP56012 Architectural Overview

MOTOROLA DSP56012 User’s Manual 2-1SECTION 2SIGNAL DESCRIPTIONS

2-2 DSP56012 User’s Manual MOTOROLASignal Descriptions2.1 SIGNAL GROUPINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32.2 POWER .

Signal DescriptionsSignal Groupings MOTOROLA DSP56012 User’s Manual 2-32.1 SIGNAL GROUPINGSThe DSP56012 input and output signals are organized into t

2-4 DSP56012 User’s Manual MOTOROLASignal DescriptionsSignal GroupingsFigure 2-1 DSP56012 SignalsDSP56012Digital AudioTransmitter (DAX)PLL OnCE™Por

Signal DescriptionsPower MOTOROLA DSP56012 User’s Manual 2-52.2 POWERTable 2-2 Power InputsPower Name DescriptionVCCPPLL Power—VCCP is VCC dedicate

2-6 DSP56012 User’s Manual MOTOROLASignal DescriptionsGround2.3 GROUNDTable 2-3 GroundsGround Name DescriptionGNDPPLL Ground—GNDP is ground dedica

Signal DescriptionsPhase Lock Loop (PLL) MOTOROLA DSP56012 User’s Manual 2-72.4 PHASE LOCK LOOP (PLL) Table 2-4 Phase Lock Loop Signals Signal Name

2-8 DSP56012 User’s Manual MOTOROLASignal DescriptionsInterrupt and Mode Control2.5 INTERRUPT AND MODE CONTROLTable 2-5 Interrupt and Mode Control

Signal DescriptionsInterrupt and Mode Control MOTOROLA DSP56012 User’s Manual 2-9MODC/NMI Input Input Mode Select C/Non-maskable Interrupt Request— T

Motorola v 4.4.4.1.2 HCR HI Transmit Interrupt Enable (HTIE)—Bit 1 . 4-154.4.4.1.3 HCR HI Command Interrupt Enable (HCIE)—Bit 2 4-154.4.4.1.4 HCR HI

2-10 DSP56012 User’s Manual MOTOROLASignal DescriptionsHost Interface (HI)2.6 HOST INTERFACE (HI) The HI provides a fast parallel data to 8-bit port

Signal DescriptionsHost Interface (HI) MOTOROLA DSP56012 User’s Manual 2-11HR/WPB11InputInput/ OutputInput Host Read/Write—This input selects the dir

2-12 DSP56012 User’s Manual MOTOROLASignal DescriptionsHost Interface (HI)HACKPB14Input Input/ OutputInput Host Acknowledge— This input has two func

Signal DescriptionsSerial Host Interface (SHI) MOTOROLA DSP56012 User’s Manual 2-132.7 SERIAL HOST INTERFACE (SHI) The SHI has five I/O signals that

2-14 DSP56012 User’s Manual MOTOROLASignal DescriptionsSerial Host Interface (SHI)MISO/ SDAInput or OutputTri-stated SPI Master-In-Slave-Out/I2C Dat

Signal DescriptionsSerial Host Interface (SHI) MOTOROLA DSP56012 User’s Manual 2-15SS/HA2 Input Tri-stated SPI Slave Select/I2C Slave Address 2—This

2-16 DSP56012 User’s Manual MOTOROLASignal DescriptionsSerial Audio Interface (SAI)2.8 SERIAL AUDIO INTERFACE (SAI)The SAI is composed of separate r

Signal DescriptionsSerial Audio Interface (SAI) MOTOROLA DSP56012 User’s Manual 2-172.8.2 SAI Transmit SectionThe transmit section of the SAI has fiv

2-18 DSP56012 User’s Manual MOTOROLASignal DescriptionsGeneral Purpose Input/Output (GPIO)2.9 GENERAL PURPOSE INPUT/OUTPUT (GPIO) 2.10 DIGITAL AUDIO

Signal DescriptionsOnCE Port MOTOROLA DSP56012 User’s Manual 2-192.11 OnCE PORTTable 2-12 On-Chip Emulation Port (OnCE) Signals Signal NameSignalT

vi Motorola 4.4.5.6.4 ISR HI Flag 2 (HF2)—Bit 3 (read only) . . . . . . . . . 4-314.4.5.6.5 ISR HI Flag 3 (HF3)—Bit 4 (read only) . . . . . . . . .

2-20 DSP56012 User’s Manual MOTOROLASignal DescriptionsOnCE PortDSO Output Pulled highDebug Serial Output—Data contained in one of the OnCE controll

SECTION 3MEMORY, OPERATING MODES, AND INTERRUPTS

3-2 DSP56012 User’s Manual MOTOROLAMemory, Operating Modes, and InterruptsSECTION 3 MEMORY, OPERATING MODES, AND INTERRUPTS. . . . . . . . . . . . .

Memory, Operating Modes, and InterruptsIntroduction MOTOROLA DSP56012 User’s Manual 3-33.1 INTRODUCTIONThe DSP56012 program and data memories are ind

3-4 DSP56012 User’s Manual MOTOROLAMemory, Operating Modes, and InterruptsDSP56012 Data and Program Memory Maps3.2.1 X and Y Data ROMThe X data ROM

Memory, Operating Modes, and InterruptsDSP56012 Data and Program Memory Maps MOTOROLA DSP56012 User’s Manual 3-53.3.1 Reserved Memory SpacesCertain a

3-6 DSP56012 User’s Manual MOTOROLAMemory, Operating Modes, and InterruptsDSP56012 Data and Program Memory MapsFigure 3-2 Memory Maps for PEA = 1,

Memory, Operating Modes, and InterruptsDSP56012 Data and Program Memory Maps MOTOROLA DSP56012 User’s Manual 3-7Figure 3-3 Memory Maps for PEA = 0,

3-8 DSP56012 User’s Manual MOTOROLAMemory, Operating Modes, and InterruptsDSP56012 Data and Program Memory MapsFigure 3-4 Memory Maps for PEA = 1,

Memory, Operating Modes, and InterruptsDSP56012 Data and Program Memory Maps MOTOROLA DSP56012 User’s Manual 3-9• No accesses (including instruction

Motorola vii 4.4.8.4.4 Overwriting the Host Vector . . . . . . . . . . . . . . . . . 4-664.4.8.4.5 Cancelling a Pending Host Command interrupt . .

3-10 DSP56012 User’s Manual MOTOROLAMemory, Operating Modes, and InterruptsDSP56012 Data and Program Memory MapsANDI #$F3,OMR ; Clear PEA/PEB bit i

Memory, Operating Modes, and InterruptsDSP56012 Data and Program Memory Maps MOTOROLA DSP56012 User’s Manual 3-11X: $FFF5 ReservedX: $FFF4 ReservedX:

3-12 DSP56012 User’s Manual MOTOROLAMemory, Operating Modes, and InterruptsOperating Mode Register (OMR)3.4 OPERATING MODE REGISTER (OMR)The Operati

Memory, Operating Modes, and InterruptsOperating Modes MOTOROLA DSP56012 User’s Manual 3-13T states). When the DSP is driven by a stable external clo

3-14 DSP56012 User’s Manual MOTOROLAMemory, Operating Modes, and InterruptsOperating Modesends up in the first location of the Program ROM (program

Memory, Operating Modes, and InterruptsInterrupt Priority Register MOTOROLA DSP56012 User’s Manual 3-153.6 INTERRUPT PRIORITY REGISTERInterrupt prior

3-16 DSP56012 User’s Manual MOTOROLAMemory, Operating Modes, and InterruptsInterrupt Priority RegisterFigure 3-6 Interrupt Priority Register (Addr

Memory, Operating Modes, and InterruptsInterrupt Priority Register MOTOROLA DSP56012 User’s Manual 3-17SAI Right Channel ReceiverSAI Right Channel Tr

3-18 DSP56012 User’s Manual MOTOROLAMemory, Operating Modes, and InterruptsInterrupt Priority RegisterP: $0018 SAI Right Channel Receiver if RXIL =

Memory, Operating Modes, and InterruptsPhase Lock Loop (PLL) Configuration MOTOROLA DSP56012 User’s Manual 3-193.7 PHASE LOCK LOOP (PLL) CONFIGURATIO

viii Motorola 5.4.6.16 Host Receive Overrun Error (HROE)—Bit 20 . . . . . . 5-185.4.6.17 Host Bus Error (HBER)—Bit 21 . . . . . . . . . . . . . . .

3-20 DSP56012 User’s Manual MOTOROLAMemory, Operating Modes, and InterruptsOperation on Hardware Reset3.8 OPERATION ON HARDWARE RESETThe processor e

MOTOROLA DSP56012 User’s Manual 4-1SECTION 4PARALLEL HOST INTERFACE

4-2 DSP56012 User’s Manual MOTOROLAParallel Host Interface4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34.

Parallel Host InterfaceIntroduction MOTOROLA DSP56012 User’s Manual 4-34.1 INTRODUCTIONThe parallel Host Interface (HI) can serve as an 8-bit, bidire

4-4 DSP56012 User’s Manual MOTOROLAParallel Host InterfacePort B ConfigurationFigure 4-2 Parallel Port B RegistersBC1 BC0 Function00Parallel I/O (R

Parallel Host InterfacePort B Configuration MOTOROLA DSP56012 User’s Manual 4-5Figure 4-3 Port B GPIO Signals and RegistersPort BPB0PB1PB2PB3PB4PB5P

4-6 DSP56012 User’s Manual MOTOROLAParallel Host InterfacePort B Configuration4.2.1 Port B Control (PBC) RegisterThe Port B Control (PBC) register d

Parallel Host InterfacePort B Configuration MOTOROLA DSP56012 User’s Manual 4-74.2.2 Port B Data Direction Register (PBDDR)For pins configured as GPI

4-8 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceProgramming the GPIO4.3 PROGRAMMING THE GPIOThe DSP56012 on-chip peripheral memory map is

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-9Note: The Port B GPIO timing differs from the timing of the GPIO periph

Motorola ix 6.3.2.10 RCS Receiver Data Word Truncation (RDWT)—Bit 106-146.3.2.11 RCS Receiver Interrupt Enable (RXIE)—Bit 11. . . . . 6-156.3.2.12 R

4-10 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)4.4.1 HI Features• Speed—6.6 million words/sec (19.8 MBytes/sec) Inter

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-11– I/O short addressing provides faster execution with fewer instructio

4-12 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)•4.4.3 HI—DSP ViewpointThe DSP views the HI as a memory-mapped periphe

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-13standard instructions and addressing modes. The MOVEP instruction allo

4-14 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)The following paragraphs describe the purpose and operation of each bi

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-15portion is 0-filled. Any reserved bits are read as 0s and should be wr

4-16 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)Note: Hardware reset and software reset clear HF3.Note: There are four

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-174.4.4.2.3 HSR HI Command Pending (HCP)—Bit 2The HI Command Pending (HC

4-18 DSP56012 User’s Manual MOTOROLAParallel Host InterfaceHost Interface (HI)4.4.4.2.6 HSR Reserved—Bits 5 and 6These status bits are reserved for

Parallel Host InterfaceHost Interface (HI) MOTOROLA DSP56012 User’s Manual 4-19(TXDE) and DSP HI Receive Data Full (HRDF) bits are cleared. This tran