Motorola DSP96002 manuels

Manuels d'utilisation et guides de l'utilisateur pour Acoustique Motorola DSP96002.
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Motorola DSP96002 Manuel d'utilisateur (897 pages)


marque: Motorola | Catégorie: Acoustique | Taille: 2.60 MB |

 

Table des matières

DSP96002

1

SECTION 1

2

DSP96002 INTRODUCTION

2

SECTION 2

4

5.16.1 Arbitration Scheme

19

SECTION 3

24

CHIP ARCHITECTURE

24

3.2.2 Address Buses

25

3.2.6 Y Data Memory

27

3.3.1 Multiply Unit

30

CAUTION

34

SOFTWARE ARCHITECTURE

40

SECTION 4

40

Figure 4-3. SR Format

44

SECTION 5

54

5.3.1 Data ALU Registers

58

5.6 OPERAND REFERENCES

64

5.6.1 Program References

64

5.6.2 Stack References

64

5.8.1 Linear Modifier

71

5.8.3 Modulo Modifier

71

No x

72

Yes x x x x x

72

Yes x x x x

72

∫Nn∫ is not

73

Modifier

75

SECTION 6

77

INSTRUCTION SET AND EXECUTION

77

6.3 INSTRUCTION FORMAT

82

SECTION 7

87

7.4.2 HI Reset

98

7.4.4 HI Programming Model

100

Figure 7-12. HI Functions

104

CAUTION:

110

7.4.21.1 Semaphore Control

123

7.4.21.4 ICS Register Read

124

7.4.21.5 ICS Register Write

124

7.4.21.7 IVR Register Read

124

7.5.1 Introduction

129

7.5 DMA CONTROLLER

129

DE DMA Operation

136

7.5.9 DMA Addressing Modes

137

7.5.10 DMA Restrictions

137

7.6 I/O MEMORY MAP

138

SECTION 8

141

EXCEPTION PROCESSING

141

SECTION 9

157

SECTION 10

167

ON-CHIP EMULATOR

167

10.4.2 Breakpoint Counter

174

10.8.3 PIL Register (OPILR)

180

10.8.4 GDB Register (OGDBR)

180

10.9 PAB HISTORY BUFFER

180

APPENDIX A

189

INSTRUCTION SET DETAILS

189

– – X Nn

190

001 Rn X X X X (Rn)+Nn

190

000 Rn X X X (Rn)- Nn

190

101 Rn X X (Rn+Nn)

190

Figure A-3

192

Mnemonic A

193

Bcc ––––––––

193

A.7 OPCODE DESCRIPTIONS

206

ABS Absolute Value ABS

207

ADD Add ADD

208

ADDC Add with Carry ADDC

209

AND Logical AND AND

210

ASL Arithmetic Shift Left ASL

215

Bcc Branch Conditionally Bcc

219

BCHG Bit Test and Change BCHG

221

BCLR Bit Test and Clear BCLR

225

BFIND Find Leading One BFIND

229

BRA Branch Always BRA

230

BRSET Branch if Bit Set BRSET

234

BSET Bit Test and Set BSET

242

BSR Branch to Subroutine BSR

246

BTST Bit Test BTST

251

CLR Clear an Operand CLR

254

CMP Compare CMP

255

Accept/Reject Flags

257

Conditionally

259

DEC Decrement by One DEC

261

DO Start Hardware Loop DO

262

EOR Logical Exclusive OR EOR

271

EXT Sign Extend Half Word EXT

272

EXTB Sign Extend Byte EXTB

273

FABS.S Absolute Value FABS.S

274

FABS.X Absolute Value FABS.X

276

To Subroutine Conditionally

289

FCMP Compare Two FCMP

294

Floating-Point Operands

294

FCMPG Graphics Compare FCMPG

296

FCMPM Compare Magnitude FCMPM

298

FCOPYS.S Copy Sign FCOPYS.S

300

FCOPYS.X Copy Sign FCOPYS.X

302

Conversion

316

Floating-Point Conversion

320

Multiply and Add

326

Floating-Point

330

Multiply, Add, and Subtract

330

Multiply and Subtract

334

FNEG.S Negate FNEG.S

344

FNEG.X Negate FNEG.X

346

FSCALE.S Scale FSCALE.S

348

FSCALE.X Scale FSCALE.X

350

FSEEDR Square Root FSEEDR

354

Reciprocal Approximation

354

Data ALU Register

360

INC Increment by One INC

371

INTRZ Floating-Point INTRZ

374

INTU Floating-Point INTU

376

INTURZ Floating-Point INTURZ

378

Jcc Jump Conditionally Jcc

380

JCLR Jump if Bit Clear JCLR

382

D ddddddd

384

JMP Jump JMP

385

JSET Jump if Bit Set JSET

393

JSR Jump to Subroutine JSR

396

LRA Load PC Relative Address

403

PC+xxxx → D

404

LSL Logical Shift Left LSL

407

LSR Logical Shift Right LSR

409

MOVE Move Data Registers MOVE

411

No Parallel Data Move

412

Move Move

412

U Move Update U

415

X: X Memory Move X:

416

Y: Y Memory Move Y:

421

- Opcode-operands: S,Y: ea

422

L: Long Memory Move L:

425

X: Y: XY Memory X: Y:

427

FFcc Floating-Point iF FFcc

430

Conditional Instruction

430

Rn n n n where nnn = 0-7

432

Rn n n n where nnn = 0-7

432

IFcc Integer iF IFcc

436

Conditional Instruction

436

IFcc.U Integer iF IFcc.U

439

SIOP - Not affected

460

MPYS Signed Multiply MPYS

465

MPYU Unsigned Multiply MPYU

467

NEG Negate NEG

469

NEGC Negate with Carry NEGC

470

NOP No Operation NOP

471

NOT Logical Complement NOT

472

OR Logical Inclusive OR OR

473

REP Repeat Next Instruction

477

ROL Rotate Left ROL

481

ROR Rotate Right ROR

482

RTI Return from Interrupt

483

SUB Subtract SUB

493

SUBC Subtract with Carry SUBC

494

TST Test an Operand TST

498

WAIT Wait for Interrupt WAIT

499

A.9 INSTRUCTION TIMING

501

Mnemonic Words Cycles

501

A.9.3 MOVEC Timing Summary

509

A.9.4 MOVEM Timing Summary

509

A.9.5 MOVEP Timing Summary

510

A.9.6 MOVES Timing Summary

510

A.10.3 ENDDO Restrictions

516

A.10.8 REP Restrictions

518

APPENDIX B

520

DSP BENCHMARKS

520

B.1.2 N Real Multiplies

521

B.1.3 Real Update

521

B.1.4 N Real Updates

522

B.1.8 N Complex Multiplies

524

B.1.9 Complex Update

525

B.1.10 N Complex Updates

525

B.1.16 LMS ADAPTIVE FILTER

542

B.1.17 FIR Lattice Filter

546

B.1.25 Argument Reduction

564

B.1.27 Multibit Rotates

566

B.1.43 Line Drawing

595

r5 output list

603

B.1.45.1 In-place WHT

628

B.1.45.2 Out-of-place WHT

630

B.1.46 Evaluation of LOG(x)

634

B.1.49 Power Function X

637

ftfr.s d4,d1 ffinf

645

B.3.1 Copysign(x,y)

664

B.3.5 Nextafter(x,y)

666

B.3.6 Finite(x)

668

B.3.7 Isnan(x)

668

B.3.8 x<>y

668

B.3.10Class(x)

669

671

Double precision FIR example

716

APPENDIX C

724

IEEE ARITHMETIC

724

C.1.5 Data ALU Block Diagram

731

C.1.5.2 Multiply unit

745

C.1.5.3 Adder/Subtracter Unit

745

C.1.5.4 Special Function Unit

748

C.2.1 General

749

C.2.4 Integer Arithmetic

751

APPENDIX D

753

D.1.5 Data ALU Block Diagram

759

Figure D-6. Tiny Numbers

760

Figure D-8. The Data ALU

761

\ /

766

D.1.5.2 Multiply unit

775

D.1.5.3 Adder/Subtracter Unit

775

D.1.5.4 Special Function Unit

777

D.2.1 General

780

D.2.4 Integer Arithmetic

781

 Motorola Inc., 1994

782

MOTOROLA

783

2 INSTRUCTION CACHE

785

• 25 MSBs for the tag

787

MAMBMCDECEreserved

789

3 INTEGER MODE

800

4 SINGLE PRECISION MODE

801

MAMBMCDECE

802

Single Precision Mode Bit

802

5 OnCE ENHANCEMENTS

803

24 MOTOROLA

806

MOTOROLA 27

809

223 PIN VCCN AD28 AD27 AD26 H

812

PGA GNDQ AD24 AD25 AD23 J

812

TE TIE INV TC2 TC1 TC0 TS

814

DIR DI DO

814

MOTOROLA 37

819

MOTOROLA 39

821

MOTOROLA 41

823

42 MOTOROLA

824

;and clear INV for GPIO input

825

7 ADDITIONAL CHANGES

829

******M8

830

50 MOTOROLA

832

MOTOROLA 51

833

Multiply and Add

837

56 MOTOROLA

838

58 MOTOROLA

840

60 MOTOROLA

842

62 MOTOROLA

844

MOTOROLA 63

845

64 MOTOROLA

846

MOTOROLA 65

847

66 MOTOROLA

848

MOTOROLA 67

849

68 MOTOROLA

850

MOTOROLA 69

851

70 MOTOROLA

852

MOTOROLA INC., 1994

853

10 MOTOROLA

862

MOTOROLA 11

863

12 MOTOROLA

864

MOTOROLA 13

865

14 MOTOROLA

866

MOTOROLA 15

867

16 MOTOROLA

868

MOTOROLA 17

869

18 MOTOROLA

870

Addendum

871

INDEX - 1

888





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