Motorola pro7100 Manuel de service Page 21

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Theory of Operation 2-7
2.2.10 Normal Microprocessor Operation
The µP is configured to operate in one of two modes: expanded or bootstrap. In expanded mode, the
µP uses external memory devices to operate. In bootstrap mode, the µP uses only its internal
memory.
During normal operation of the radio, the µP is operating in expanded mode and the µP (U0101) has
access to three external memory devices: U0121 (EEPROM), U0122 (SRAM), and U0111
(EEPROM). Also, within the µP there are three KBs of internal RAM, as well as logic to select
external memory devices.
The external EEPROM (U0111) space contains the information in the radio which is customer
specific, referred to as the codeplug. This information consists of items such as:
n
Band in which the radio operates
n
What frequencies are assigned to what channel
n
Tuning information.
The external SRAM (U0122) as well as the µP’s own internal RAM space are used for temporary
calculations required by the software during execution. All of the data stored in both of these
locations is lost when the radio powers off (See the particular device subsection for more details).
The µP provides an address bus of 16 address lines (ADDR 0 - ADDR 15), and a data bus of eight
data lines (DATA 0 - DATA 7). There are also three control lines: CSPROG (U0101, pin 38) to chip
select U0121, pin 30 (EEPROM), CSGP2 (U0101, pin 41) to chip select U0122, pin 20 (SRAM) and
PG7 R W (U0101, pin 4) to select whether to read or to write. The external EEPROM (U0111,pin 1),
the OPTION BOARD and EXPANSION BOARD are selected by three lines of the µP using address
decoder U0141. The chips ASFIC CMP / FRAC-N / PCIC are selected by line CSX (U0101, pin 2).
When the µP is functioning normally, the address and data lines are toggling at CMOS logic levels.
Specifically, the logic high levels should be between 4.8 to 5.0 volts, and the logic low levels should
be between 0 to 0.2 volts. No other intermediate levels should be observed, and the rise and fall
times should be <30ns.
The low-order address lines (ADDR 0 - ADDR 7) and the data lines (DATA 0-DATA 7) should be
toggling at a high rate, e. g., you should set your oscilloscope sweep to 1µs/div. or faster to observe
individual pulses. High speed CMOS transitions should also be observed on the µP control lines.On
the µP the lines XIRQ (U0101, pin 48), MODA LIR (U0101, pin 58), MODB VSTPY (U0101, pin 57)
and RESET (U0101, pin 94) should be high at all times during normal operation. Whenever a data or
address line becomes open or shorted to an adjacent line, a common symptom is that the RESET
line goes low periodically, with the period being in the order of 20msecs. In the case of shorted lines
you may also detect the line periodically at an intermediate level, i.e. around 2.5 volts when two
shorted lines attempt to drive to opposite rails.
The MODA LIR (U0101, pin 58) and MODB VSTPY (U0101, pin 57) inputs to the µP must be at a
logic 1 for it to start executing correctly. After the µP starts execution it periodically pulses these lines
to determine the desired operating mode. While the central processing unit (CPU) is running, MODA
LIR is an open-drain CMOS output which goes low whenever the µP begins a new instruction. One
instruction typically requires 2-4 external bus cycles, or memory fetches.
There are eight analog-to-digital converter ports (A/D) on U0101 labelled within the device block as
PE0-PE7. These lines sense the voltage level ranging from 0 to 5V of the input line and convert that
level to a number ranging from 0 to 255 which is read by the software to take appropriate action.
For example U0101, pin 67 is the battery voltage detect line. R0671 and R0672 form a resistor
divider on INT SWB+. With 30K and 10K and a voltage range of 11V to 17V, that A/D port is 2.74V to
4.24V which is then be converted to ~140 to 217 respectively.
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