Motorola pro7100 Manuel de service télécharger pdf (Page 28)

2-14 Theory of Operation

2.3.5.2 Audio Processing and Digital Volume Control

The receiver audio signal (DISC AUDIO) enters the controller section from the IF IC where it is AC

coupled by C0227 before entering the ASFIC CMP via the DISC input at U0221, pin 2. The signal is

then applied to both the audio and the PL/DPL paths.

The signal on the audio path is applied to a programmable amplifier, whose setting is based on the

channel bandwidth being received, an LPF filter to remove any frequency components above

3000Hz, and HPF filter to strip off any sub-audible data below 300Hz. The recovered audio passes

through a de-emphasis filter, if it is enabled, to compensate for pre-emphasis which is used to reduce

the effects of FM noise. The audio then goes through the 8-bit programmable attenuator whose level

is set depending on the value of the volume control. The resulting filtered audio signal is passed

through an output buffer within the ASFIC CMP and exits the ASFIC CMP at the AUDIO output

(U0221, pin 41).

The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum/

maximum settings of the attenuator are set by codeplug parameters.

Since sub-audible signalling is summed with voice information on transmit, it must be separated from

the voice information before processing. Any sub-audible signal enters the ASFIC CMP from the IF

IC at DISC U0221, pin 2, then through the PL/DPL path. The signal first passes through one of two

low pass filters, either PL low pass filter, or DPL/LST low pass filter. Either signal is then filtered, goes

through a limiter, and exits the ASFIC CMP at LSIO (U0221, pin 18). At this point the signal appears

as a square wave version of the sub-audible signal the radio received. The µP (U0101, pin 80)

decodes the signal directly to determine if it is the tone/code currently active on that mode.

2.3.5.3 Audio Amplification Speaker (+) Speaker (-)

The output of the ASFIC CMP’s digital volume pot (U0221, pin 41) is routed through dc blocking

capacitor C0256 to a buffer formed by U0211, pin 1. Resistors R0256 and R0268 set the correct

input level to the audio PA (U0271). This is necessary because the gain of the audio PA is 46 dB and

the ASFIC CMP output is capable of overdriving the PA unless the maximum volume is limited.

Resistor R0267 and capacitor C0267 increase frequency components below 350 Hz.

The audio then passes through R0269 and C0272 which provides AC coupling and low frequency

roll-off. C0273 provides high frequency roll-off as the audio signal is routed to audio power amplifier

U0271, pins 1 and 9 which are both tied to the received audio. The audio power amplifier has one

inverted and one non-inverted output that produces the differential audio output SPK+/SPK- (U0271,

pins 4 and 6).

The audio PA’s dc biases are not activated until the audio PA is enabled at pin 8. The audio PA is

enabled via the ASFIC CMP (U0221, pin 38). When the base of Q0271 is low, the transistor is off and

U0271-8 is high via pull-up resistor R0273, and the audio PA is ON. The voltage at U0273-8 must be

above 8.5Vdc to properly enable the device. If the voltage is between 3.3 and 6.4V, the device is

active, but has its input (U0273, pins 1 and 9) off. This is a mute condition used to prevent an audio

pop when the PA is enabled.

The SPK+ and SPK- outputs of the audio PA are dc biased and vary proportionately with FLT A+

(U0271, pin 7). FLT A+ of 11V yields a dc offset of 5V, and FLT A+ of 17V yields a dc offset of 8.5V. If

either of these lines is shorted to ground, it is possible that the audio PA could be damaged. SPK+

and SPK- are routed to the accessory connector (J0501, pins 1 and 16) and to the control head

connector (J0401, pins 2 and 3).

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Motorola pro7100 Manuel de service Page 28

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