Motorola pro7100 Manuel de service télécharger pdf (Page 47)

Theory of Operation 2-33

The external RX buffers (Q3301 and Q3302) are enabled by a high at U3301, pin 7 (RX_SWITCH)

via transistor switch Q3303. In the TX mode, the modulation signal (VCOMOD) from the LVFRAC-N

synthesizer IC (U3201 pin 41) is applied to varactor diode D3362, which modulates the TX VCO

frequency via capacitor C3362. Varactor D3362 is biased for linearity from the VSF.

2.9.4 Synthesizer Operation

The complete synthesizer subsystem consists of the low voltage FRAC-N (LVFRACN), reference

oscillator (a crystal oscillator with temperature compensation), charge pump circuit, loop filter circuit

and a dc supply. The output signal PRESC from the VCOBIC (U3301 pin 12) is fed to U3201 pin 32

(PREIN) via a low pass filter (C3318, L3318 and C3226) which attenuates harmonics and provides

the correct level to close the synthesizer loop.

The pre-scaler in the synthesizer (U3201) is a dual modulus type with selectable divider ratios. The

divider ratio of the pre-scaler is controlled by the loop divider, which in turn receives its inputs via the

SRL. The output of the pre-scaler is applied to the loop divider. The output of the loop divider is

connected to the phase detector, which compares the loop divider´s output signal with the reference

signal. The reference signal is generated by dividing down the signal of reference oscillator Y3261 or

Y3262.

The output signal of the phase detector is a pulsed dc signal which is routed to the charge pump. The

charge pump outputs a current at U3201 pin 43 (IOUT). The loop filter (which consists of R3221-

R3223 and C3221-C3224) transforms this current into a voltage that is applied to the varactor diodes

(D3361 for transmit, D3341 for receive) to alter the output frequency of the appropriate VCO. The

current can be set to a value fixed within the LVFRAC-N IC, or to a value determined by the currents

flowing into BIAS 1 (U3201-40) or BIAS 2 (U3201-39). The currents are set by the value of R3251

and R3252 respectively. The selection of the three different bias sources is done by software

programming.

To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer, the

magnitude of the loop current is increased by enabling the IADAPT pin (U3201-45) for a certain

software programmable time (adapt mode). The adapt mode timer is started by a low to high

transient of the CSX line. When the synthesizer is within the lock range, the current is determined

only by the resistors connected to BIAS 1 and BIAS 2, or by the internal current source. A settled

synthesizer loop is indicated by a high level signal at U3201-4 (LOCK).

The LOCK signal is routed to one of the µP´s ADC inputs (U0101-56). From the measured voltage,

the µP determines whether LOCK is active.

To modulate the PLL, the two spot modulation method is utilized. Via U3201, pin 10 (MODIN), the

audio signal is applied to both the A/D converter (low frequency path) as well as the balance

attenuator (high frequency path). The A/D converter changes the low frequency analog modulating

signal into a digital code that is applied to the loop divider, thereby causing the carrier to deviate. The

balance attenuator is used to adjust the VCO’s deviation sensitivity to high frequency modulating

signals. The output of the balance attenuator is present at the MODOUT port (U3201-41) and

connected to the VCO modulation diode D3362 via R3364.

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Motorola pro7100 Manuel de service Page 47