Motorola M6800 Manuel d'utilisateur

MPU-1 INTRODUCTION The Motorola M6800 Microcomputer System of standard LSI (Large Scale Integration) devices permits the systems designer to configur

MPU-10 Request signal, the processor will complete the current instruction that is being executed before it recognizes the NMI signal. The interrupt

MPU-11 available. This will occur if the GO/HALT line is in the Halt (low) mode or the 14PU is in a "Wait" state as the result of some inst

MPU-12 Microprocessor Instruction Set -- Alphabetic Sequence ABA Add Accumulators INS Increment Stack Pointer ADC Add with Carry INX Increment

MPU-13 Hardware Interrupts What happens when the MPU gets a hardware interrupt? After it has been determined that the interrupt is not non-maskable,

MPU-14

MPU-15 SUMMARY OF MPU OPERATION The MPU requires a two phase symmetrical, TTL compatible, nonoverlapping clock. During the first phase of the clock (

MPU-16 RESET SEQUENCE 1. While HALT is high, RESET goes low for at least eight cycles of Øl, Ø2 during which all internal registers are cleared and i

MPU-17 IRQ SEQUENCE 1. If bit "I" in condition code register is not set (I = 0) and IRQ goes low for at least one Ø2 cycle, the IRQ sequenc

MPU-18 NMI SEQUENCE 1. If NMI goes low for at least one Ø2 cycle, the MPU will wait for completion of current instruction. 2. The internal registers

MPU-19 SWI INSTRUCTION 1. Contents of the MPU registers PC, 1X, ACCA, ACCB and CC are stored in RAM at the address indicated by the stack pointer in

MPU-2 Microprocessing Unit (MC6800) The nucleus of the M6800 Microcomputer Family is the microprocessing unit (MPU). The MPU is enclosed in a 40 pin

MPU-20 Number Systems Everyone is quite familiar with the base 10 number system i.e. 0, 1, 2, 3, 4, 5, 6, 7, 8, & 9, since this is the system w

MPU-21 1011112 = lx20 + 1x21 + lx22 + lx23 + 0x24 + 1x25 = 1x1 + 1x2 + 1x4 + 1x8 + 0x16 + 1x32 = 1 + 2 + 4 + 8 + 0

MPU-22 First lets prove that 758 & 1111012 are really equal to 6110. 758 = 5x80+ 7x81 = 5x1 + 7x8 = 5 + 56 = 6110 1111012 = 1x20

MPU-23 Therefore 758 - 111101 which is the same pattern of 1's & 0's as we got from converting from base 10 to base 2. What this really

MPU-24 2 1 2 2 R=1 0 2 1 R=1 102 6 3 2 6 R=0 1 2 3 R=1 1102 0 2 1 R=1 7 3 2 7 R=1 1 2 3 R=1

MPU-25 1478 = 7x80 + 4x81 + 1x82 = 7x1 + 4x8 + 1x64 = 7 + 32 + 64 = 10310 6716 = 7x160 + 6x161 = 7x1 + 6x16 = 7

MPU-26 To convert any base 10 number to hex (base 16) you may convert it to base 8 first, then represent the base 8 number with its binary represent

MPU-27 82510 to octal 103 8 825 R=1 12 8 103 R=7 14718 1 8 12 R=4 0 8 1 R=1 82510 to binary 412 2 825 R=1 206 2 4

MPU-28 82510 = 11001110012 = 1x20 +Ox21 +0x22 +lx23 +1x24 +1x25 +0x26 +0x27 +lx28 +1x29 = lxl +0x2 +0x4 +lx8 +1x16 +lx32 +0x64 +0x

MPU-29 Conversion Chart Decimal Octal Hexadecimal Binary 0 0 0 0000 0000 1 1 1 0000 0001 2 2 2 0000 0010 3 3 3 0000 0011 4 4 4 000

MPU-3 5. One condition code register (CC) 6. 72 instructions 7. Five addressing modes 8. System clock range of 100 kilohertz to 1 megahertz 9. P

MPU-4 INC – Increment LDA - Load accumulator LSR - Logical shift right NEA - Negate ORA - Inclusive OR PSH - Push data onto stack PUL - Pull

MPU-5 CPX - Compare index register DEX - Decrement index register INX - Increment index register LDX - Load index register RTI - Return fr

MPU-6 Stack Pointer Address-5 : Contents of ACCB Stack Pointer Address-6 : Contents of CC After the status of each register is stored on the stack,

MPU-7 Carry-Borrow: For addition, the carry-borrow condition code (C) in the zero bit position, represents a carry. This bit gets set (C=1) to indi

MPU-8 MPU Signal Descriptions 1. READ/WRITE (R/W): This output line is used to signal all devices external to the MPU that the MPU is in a read stat

MPU-9 Counter, Accumulators, and Condition Code Register are stored away on the stack. Next the MPU will respond to the interrupt request by setting