Motorola 68HC08LD Manuel d'utilisateur

_ V1.1 POD Hardware ReferenceMotorola 68HC08LD POD rev. B iSYSTEM, March 2004 1/12Ordering code IC20187Thank you for purchasing this product

 iSYSTEM, March 2004 10/12POD Target LayoutThe POD Target Layout is T_QFP64.15 13 11 9 7 5 3 116 14 12 10 8 6 4 217 18 64 6319 20 62 6121 22 60 5923

 iSYSTEM, March 2004 11/12Notes:

 iSYSTEM, March 2004 12/12Notes:

_ POD Hardware ReferenceIn-Circuit Emulation PODs iSYSTEM, March 2004 2/12The following elements of interest are located on all In-Circuit em

 iSYSTEM, March 2004 3/12For every POD the following information is given:• Ordering code. If there are different speed versions of a POD the orderi

_ POD Hardware ReferenceMotorola 68HC08LD POD rev. B iSYSTEM, March 2004 4/12Ordering code IC20187Maximum CPU Clock (MHz) 6Emulator Speed (ns

 iSYSTEM, March 2004 5/12Bottom boardEmulated CPU68HC908LD64CPU Mask InformationA standard 68HC908LD64 CPU is inserted in the POD. If you are confron

 iSYSTEM, March 2004 6/12Electrical and Logical DifferencesIn order to enable emulation, 1k Pull-up resistor is present on the Target Reset line.The

 iSYSTEM, March 2004 7/12Voltage settingsJ1 (on the top board)Jumper selector J1 on the top board determines the operational voltage.Position Vcc lev

 iSYSTEM, March 2004 8/12General HC08 Emulation NotesInternal RAM, Internal EEPROMNote that the internal RAM of the 68HC08 CPU on the POD is disabled

 iSYSTEM, March 2004 9/12The Signal ConnectorA signal connector is present on this pod, marked as ST4.Pin Signal Description1 GND Ground2 BPEXT Exter