Motorola ColdFire MCF5281 Manuel d'utilisateur

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MCF5282 and MCF5216 ColdFire
®
Microcontroller User’s Manual
Devices Supported:
MCF5214
MCF5216
MCF5280
MCF5281
MCF5282
Document Number: MCF5282UM
Rev. 3
2/2009
Vue de la page 0
1 2 3 4 5 6 ... 765 766

Résumé du contenu

Page 1 - Microcontroller User’s Manual

MCF5282 and MCF5216 ColdFire®Microcontroller User’s ManualDevices Supported:MCF5214MCF5216MCF5280MCF5281MCF5282Document Number: MCF5282UMRev. 32/2009

Page 2

x Freescale Semiconductor8.6.3.3 Grouped Peripheral Access Control Registers(GPACR0 & GPACR1) . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 3

Cache4-2 Freescale Semiconductor output of the storage array is driven onto the ColdFire core's local data bus, thereby completing the access in

Page 4

CacheFreescale Semiconductor 4-3 of these registers. The CACR and ACRs can only be accessed in supervisor mode using the MOVEC instruction with an Rc

Page 5

Cache4-4 Freescale Semiconductor 28CPDIDisable CPUSHL invalidation. When the privileged CPUSHL instruction is executed, the cache entry defined by bit

Page 6 - Chapter 3

CacheFreescale Semiconductor 4-5 Table 4-3 shows the relationship between CACR[CENB, DISI, & DISD] bits and the cache configuration.Table 4-4 show

Page 7 - Freescale Semiconductor vii

Cache4-6 Freescale Semiconductor 4.2.2 Access Control Registers (ACR0, ACR1)The ACRs provide a definition of memory reference attributes for two memor

Page 8

CacheFreescale Semiconductor 4-7 4.3 Functional DescriptionThe cache is physically connected to the ColdFire core's local bus, allowing it to ser

Page 9

Cache4-8 Freescale Semiconductor If the referenced address is mapped into the SRAM module, that module services the request in a single cycle. In this

Page 10 - Interrupt Controller Modules

CacheFreescale Semiconductor 4-9 4.3.5 Cache Miss Fetch Algorithm/Line FillsAs discussed in Section 4.1.2, “Introduction,” the cache hardware includes

Page 11 - Chip Select Module

Cache4-10 Freescale Semiconductor For instruction fetches, the fill buffer can also be used as temporary storage for line-sized bursts of non-cacheabl

Page 12 - Signal Descriptions

Freescale Semiconductor 5-1Chapter 5 Static RAM (SRAM)5.1 SRAM Features• One 64-Kbyte SRAM• Single-cycle access• Physically located on processor&apos

Page 13 - Freescale Semiconductor xiii

Freescale Semiconductor xi10.1.1.1 Interrupt Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-310.1.1.2 Interr

Page 14 - Chapter 15

Static RAM (SRAM)5-2 Freescale SemiconductorThe RAMBAR contains several control fields. These fields are shown in Figure 5-131 30 29 28 27 26 25 24 23

Page 15 - DMA Controller Module

Static RAM (SRAM)Freescale Semiconductor 5-35.3.2 SRAM InitializationAfter a hardware reset, the contents of the SRAM module are undefined. The valid

Page 16 - Chapter 17

Static RAM (SRAM)5-4 Freescale SemiconductorThe following loop initializes the entire SRAM to zerolea.l RAMBASE,A0 ;load pointer to SRAMmove.l #16384

Page 17 - Chapter 19

Freescale Semiconductor 6-1Chapter 6 ColdFire Flash Module (CFM)The MCF5282 incorporates SuperFlash® technology licensed from SST. The ColdFire Flash

Page 18 - Chapter 20

ColdFire Flash Module (CFM)6-2 Freescale Semiconductor6.2 Block DiagramThe CFM module shown in Figure 6-1 contains the Flash physical blocks, the Cold

Page 19 - Chapter 22

ColdFire Flash Module (CFM)Freescale Semiconductor 6-3Figure 6-1. CFM Block DiagramFlash Interface•••SATOSATOSATOSATOBISTEngineInternal BusMemory Arra

Page 20 - UART Modules

ColdFire Flash Module (CFM)6-4 Freescale Semiconductor6.3 Memory MapFigure 6-2 shows the memory map for the CFM array. The CFM array can reside anywhe

Page 21 - Chapter 25

ColdFire Flash Module (CFM)Freescale Semiconductor 6-56.3.1 CFM Configuration FieldThe CFM configuration field comprises 24 bytes of reserved array me

Page 22 - General Purpose I/O Module

ColdFire Flash Module (CFM)6-6 Freescale SemiconductorNOTEFlash accesses (reads/writes) by a bus master other than the core, (DMAcontroller or Fast Et

Page 23 - Chapter 27

ColdFire Flash Module (CFM)Freescale Semiconductor 6-76.3.3 CFM RegistersThe CFM module also contains a set of control and status registers. The memor

Page 24 - Chapter 28

xii Freescale SemiconductorChapter 13External Interface Module (EIM)13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 25 - Freescale Semiconductor xxv

ColdFire Flash Module (CFM)6-8 Freescale Semiconductor6.3.4 Register DescriptionsThe Flash registers are described in this subsection.6.3.4.1 CFM Conf

Page 26 - Debug Support

ColdFire Flash Module (CFM)Freescale Semiconductor 6-96.3.4.2 CFM Clock Divider Register (CFMCLKD)The CFMCLKD is used to set the frequency of the cloc

Page 27 - Chapter 31

ColdFire Flash Module (CFM)6-10 Freescale SemiconductorNOTECFMCLKD must be written with an appropriate value before programmingor erasing the Flash ar

Page 28 - Electrical Characteristics

ColdFire Flash Module (CFM)Freescale Semiconductor 6-11The security features of the CFM are described in Section 6.5, “Flash Security Operation.”29–16

Page 29 - Revision History

ColdFire Flash Module (CFM)6-12 Freescale Semiconductor6.3.4.4 CFM Protection Register (CFMPROT)The CFMPROT specifies which Flash logical sectors are

Page 30

ColdFire Flash Module (CFM)Freescale Semiconductor 6-13Figure 6-8. CFMPROT Protection Diagram6.3.4.5 CFM Supervisor Access Register (CFMSACC)The CFMSA

Page 31 - About This Book

ColdFire Flash Module (CFM)6-14 Freescale Semiconductor6.3.4.6 CFM Data Access Register (CFMDACC)The CFMDACC specifies the data/program access permiss

Page 32 - Conventions

ColdFire Flash Module (CFM)Freescale Semiconductor 6-156.3.4.7 CFM User Status Register (CFMUSTAT)The CFMUSTAT reports Flash state machine command sta

Page 33 - Overview

ColdFire Flash Module (CFM)6-16 Freescale Semiconductor6.3.4.8 CFM Command Register (CFMCMD)The CFMCMD is the register to which Flash program, erase,

Page 34 - 1-2 Freescale Semiconductor

ColdFire Flash Module (CFM)Freescale Semiconductor 6-17initiated by the CPU. Special cases of user mode apply when the CPU is in low-power or debug mo

Page 35 - Freescale Semiconductor 1-3

Freescale Semiconductor xiii14.2.3.2 Reset Out (RSTO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2214.2.3.3 EXTAL

Page 36 - 1-4 Freescale Semiconductor

ColdFire Flash Module (CFM)6-18 Freescale SemiconductorConsider the following example for fSYS = 66 MHz:So, for fSYS = 66 MHz, writing 0x54 to CFMCLKD

Page 37 - Freescale Semiconductor 1-5

ColdFire Flash Module (CFM)Freescale Semiconductor 6-19NOTEThe page erase command operates simultaneously on adjacent erase pagesin two interleaved Fl

Page 38 - 1-6 Freescale Semiconductor

ColdFire Flash Module (CFM)6-20 Freescale SemiconductorFigure 6-13. Example Program AlgorithmWRITE CFMCLKDREAD CFMCLKDDIVLD SET?WRITE PROGRAM DATAWRIT

Page 39 - 1.1.1 Version 2 ColdFire Core

ColdFire Flash Module (CFM)Freescale Semiconductor 6-216.4.3.4 Flash User Mode Illegal OperationsThe ACCERR flag will be set during a command write se

Page 40 - 1.1.2 System Control Module

ColdFire Flash Module (CFM)6-22 Freescale Semiconductor6.4.5 Master ModeIf the MCU is booted in master mode with an external memory selected as the bo

Page 41 - 1.1.5 Power Management

ColdFire Flash Module (CFM)Freescale Semiconductor 6-236.5.1 Back Door AccessIf the KEYEN bit is set, security can be bypassed by:1. Setting the KEYAC

Page 42 - 1.1.10 UART Modules

ColdFire Flash Module (CFM)6-24 Freescale SemiconductorAll commands are completed CCIF(CFMUSTAT) CCIE(CFMCR)Access error ACCERR(CFMUSTAT)AEIE(CFMCR)Ta

Page 43 - Freescale Semiconductor 1-11

Freescale Semiconductor 7-1Chapter 7 Power ManagementThe power management module (PMM) controls the device’s low-power operation.7.1 FeaturesThe foll

Page 44 - 1.2 MCF5282-Specific Features

Power Management7-2 Freescale Semiconductor7.2.2 Memory Map7.2.3 Register DescriptionsThe following subsection describes the PMM registers.7.2.3.1 Low

Page 45 - Freescale Semiconductor 1-13

Power ManagementFreescale Semiconductor 7-3NOTEOnly fixed (external) interrupt can bring a device out of stop mode. To exitfrom other low-power modes,

Page 46 - 1-14 Freescale Semiconductor

xiv Freescale Semiconductor14.2.12.1 DMA Timer 0 Input (DTIN0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2714.2.12.2 DMA Timer 0 O

Page 47 - ColdFire Core

Power Management7-4 Freescale Semiconductor7.2.3.2 Low-Power Control Register (LPCR)The LPCR controls chip operation and module operation during low-p

Page 48 - 2-2 Freescale Semiconductor

Power ManagementFreescale Semiconductor 7-5NOTEIf LPCR[LPMD] is cleared, then the device stops executing code upon issueof a STOP instruction. However

Page 49

Power Management7-6 Freescale Semiconductor7.3.1.2 Wait ModeWait mode is intended to be used to stop only the CPU and memory clocks until a wakeup eve

Page 50 - 2.2.1 Data Registers (D0–D7)

Power ManagementFreescale Semiconductor 7-77.3.2.3 FlashThe Flash module is in a low-power state if not being accessed. No recovery time is required a

Page 51

Power Management7-8 Freescale Semiconductor7.3.2.8 UART Modules (UART0, UART1, and UART2)In wait and doze modes, the UART may generate an interrupt to

Page 52

Power ManagementFreescale Semiconductor 7-97.3.2.12 Interrupt Controllers (INTC0, INTC1)The interrupt controller is not affected by any of the low-pow

Page 53 - 2.2.5 Program Counter (PC)

Power Management7-10 Freescale Semiconductor7.3.2.17 Clock ModuleIn wait and doze modes, the clocks to the CPU, Flash, and SRAM will be stopped and th

Page 54

Power ManagementFreescale Semiconductor 7-117.3.2.21 Queued Analog-to-Digital Converter (QADC)Setting the queued analog-to-digital converter (QADC) st

Page 55 - 2.3 Functional Description

Power Management7-12 Freescale Semiconductor• Self-wake mechanism. If the SELF-WAKE bit in the MCR is set at the time the FlexCAN enters stop mode, th

Page 56

Power ManagementFreescale Semiconductor 7-13• No host access to the FlexCAN module.• The FlexCAN is neither in halt mode (MCR bit 8), in stop mode (MC

Page 57

Freescale Semiconductor xv15.2.1 DRAM Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-415.2.2 M

Page 58

Power Management7-14 Freescale SemiconductorTable 7-7. CPU and Peripherals in Low-Power ModesModulePeripheral Status1 / Wakeup Capability1“Program” In

Page 59

Power ManagementFreescale Semiconductor 7-154The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-powe

Page 60

Power Management7-16 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 61

Freescale Semiconductor 8-1Chapter 8 System Control Module (SCM)This section details the functionality of the System Control Module (SCM) which provi

Page 62

System Control Module (SCM)8-2 Freescale Semiconductor8.3 Memory Map and Register DefinitionThe memory map for the SCM registers is shown in Table 8-1

Page 63

System Control Module (SCM)Freescale Semiconductor 8-35. Chip SelectsNOTEThis is the list of memory access priorities when viewed from the processorco

Page 64 - 2.3.4 Processor Exceptions

System Control Module (SCM)8-4 Freescale SemiconductorThe physical base address programmed in both copies of the RAMBAR is typically the same value;ho

Page 65

System Control Module (SCM)Freescale Semiconductor 8-58.4.3 Core Reset Status Register (CRSR)The CRSR contains a bit for two of the reset sources to t

Page 66 - 2.3.4.5 Privilege Violation

System Control Module (SCM)8-6 Freescale SemiconductorWhen the core watchdog timer times out and CWCR[CWRI] is programmed for a software reset, aninte

Page 67 - 2.3.4.9 Debug Interrupt

System Control Module (SCM)Freescale Semiconductor 8-78.4.5 Core Watchdog Service Register (CWSR)The software watchdog service sequence must be perfor

Page 68 - 2.3.4.15 Reset Exception

xvi Freescale SemiconductorChapter 17Fast Ethernet Controller (FEC)17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 69

System Control Module (SCM)8-8 Freescale SemiconductorFigure 8-6. Arbiter Module Functions8.5.1 OverviewThe basic functionality is that of a 4-port, p

Page 70

System Control Module (SCM)Freescale Semiconductor 8-98.5.2 Arbitration AlgorithmsThere are two modes of arbitration: fixed and round-robin. This sect

Page 71

System Control Module (SCM)8-10 Freescale Semiconductor 31 26 25 24 23 22 21 20 19 18 17 16Field — M2_P_EN BCR24BIT M3_PRTY M2_PRTY M0_PRTY M1_PRTYRes

Page 72 - 2.3.5.1 Timing Assumptions

System Control Module (SCM)Freescale Semiconductor 8-11The initial state of the master priorities is M3 > M2 > M1 > M0. System software shoul

Page 73

System Control Module (SCM)8-12 Freescale Semiconductor8.6.2 FeaturesEach bus transfer can be classified by its privilege level and the reference type

Page 74

System Control Module (SCM)Freescale Semiconductor 8-138.6.3.1 Master Privilege Register (MPR)The MPR specifies the access privilege level associated

Page 75

System Control Module (SCM)8-14 Freescale Semiconductorand writes. Each PACR follows the format illustrated in Figure 8-9. For a list of PACRs and the

Page 76

System Control Module (SCM)Freescale Semiconductor 8-15At reset, these on-chip modules are configured to have only supervisor read/write access capabi

Page 77

System Control Module (SCM)8-16 Freescale SemiconductorAt reset, these on-chip modules are configured to have only supervisor read/write access capabi

Page 78

System Control Module (SCM)Freescale Semiconductor 8-17Table 8-14. GPACR Address SpaceRegister Space Protected(IPSBAR Offset)Modules ProtectedGPACR0 0

Page 79

Freescale Semiconductor xvii17.5.2.1 Hardware Controlled Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3017.5.3 User Initializ

Page 80

System Control Module (SCM)8-18 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 81 - Table 3-1. EMAC Memory Map

Freescale Semiconductor 9-1Chapter 9 Clock ModuleThe clock module configures the device for one of several clocking methods. Clocking modes includein

Page 82

Clock Module9-2 Freescale Semiconductor9.3 Low-power Mode OperationThis subsection describes the operation of the clock module in low-power and halted

Page 83 - 3.2.2 Mask Register (MASK)

Clock ModuleFreescale Semiconductor 9-3.Figure 9-1. Clock Module Block DiagramCLKOUTXTALEXTERNAL CLOCKOSCPLLREFREFERENCECLOCKPLLMFD PLLMODELOCENCLKMOD

Page 84

Clock Module9-4 Freescale SemiconductorFigure 9-2. PLL Block Diagram9.5 Signal DescriptionsThe clock module signals are summarized in Table 9-2 and a

Page 85 - Description.”

Clock ModuleFreescale Semiconductor 9-59.5.2 XTALThis output is an internal oscillator connection to the external crystal.9.5.3 CLKOUTThis output refl

Page 86 - 3.3 Functional Description

Clock Module9-6 Freescale Semiconductor9.6.2 Register DescriptionsThis subsection provides a description of the clock module registers.9.6.2.1 Synthes

Page 87

Clock ModuleFreescale Semiconductor 9-714–12 MFD Multiplication Factor Divider. Contain the binary value of the divider in the PLL feedback loop. The

Page 88 - 3.3.1.1 Rounding

Clock Module9-8 Freescale Semiconductor9.6.2.2 Synthesizer Status Register (SYNSR)The SYNSR is a read-only register that can be read at any time. Writ

Page 89

Clock ModuleFreescale Semiconductor 9-9Table 9-5. SYNSR Field DescriptionsBit(s) Name Description7 PLLMODE Clock mode bit. The PLLMODE bit is configur

Page 90 - 3.3.1.3 MULS/MULU

xviii Freescale Semiconductor19.3.2 Free-Running Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-619.3.3 Ti

Page 91 - Three-cycle

Clock Module9-10 Freescale Semiconductor9.7 Functional DescriptionThis subsection provides a functional description of the clock module.9.7.1 System C

Page 92 - 3.3.5 MAC Opcodes

Clock ModuleFreescale Semiconductor 9-11CAUTIONXTAL must be tied low in external clock mode when reset is asserted. If itis not, clocks could be suspe

Page 93

Clock Module9-12 Freescale SemiconductorThe RFD is not in the feedback loop of the PLL, so changing the RFD divisor does not affect PLLoperation.Figur

Page 94

Clock ModuleFreescale Semiconductor 9-13The feedback clock comes from one of the following:• CLKOUT in 1:1 PLL mode• VCO output divided by two if CLKO

Page 95

Clock Module9-14 Freescale SemiconductorThe lock detect function uses two counters. One is clocked by the reference and the other is clocked by thePLL

Page 96

Clock ModuleFreescale Semiconductor 9-159.7.4.7 PLL Loss of Lock ResetIf the LOLRE bit in the SYNCR is set, a loss of lock condition asserts reset. Re

Page 97

Clock Module9-16 Freescale SemiconductorA special loss-of-clock condition occurs when both the reference and the PLL fail. The failures may besimultan

Page 98 - 3-20 Freescale Semiconductor

Clock ModuleFreescale Semiconductor 9-17NRM 0 0 0 Off On 0 Lose lock Regain NRM ‘LK 1 ‘LC Block LOCKS from being clearedLose reference clock or no loc

Page 99 - Chapter 4

Clock Module9-18 Freescale SemiconductorNRM 001OnOnX — — NRM ‘LK 1 ‘LCLose lock or clock RESET — — — Reset immediatelyNRM 1 0 0 Off Off 0 Lose lock, f

Page 100 - 4-2 Freescale Semiconductor

Clock ModuleFreescale Semiconductor 9-19NRM 101OnOnX — — NRM ‘LK 1 ‘LCLose lock or clock RESET — — — Reset immediatelyNRM 1 1 X Off X X Lose lock, f.b

Page 101 - Table 4-1. Cache Memory Map

Freescale Semiconductor xix20.8.3 Pulse Accumulator Input (PAIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2220.8.4 Time

Page 102

Clock Module9-20 Freescale SemiconductorSCM 1 0 0 On On 1 — — SCM 0 0 1Lose reference clockSCMNote: PLL = PLL enabled during STOP mode. PLL = On when

Page 103

Freescale Semiconductor 10-1Chapter 10 Interrupt Controller ModulesThis section details the functionality for the interrupt controllers (INTC0, INTC1

Page 104

Interrupt Controller Modules10-2 Freescale SemiconductorSection 2.3.3.1, “Exception Stack Frame Definition” for more information on the stack frame fo

Page 105 - 4.3 Functional Description

Interrupt Controller ModulesFreescale Semiconductor 10-3The level and priority is fully programmable for all sources except interrupt sources 1–7. Int

Page 106 - 4.3.4 Reset

Interrupt Controller Modules10-4 Freescale Semiconductor10.1.1.2 Interrupt PrioritizationAs an active request is detected, it is translated into the p

Page 107 - . CLNF Bits

Interrupt Controller ModulesFreescale Semiconductor 10-5The registers and their locations are defined in Table 10-3. The offsets listed start from the

Page 108

Interrupt Controller Modules10-6 Freescale Semiconductor10.3 Register Descriptions10.3.1 Interrupt Pending Registers (IPRHn, IPRLn) The IPRHn and IPRL

Page 109 - Static RAM (SRAM)

Interrupt Controller ModulesFreescale Semiconductor 10-7. 10.3.2 Interrupt Mask Register (IMRHn, IMRLn)The IMRHn and IMRLn registers are each 32 bits

Page 110

Interrupt Controller Modules10-8 Freescale Semiconductor. .31 16Field INT_MASK[63:48]Reset 1111_1111_1111_1111R/W R/W15 0Field INT_MASK[47:32]Reset 11

Page 111 - 5.3.2 SRAM Initialization

Interrupt Controller ModulesFreescale Semiconductor 10-9NOTEIf an interrupt source is being masked in the interrupt controller maskregister (IMR) or a

Page 112 - 5.3.4 Power Management

How to Reach Us:Home Page:www.freescale.comWeb Support:http://www.freescale.com/supportUSA/Europe or Locations Not Listed:Freescale Semiconductor, Inc

Page 113 - ColdFire Flash Module (CFM)

xx Freescale Semiconductor22.4.1.3 Command RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1222.4.2 Baud Rate S

Page 114 - 6.2 Block Diagram

Interrupt Controller Modules10-10 Freescale Semiconductor. 31 16Field INTFRCH[63:48]Reset 0000_0000_0000_0000R/W R/W15 0Field INTFRCH[47:32]Reset 0000

Page 115 - Figure 6-1. CFM Block Diagram

Interrupt Controller ModulesFreescale Semiconductor 10-1110.3.4 Interrupt Request Level Register (IRLRn)This 7-bit register is updated each machine cy

Page 116 - 6.3 Memory Map

Interrupt Controller Modules10-12 Freescale Semiconductor10.3.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63))Each ICRnx specifies the interru

Page 117 - 6.3.1 CFM Configuration Field

Interrupt Controller ModulesFreescale Semiconductor 10-1310.3.6.1 Interrupt SourcesTable 10-13 and Table 10-14 list the interrupt sources for each int

Page 118 - 15 9876543210

Interrupt Controller Modules10-14 Freescale Semiconductor23 FECNote:Not usedon MCF5214& MCF5216X_INTF Transmit frame interrupt Write X_INTF = 124

Page 119 - 6.3.3 CFM Registers

Interrupt Controller ModulesFreescale Semiconductor 10-1556 PIT1 PIF PIT interrupt flag Write PIF = 1 of write PMR57 PIT2 PIF PIT interrupt flag Write

Page 120 - 6.3.4 Register Descriptions

Interrupt Controller Modules10-16 Freescale Semiconductor10.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)The eight IACK registers c

Page 121

Interrupt Controller ModulesFreescale Semiconductor 10-17service routine, and if there are additional active interrupt sources, the current interrupt

Page 122 - 31 30 29 16

Interrupt Controller Modules10-18 Freescale SemiconductorNOTEThe wakeup mask level taken from LPICR[6:4] is adjusted by hardware toallow a level 7 IRQ

Page 123

Freescale Semiconductor 11-1Chapter 11 Edge Port Module (EPORT)11.1 IntroductionThe edge port module (EPORT) has seven external interrupt pins, IRQ7–

Page 124

Freescale Semiconductor xxi23.5.1.1 Setting up the UART to Generate Core Interrupts . . . . . . . . . . . . . 23-2623.5.1.2 Setting up the UART to Re

Page 125

Edge Port Module (EPORT)11-2 Freescale SemiconductorTable 11-1. Edge Port Module Operation in Low-power ModesIn wait and doze modes, the EPORT module

Page 126

Edge Port Module (EPORT)Freescale Semiconductor 11-311.4 Memory Map and RegistersThis subsection describes the memory map and register structure.11.4.

Page 127

Edge Port Module (EPORT)11-4 Freescale Semiconductor11.4.2.2 EPORT Data Direction Register (EPDDR)Table 11-3. EPPAR Field DescriptionsBit(s) Name Desc

Page 128 - 6.4 CFM Operation

Edge Port Module (EPORT)Freescale Semiconductor 11-511.4.2.3 Edge Port Interrupt Enable Register (EPIER)11.4.2.4 Edge Port Data Register (EPDR)765 432

Page 129 - 6.4.2 Write Operations

Edge Port Module (EPORT)11-6 Freescale Semiconductor11.4.2.5 Edge Port Pin Data Register (EPPDR)11.4.2.6 Edge Port Flag Register (EPFR)765 43210Field

Page 130 - 6-18 Freescale Semiconductor

Freescale Semiconductor 12-1Chapter 12 Chip Select ModuleThis chapter describes the chip select module, including the operation and programming model

Page 131 - 6.4.3.3 Flash Valid Commands

Chip Select Module12-2 Freescale SemiconductorTable 12-2. Byte Enables/Byte Write Enable Signal SettingsTransfer Size Port Size A1 A0BS3 BS2 BS1 BS0D[

Page 132 - 6-20 Freescale Semiconductor

Chip Select ModuleFreescale Semiconductor 12-312.3 Chip Select OperationEach chip select has a dedicated set of registers for configuration and contro

Page 133 - 6.4.4 Stop Mode

Chip Select Module12-4 Freescale Semiconductorbetween the data bus and the external byte strobe control lines (BS[3:0]). Note that all byte lanes ared

Page 134 - 6.5 Flash Security Operation

Chip Select ModuleFreescale Semiconductor 12-5Table 12-5. Chip Select RegistersIPSBAR Offset[31:24] [23:16] [15:8] [7:0]0x00_0080 Chip select address

Page 135 - 6.7 Interrupts

xxii Freescale Semiconductor25.3.1.3 Fields for Standard Format Frames . . . . . . . . . . . . . . . . . . . . . . . . . 25-725.3.2 Message Buffer Me

Page 136

Chip Select Module12-6 Freescale Semiconductor12.4.1 Chip Select Module RegistersThe chip select module is programmed through the chip select address

Page 137 - Power Management

Chip Select ModuleFreescale Semiconductor 12-712.4.1.3 Chip Select Control Registers (CSCR0–CSCR6)Each CSCR, shown in Figure 12-4, controls the auto-a

Page 138 - 7.2.3 Register Descriptions

Chip Select Module12-8 Freescale SemiconductorFigure 12-4. Chip Select Control Registers (CSCRn)Table 12-8 describes CSCRn fields.15 14 13 10 9 8 7 6

Page 139 - Table 7-3. XLPM_IPL Settings

Chip Select ModuleFreescale Semiconductor 12-93 BSTW Burst write enable. Specifies whether burst writes are used for memory associated with each CSn.0

Page 140 - 7 6543210

Chip Select Module12-10 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 141 - 7.3 Functional Description

Freescale Semiconductor 13-1Chapter 13 External Interface Module (EIM)This chapter describes data-transfer operations, error conditions, and reset op

Page 142 - 7-6 Freescale Semiconductor

External Interface Module (EIM)13-2 Freescale Semiconductor13.3 Bus CharacteristicsThe device uses its system clock to generate CLKOUT. Therefore, the

Page 143 - 7.3.2.6 Chip Select Module

External Interface Module (EIM)Freescale Semiconductor 13-3Figure 13-2. Connections for External Memory Port SizesThe timing relationship of chip sele

Page 144 - C Module

External Interface Module (EIM)13-4 Freescale SemiconductorBasic operation of the bus is a three-clock bus cycle:1. During the first clock, the addres

Page 145 - 7.3.2.15 Reset Controller

External Interface Module (EIM)Freescale Semiconductor 13-5Figure 13-4. Data Transfer State Transition DiagramTable 13-3 describes the states as they

Page 146 - 7.3.2.19 Watchdog Timer

Freescale Semiconductor xxiii26.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 147 - 7.3.2.23 FlexCAN

External Interface Module (EIM)13-6 Freescale SemiconductorNOTEAn external device has at most two CLKOUT cycles after the start of S4 tothree-state th

Page 148 - 7-12 Freescale Semiconductor

External Interface Module (EIM)Freescale Semiconductor 13-7Figure 13-6. Basic Read Bus CycleNote the following characteristics of a basic read:• In S3

Page 149 - 7.3.2.26 JTAG

External Interface Module (EIM)13-8 Freescale SemiconductorThe write cycle timing diagram is shown in Figure 13-8.Figure 13-8. Basic Write Bus CycleTa

Page 150

External Interface Module (EIM)Freescale Semiconductor 13-9Figure 13-10. Write Cycle with Fast Termination13.4.6 Back-to-Back Bus CyclesThe processor

Page 151 - Freescale Semiconductor 7-15

External Interface Module (EIM)13-10 Freescale Semiconductor13.4.7 Burst CyclesThe processor can be programmed to initiate burst cycles if its transfe

Page 152 - 7-16 Freescale Semiconductor

External Interface Module (EIM)Freescale Semiconductor 13-11Figure 13-12. Line Read Burst (2-1-1-1), External TerminationFigure 13-13 shows timing whe

Page 153 - System Control Module (SCM)

External Interface Module (EIM)13-12 Freescale Semiconductor.Figure 13-14. Line Read Burst (3-2-2-2), External TerminationFigure 13-15 shows a burst-i

Page 154 - [31:24] [23:16] [15:8] [7:0]

External Interface Module (EIM)Freescale Semiconductor 13-13 Figure 13-16. Line Write Burst (2-1-1-1), Internal/External Termination Figure 13-17 show

Page 155

External Interface Module (EIM)13-14 Freescale SemiconductorFigure 13-18. Line Write Burst-Inhibited13.5 Misaligned OperandsBecause operands can resid

Page 156 - 15 10 9 8 0

External Interface Module (EIM)Freescale Semiconductor 13-15Figure 13-20. Example of a Misaligned Word Transfer (32-Bit Port)Transfer 1Transfer 2—Byte

Page 157

xxiv Freescale Semiconductor27.6.3 Boot Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-927.

Page 158 - 765 32 1 0

External Interface Module (EIM)13-16 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 159 - 8.5 Internal Bus Arbitration

Freescale Semiconductor 14-1Chapter 14 Signal DescriptionsThis chapter describes the processor’s external signals. It includes an alphabetical listin

Page 160 - MCF5214/16

Signal Descriptions14-2 Freescale SemiconductorFigure 14-1. MCF5282 Block Diagram with Signal InterfacesTDO/DSOTDI/DSITMS/BKPTTCLKInterfaceChipUART1Se

Page 161 - 8.5.2 Arbitration Algorithms

Signal DescriptionsFreescale Semiconductor 14-3Table 14-1 lists the external signals grouped by functionality.NOTEThe primary functionality of a pin i

Page 162 - 15 14 13 12 11 8 7 0

Signal Descriptions14-4 Freescale SemiconductorSDRAM write enable DRAMW Asserted to signify that a DRAM write cycle is underway. Negated to indicate a

Page 163 - 8.6.1 Overview

Signal DescriptionsFreescale Semiconductor 14-5Receive data valid ERXDV Asserted to indicate that the PHY has valid nibbles present on the MII.I 14-24

Page 164 - 8.6.2 Features

Signal Descriptions14-6 Freescale SemiconductorClear-to-send UCTS[1:0] Signals UART that it can begin data transmission.I 14-26Request to send URTS[1:

Page 165

Signal DescriptionsFreescale Semiconductor 14-7Table 14-2 lists signals in alphabetical order by abbreviated name.Development serialinput/Test dataDSI

Page 166 - 76 432 0

Signal Descriptions14-8 Freescale SemiconductorTable 14-2. MCF5282 Alphabetical Signal IndexAbbreviation Function I/OA[23:0] Define the address of ext

Page 167

Signal DescriptionsFreescale Semiconductor 14-9EMDC Provides a timing reference to the PHY for data transfers on the EMDIO signal.Note: Not available

Page 168

Freescale Semiconductor xxv28.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 169 - Modules Protected

Signal Descriptions14-10 Freescale SemiconductorJTAG_EN Selects between multiplexed debug module and JTAG signals at reset.IOEIndicates when an extern

Page 170 - 8-18 Freescale Semiconductor

Signal DescriptionsFreescale Semiconductor 14-11TEST Reserved, should be connected to VSS. ITCK JTAG test logic clock. ITIPAsserted to indicate that a

Page 171

Signal Descriptions14-12 Freescale SemiconductorExternal Memory Interface and PortsC6:B6:A5 A[23:21] PF[7:5] CS[6:4] Address bus O YesC4:B4:A4:B3:A3 A

Page 172 - 9.4 Block Diagram

Signal DescriptionsFreescale Semiconductor 14-13External Interrupts PortB15:B16:C14:C15:C16: D14:D15IRQ[7:1] PNQ[7:1] — External interrupt request I/O

Page 173 - Freescale Semiconductor 9-3

Signal Descriptions14-14 Freescale SemiconductorA7:B7:C7 PEL[7:5] — — GPIO I/O —D10 PEL4 — — GPIO I/O —A9:B9:C9 PEL[3:1] — — GPIO I/O —B8 NC — — No co

Page 174 - 9.5 Signal Descriptions

Signal DescriptionsFreescale Semiconductor 14-15J16 DTIN1 PTD3 URTS1/ URTS0U1/U0 Request to Send I/O —J15 DTOUT1 PTD2 URTS1/ URTS0U1/U0 Request to Sen

Page 175 - Register Name Access

Signal Descriptions14-16 Freescale SemiconductorJ14 DTIN0 PTD1 UCTS1/ UCTS0Timer 0 in I/O —J13 DTOUT0 PTD0 UCTS1/ UCTS0Timer 0 out I/O —Queued Analog-

Page 176 - 76 5 4 3210

Signal DescriptionsFreescale Semiconductor 14-1714.1.1 Single-Chip ModeIn single-chip mode, signals default to GPIO inputs after a system reset. Table

Page 177

Signal Descriptions14-18 Freescale Semiconductor14.1.2 External Boot ModeWhen booting from external memory, the address bus, data bus, and bus control

Page 178

Signal DescriptionsFreescale Semiconductor 14-1914.2.1.1 Address Bus (A[23:0])The 24 dedicated address signals, A[23:0], define the address of externa

Page 179

xxvi Freescale Semiconductor28.9.7.2 Error Resulting from Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6728.10Interrupts . .

Page 180 - 9.7 Functional Description

Signal Descriptions14-20 Freescale Semiconductor14.2.1.6 Transfer Error Acknowledge (TEA)This signal indicates an error condition exists for the bus t

Page 181 - 9.7.4 PLL Operation

Signal DescriptionsFreescale Semiconductor 14-2114.2.1.10 Transfer In Progress (TIP)The TIP output is asserted indicating a bus transfer is in progres

Page 182 - 9-12 Freescale Semiconductor

Signal Descriptions14-22 Freescale Semiconductor14.2.2.5 SDRAM Clock Enable (SCKE)This output is the SDRAM clock enable. This pin is configured as GPI

Page 183 - 9.7.4.5 PLL Lock Detection

Signal DescriptionsFreescale Semiconductor 14-2314.2.5 External Interrupt Signals14.2.5.1 External Interrupts (IRQ[7:1])These inputs are the external

Page 184 - ≠ Feedback Count

Signal Descriptions14-24 Freescale Semiconductor14.2.6.6 Collision (ECOL)The ECOL input is asserted upon detection of a collision and remains asserted

Page 185 - 9.7.4.9 Loss of Clock Reset

Signal DescriptionsFreescale Semiconductor 14-2514.2.6.14 Receive Error (ERXER)ERXER is an input signal which when asserted along with ERXDV signals t

Page 186

Signal Descriptions14-26 Freescale Semiconductor14.2.9 I2C SignalsThe I2C module acts as a two-wire, bidirectional serial interface between the proces

Page 187

Signal DescriptionsFreescale Semiconductor 14-2714.2.10.4 Request-to-Send (URTS[1:0])The URTS[1:0] signals are automatic request to send outputs from

Page 188

Signal Descriptions14-28 Freescale SemiconductorThis pin can also be configured as GPIO PTD3, secondary function URTS1, or secondary function URTS0.14

Page 189

Signal DescriptionsFreescale Semiconductor 14-2914.2.13.3 QADC Analog Input (AN2/ANY)This PQB signal is the direct analog input AN2. When using extern

Page 190

Freescale Semiconductor xxvii30.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR) . . . . . . . . . . . . 30-1330.4.7 Trigger Definition Regis

Page 191

Signal Descriptions14-30 Freescale Semiconductor14.2.14.2 Development Serial Clock/Test Reset (DSCLK/TRST)Debug mode operation: DSCLK is selected. DSC

Page 192

Signal DescriptionsFreescale Semiconductor 14-3114.2.14.7 Debug Data (DDATA[3:0])Debug data signals (DDATA[3:0]) display captured processor addresses,

Page 193

Signal Descriptions14-32 Freescale Semiconductor14.2.16 Power and Reference SignalsThese signals provide system power, ground and references to the de

Page 194 - 10.2 Memory Map

Freescale Semiconductor 15-1Chapter 15 Synchronous DRAM Controller ModuleThis chapter describes configuration and operation of the synchronous DRAM (

Page 195

Synchronous DRAM Controller Module15-2 Freescale SemiconductorFigure 15-1. Synchronous DRAM Controller Block Diagram The DRAM controller’s major compo

Page 196 - 10.3 Register Descriptions

Synchronous DRAM Controller ModuleFreescale Semiconductor 15-315.2 SDRAM Controller OperationBy running synchronously with the system clock, SDRAM can

Page 197

Synchronous DRAM Controller Module15-4 Freescale Semiconductor15.2.1 DRAM Controller SignalsTable 15-2 describes the behavior of DRAM signals in synch

Page 198

Synchronous DRAM Controller ModuleFreescale Semiconductor 15-5Table 15-4 describes DCR fields.15 14 13 12 11 10 9 8 0Field — NAM COC IS RTIM RCReset U

Page 199

Synchronous DRAM Controller Module15-6 Freescale Semiconductor15.2.2.2 DRAM Address and Control Registers (DACR0/DACR1)The DACRn registers, shown in F

Page 200

Synchronous DRAM Controller ModuleFreescale Semiconductor 15-710–8 CBM Command and bank MUX [2:0]. Because different SDRAM configurations cause the co

Page 201

xxviii Freescale Semiconductor31.5.3.1 External Test Instruction (EXTEST) . . . . . . . . . . . . . . . . . . . . . . . . . 31-731.5.3.2 IDCODE Instr

Page 202

Synchronous DRAM Controller Module15-8 Freescale Semiconductor15.2.2.3 DRAM Controller Mask Registers (DMR0/DMR1)The DMRn, Figure 15-4, includes mask

Page 203 - 10.3.6.1 Interrupt Sources

Synchronous DRAM Controller ModuleFreescale Semiconductor 15-915.2.3 General Synchronous Operation GuidelinesTo reduce system logic and to support a v

Page 204

Synchronous DRAM Controller Module15-10 Freescale SemiconductorTable 15-8. Processor to SDRAM Interface (8-Bit Port, 9-Column Address Lines)Processor

Page 205

Synchronous DRAM Controller ModuleFreescale Semiconductor 15-11Table 15-13. Processor to SDRAM Interface (16-Bit Port, 8-Column Address Lines)Processo

Page 206

Synchronous DRAM Controller Module15-12 Freescale SemiconductorTable 15-18. Processor to SDRAM Interface (16-Bit Port, 13-Column-Address Lines)Proces

Page 207

Synchronous DRAM Controller ModuleFreescale Semiconductor 15-1315.2.3.2 SDRAM Byte Strobe ConnectionsFigure 15-5 shows SDRAM connections for port siz

Page 208 - 10-18 Freescale Semiconductor

Synchronous DRAM Controller Module15-14 Freescale SemiconductorNote that in synchronous operation, burst mode and address incrementing during burst cy

Page 209

Synchronous DRAM Controller ModuleFreescale Semiconductor 15-15Figure 15-7. Burst Write SDRAM AccessAccesses in synchronous burst page mode always cau

Page 210

Synchronous DRAM Controller Module15-16 Freescale SemiconductorFigure 15-8 shows the auto-refresh timing. In this case, there is an SDRAM access when

Page 211 - Bits 15–8 Bits 7–0 Access

Synchronous DRAM Controller ModuleFreescale Semiconductor 15-17Figure 15-9. Self-Refresh Operation15.2.4 Initialization SequenceSynchronous DRAMs have

Page 212 - 765 43210

Freescale Semiconductor xxixAppendix ARegister Memory MapAppendix BRevision HistoryB.1 Changes Between Rev. 0 and Rev. 0.1 . . . . . . . . . . . . .

Page 213

Synchronous DRAM Controller Module15-18 Freescale Semiconductor15.2.4.1 Mode Register SettingsIt is possible to configure the operation of SDRAMs, nam

Page 214

Synchronous DRAM Controller ModuleFreescale Semiconductor 15-19Table 15-25. SDRAM Example SpecificationsParameter SpecificationSpeed grade (-8E) 40 M

Page 215

Synchronous DRAM Controller Module15-20 Freescale Semiconductor15.3.1 SDRAM Interface ConfigurationTo interface this component to the DRAM controller,

Page 216

Synchronous DRAM Controller ModuleFreescale Semiconductor 15-21Figure 15-12. SDRAM Configuration The DACRs should be programmed as shown in Figure 15-

Page 217 - 12.3 Chip Select Operation

Synchronous DRAM Controller Module15-22 Freescale Semiconductor15.3.4 DMR InitializationAgain, in this example only the second 512-Kbyte block of each

Page 218 - 12.4 Chip Select Registers

Synchronous DRAM Controller ModuleFreescale Semiconductor 15-2315.3.5 Mode Register InitializationWhen DACR[IMRS] is set, a bus cycle initializes the

Page 219

Synchronous DRAM Controller Module15-24 Freescale SemiconductorPower-Up Sequence:move.w #0x0026, d0//Initialize DCRmove.w d0, DCRmove.l #0xFF880300, d

Page 220 - 31 1615 9876543210

Freescale Semiconductor 16-1Chapter 16 DMA Controller ModuleThis chapter describes the direct memory access (DMA) controller module. It provides an o

Page 221

DMA Controller Module16-2 Freescale SemiconductorNOTEThroughout this chapter “external request” and DREQ are used to refer to aDMA request from one of

Page 222 - 15 14 13 10 9 8 7 6 5 4 3 2 0

DMA Controller ModuleFreescale Semiconductor 16-331–16 — Reserved. Should be cleared.15–0 DMACn DMA Channel n. Each four bit field defines the logical

Page 223

OverviewColdFire CoreEnhanced Multiply-Accumulate Unit (EMAC)CacheStatic RAM (SRAM)ColdFire Flash Module (CFM)Power ManagementSystem Control Module (S

Page 224 - 12-10 Freescale Semiconductor

xxx Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 225

DMA Controller Module16-4 Freescale Semiconductor16.3 DMA Transfer OverviewThe DMA module can transfer data faster than the ColdFire core. The term “d

Page 226 - 13.4 Data Transfer Operation

DMA Controller ModuleFreescale Semiconductor 16-516.4.1 Source Address Registers (SAR0–SAR3)SARn, shown in Figure 16-4, contains the address from whic

Page 227 - 13.4.1 Bus Cycle Execution

DMA Controller Module16-6 Freescale SemiconductorNOTEThe backdoor enable bit must be set in both the core and SCM in order toenable backdoor accesses

Page 228

DMA Controller ModuleFreescale Semiconductor 16-716.4.3 Byte Count Registers (BCR0–BCR3)BCRn, shown in Figure 16-6 and Figure 16-7, hold the number of

Page 229 - Table 13-3. Bus Cycle States

DMA Controller Module16-8 Freescale SemiconductorTable 16-3 describes DCRn fields. 31 30 29 28 27 25 24 23 22 21 20 19 18 17 16Field INT EEXT CS AA BW

Page 230 - 13.4.3 Read Cycle

DMA Controller ModuleFreescale Semiconductor 16-927–25 BWC Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count r

Page 231 - 13.4.4 Write Cycle

DMA Controller Module16-10 Freescale Semiconductor16.4.5 DMA Status Registers (DSR0–DSR3)In response to an event, the DMA controller writes to the app

Page 232

DMA Controller ModuleFreescale Semiconductor 16-1116.5 DMA Controller Module Functional DescriptionIn the following discussion, the term “DMA request”

Page 233

DMA Controller Module16-12 Freescale Semiconductor16.5.2 Data Transfer ModesEach channel supports dual-address transfers, described in the next sectio

Page 234 - 13.4.7 Burst Cycles

DMA Controller ModuleFreescale Semiconductor 16-13peripheral device or memory, the source address is the starting address of the data block. This can

Page 235

Freescale Semiconductor xxxiAbout This BookThe primary objective of this user’s manual is to define the functionality of the MCF5282 processor for use

Page 236

DMA Controller Module16-14 Freescale SemiconductorIf DSIZE is another size, data writes are optimized to write the largest size allowed based on the a

Page 237

Freescale Semiconductor 17-1Chapter 17 Fast Ethernet Controller (FEC)17.1 IntroductionThis chapter provides a feature-set overview, a functional bloc

Page 238 - 13.5 Misaligned Operands

Fast Ethernet Controller (FEC)17-2 Freescale SemiconductorFigure 17-1. FEC Block DiagramThe descriptor controller is a RISC-based controller providing

Page 239 - 31 24 23 16 15 8 7 0

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-3You control the FEC by writing into control registers located in each block. The CSR (contro

Page 240 - 13-16 Freescale Semiconductor

Fast Ethernet Controller (FEC)17-4 Freescale Semiconductor17.2 Modes of OperationThe primary operational modes are described in this section.17.2.1 Fu

Page 241

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-517.3 External Signal DescriptionTable 17-1 describes the various FEC signals, as well as ind

Page 242 - 14-2 Freescale Semiconductor

Fast Ethernet Controller (FEC)17-6 Freescale Semiconductor• Control/status registers• Event/statistic counters held in the MIB blockTable 17-2 defines

Page 243

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-717.4.1 MIB Block Counters Memory MapThe MIB counters memory map (Table 17-4) defines the loc

Page 244

Fast Ethernet Controller (FEC)17-8 Freescale Semiconductor0x1254 Frames transmitted with multiple collisions (IEEE_T_MCOL)0x1258 Frames transmitted af

Page 245

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-917.4.2 Ethernet Interrupt Event Register (EIR)When an event occurs that sets a bit in EIR, a

Page 246

xxxii Freescale Semiconductor• User’s manuals — These books provide details about individual ColdFire implementations and are intended to be used in c

Page 247

Fast Ethernet Controller (FEC)17-10 Freescale Semiconductor17.4.3 Interrupt Mask Register (EIMR)The EIMR register controls which interrupt events are

Page 248

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-1117.4.4 Receive Descriptor Active Register (RDAR)RDAR is a command register, written by the

Page 249

Fast Ethernet Controller (FEC)17-12 Freescale Semiconductor17.4.5 Transmit Descriptor Active Register (TDAR)The TDAR is a command register which the u

Page 250

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-1317.4.7 MII Management Frame Register (MMFR)The MMFR is user-accessible and does not reset t

Page 251

Fast Ethernet Controller (FEC)17-14 Freescale SemiconductorTo perform a read or write operation on the MII Management Interface, write the MMFR regist

Page 252

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-1517.4.8 MII Speed Control Register (MSCR)The MSCR provides control of the MII clock (FEC_MDC

Page 253

Fast Ethernet Controller (FEC)17-16 Freescale SemiconductorThe MIBC is a read/write register controlling and observing the state of the MIB block. Use

Page 254 - C Serial clock I/O Ye s

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-1717.4.11 Transmit Control Register (TCR)TCR is read/write and configures the transmit block.

Page 255

Fast Ethernet Controller (FEC)17-18 Freescale Semiconductor17.4.12 Physical Address Lower Register (PALR)PALR contains the lower 32 bits (bytes 0,1,2,

Page 256

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-1917.4.13 Physical Address Upper Register (PAUR)PAUR contains the upper 16 bits (bytes 4 and

Page 257 - 14.1.1 Single-Chip Mode

Freescale Semiconductor 1-1Chapter 1 OverviewThis chapter provides an overview of the microprocessor features, including the major functionalcomponen

Page 258 - 14.2 External Signals

Fast Ethernet Controller (FEC)17-20 Freescale Semiconductor17.4.15 Descriptor Individual Upper Address Register (IAUR)IAUR contains the upper 32 bits

Page 259 - 14.2.1.4 Output Enable (OE)

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-2117.4.17 Descriptor Group Upper Address Register (GAUR)GAUR contains the upper 32 bits of th

Page 260 - 14.2.1.9 Transfer Start (TS)

Fast Ethernet Controller (FEC)17-22 Freescale Semiconductor17.4.19 Transmit FIFO Watermark Register (TFWR)The TFWR controls the amount of data require

Page 261 - Freescale Semiconductor 14-21

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-2317.4.21 FIFO Receive Start Register (FRSR)FRSR indicates the starting address of the receiv

Page 262 - 14-22 Freescale Semiconductor

Fast Ethernet Controller (FEC)17-24 Freescale Semiconductor17.4.23 Transmit Buffer Descriptor Ring Start Registers (ETSDR)ETSDR provides a pointer to

Page 263 - Freescale Semiconductor 14-23

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-25To minimize bus utilization (descriptor fetches), it is recommended that EMRBR be greater t

Page 264 - 14-24 Freescale Semiconductor

Fast Ethernet Controller (FEC)17-26 Freescale SemiconductorSoftware produces buffers by allocating/initializing memory and initializing buffer descrip

Page 265 - 14.2.8 FlexCAN Signals

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-2717.5.1.1.2 Driver/DMA Operation with Receive BDsUnlike transmit, the length of the receive

Page 266 - 14.2.10 UART Module Signals

Fast Ethernet Controller (FEC)17-28 Freescale SemiconductorTable 17-29. Receive Buffer Descriptor Field DefinitionsWord Field DescriptionOffset + 0 15

Page 267 - 14.2.12 DMA Timer Signals

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-29NOTEWhen the software driver sets an E bit in one or more receive descriptors, the driver s

Page 268 - 14-28 Freescale Semiconductor

Overview1-2 Freescale Semiconductor— Memory-based flexible descriptor rings— Media-independent interface (MII) to transceiver (PHY)• FlexCAN 2.0B Modu

Page 269 - 14.2.14 Debug Support Signals

Fast Ethernet Controller (FEC)17-30 Freescale SemiconductorNOTEAfter the software driver has set up the buffers for a frame, it should set up the corr

Page 270 - 14.2.14.6 Test Clock (TCLK)

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-31Other registers reset when the ECR[ETHER_EN] bit is cleared (which is accomplished by a har

Page 271 - 14.2.15 Test Signals

Fast Ethernet Controller (FEC)17-32 Freescale Semiconductor17.5.4 Microcontroller InitializationIn the FEC, the descriptor control RISC initializes so

Page 272 - 14-32 Freescale Semiconductor

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-33The 7-wire serial mode interface (RCR[MII_MODE] cleared) is generally referred to as AMD mo

Page 273

Fast Ethernet Controller (FEC)17-34 Freescale SemiconductorIf a collision occurs during transmission of the frame (half duplex mode), the Ethernet con

Page 274

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-3517.5.8 FEC Frame ReceptionThe FEC receiver works with almost no intervention from the host

Page 275 - Table 15-1. SDRAM Commands

Fast Ethernet Controller (FEC)17-36 Freescale Semiconductorgroup address is determined by the I/G bit in the destination address field. A flowchart fo

Page 276

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-37Figure 17-27. Ethernet Address Recognition—Receive Block DecisionsAccept/RejectBroadcast Ad

Page 277 - 15 14 13 12 11 10 9 8 0

Fast Ethernet Controller (FEC)17-38 Freescale SemiconductorFigure 17-28. Ethernet Address Recognition—Microcode Decisions17.5.10 Hash AlgorithmThe has

Page 278 - ACTV command 1 2 3 3

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-39The user must initialize the hash table registers. Use this CRC32 polynomial to compute the

Page 279

OverviewFreescale Semiconductor 1-3• Queued serial peripheral interface (QSPI)— Full-duplex, three-wire synchronous transfers— Up to four chip selects

Page 280 - 31 1817 9876543210

Fast Ethernet Controller (FEC)17-40 Freescale Semiconductor59FF_FFFF_FFFF 0x1C 2879FF_FFFF_FFFF 0x1D 2929FF_FFFF_FFFF 0x1E 3019FF_FFFF_FFFF 0x1F 31D1F

Page 281 - 15.2.3.1 Address Multiplexing

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-4117.5.11 Full Duplex Flow ControlFull-duplex flow control allows you to transmit pause frame

Page 282

Fast Ethernet Controller (FEC)17-42 Freescale SemiconductorWhen the transmitter pauses due to receiver/microcontroller pause frame detection, TCR[TFC_

Page 283

Fast Ethernet Controller (FEC)Freescale Semiconductor 17-4317.5.15.1 Transmission Errors17.5.15.1.1 Transmitter UnderrunIf this error occurs, the FEC

Page 284

Fast Ethernet Controller (FEC)17-44 Freescale Semiconductor17.5.15.2.3 CRC ErrorWhen a CRC error occurs with no dribble bits, FEC closes the buffer an

Page 285 - 15.2.3.4 Burst Page Mode

Freescale Semiconductor 18-1Chapter 18 Watchdog Timer Module18.1 IntroductionThe watchdog timer is a 16-bit timer used to help software recover from

Page 286

Watchdog Timer Module18-2 Freescale Semiconductor18.3 Block Diagram Figure 18-1. Watchdog Timer Block Diagram18.4 SignalsThe watchdog timer module has

Page 287

Watchdog Timer ModuleFreescale Semiconductor 18-318.5.2 RegistersThe watchdog timer programming model consists of these registers: • Watchdog control

Page 288 - REF ACTV

Watchdog Timer Module18-4 Freescale Semiconductor18.5.2.2 Watchdog Modulus Register (WMR)Table 18-3. WCR Field DescriptionsBit(s) Name Description15–4

Page 289 - Possible

Watchdog Timer ModuleFreescale Semiconductor 18-518.5.2.3 Watchdog Count Register (WCNTR)18.5.2.4 Watchdog Service Register (WSR)When the watchdog tim

Page 290 - 15.3 SDRAM Example

Overview1-4 Freescale Semiconductor— Toggle-on-overflow feature for pulse-width modulator (PWM) generation— One dual-mode pulse accumulation channel p

Page 291

Watchdog Timer Module18-6 Freescale Semiconductor 15 14 13 12 11 10 9 8Field WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8Reset 0000_0000R/W R/W765 4 3210Fiel

Page 292 - ACTV timing

Freescale Semiconductor 19-1Chapter 19 Programmable Interrupt Timers (PIT0–PIT3)19.1 IntroductionThis chapter describes the operation of the four pro

Page 293 - 151413121110 876543210

Programmable Interrupt Timers (PIT0–PIT3)19-2 Freescale SemiconductorNOTEThe low-power interrupt control register (LPICR) in the system control module

Page 294

Programmable Interrupt Timers (PIT0–PIT3)Freescale Semiconductor 19-319.2.1 PIT Control and Status Register (PCSRn)The PCSRn registers configure the c

Page 295 - 1514131211109876543210

Programmable Interrupt Timers (PIT0–PIT3)19-4 Freescale SemiconductorTable 19-3. PCSRn Field DescriptionsField Description15–12 Reserved, must be clea

Page 296 - Refresh Sequence:

Programmable Interrupt Timers (PIT0–PIT3)Freescale Semiconductor 19-519.2.2 PIT Modulus Register (PMRn)The 16-bit read/write PMRn contains the timer m

Page 297

Programmable Interrupt Timers (PIT0–PIT3)19-6 Freescale Semiconductor19.3 Functional DescriptionThis section describes the PIT functional operation.19

Page 298 - 15 12 11 8 7 4 3 0

Programmable Interrupt Timers (PIT0–PIT3)Freescale Semiconductor 19-7When the PCSRn[OVW] bit is set, counter can be directly initialized by writing to

Page 299

Programmable Interrupt Timers (PIT0–PIT3)19-8 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 300 - 16.3 DMA Transfer Overview

Freescale Semiconductor 20-1Chapter 20 General Purpose Timer Modules (GPTA and GPTB)The processor has two 4-channel general purpose timer modules (GP

Page 301

OverviewFreescale Semiconductor 1-5— Ability to boot from internal Flash memory or external memories that are 8, 16, or 32 bits wide•Reset— Separate r

Page 302

General Purpose Timer Modules (GPTA and GPTB)20-2 Freescale Semiconductor20.2 Block Diagram Figure 20-1. GPT Block DiagramPrescalerChannel 0PT016-Bit

Page 303 - 31 24 23 0

General Purpose Timer Modules (GPTA and GPTB)Freescale Semiconductor 20-320.3 Low-Power Mode OperationThis subsection describes the operation of the g

Page 304

General Purpose Timer Modules (GPTA and GPTB)20-4 Freescale Semiconductor20.4.3 SYNCnThe SYNCn pin is for synchronization of the timer counter. It can

Page 305

General Purpose Timer Modules (GPTA and GPTB)Freescale Semiconductor 20-520.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS)0x1A_0017 0x1

Page 306 - 76543210

General Purpose Timer Modules (GPTA and GPTB)20-6 Freescale Semiconductor20.5.2 GPT Compare Force Register (GPCFORC)NOTEA successful channel 3 output

Page 307

General Purpose Timer Modules (GPTA and GPTB)Freescale Semiconductor 20-720.5.4 GPT Output Compare 3 Data Register (GPTOC3D)NOTEA successful channel 3

Page 308 - 16.5.2 Data Transfer Modes

General Purpose Timer Modules (GPTA and GPTB)20-8 Freescale Semiconductor20.5.6 GPT System Control Register 1 (GPTSCR1)Table 20-8. GPTCNT Field Descri

Page 309 - 16.5.4 Data Transfer

General Purpose Timer Modules (GPTA and GPTB)Freescale Semiconductor 20-9Figure 20-8. Fast Clear Flag Logic20.5.7 GPT Toggle-On-Overflow Register (GPT

Page 310 - 16.5.5 Termination

General Purpose Timer Modules (GPTA and GPTB)20-10 Freescale Semiconductor20.5.9 GPT Control Register 2 (GPTCTL2)20.5.10 GPT Interrupt Enable Register

Page 311

General Purpose Timer Modules (GPTA and GPTB)Freescale Semiconductor 20-1120.5.11 GPT System Control Register 2 (GPTSCR2)Table 20-13. GPTIE Field Desc

Page 312 - Master Bus

Overview1-6 Freescale SemiconductorFigure 1-1. MCF528x and MCF521x Block DiagramInterfaceChipUART1SerialI/OJTAGPortSelectsColdFire V2 CoreEMACExternal

Page 313 - 17.1.3 Features

General Purpose Timer Modules (GPTA and GPTB)20-12 Freescale Semiconductor20.5.12 GPT Flag Register 1 (GPTFLG1)20.5.13 GPT Flag Register 2 (GPTFLG2)2–

Page 314 - 17.2 Modes of Operation

General Purpose Timer Modules (GPTA and GPTB)Freescale Semiconductor 20-13Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access

Page 315

General Purpose Timer Modules (GPTA and GPTB)20-14 Freescale Semiconductor20.5.15 Pulse Accumulator Control Register (GPTPACTL)7 6543 0Field — PAE PAM

Page 316 - Register

General Purpose Timer Modules (GPTA and GPTB)Freescale Semiconductor 20-1520.5.16 Pulse Accumulator Flag Register (GPTPAFLG)NOTEWhen the fast flag cle

Page 317

General Purpose Timer Modules (GPTA and GPTB)20-16 Freescale Semiconductor20.5.17 Pulse Accumulator Counter Register (GPTPACNT)20.5.18 GPT Port Data R

Page 318

General Purpose Timer Modules (GPTA and GPTB)Freescale Semiconductor 20-1720.5.19 GPT Port Data Direction Register (GPTDDR)20.6 Functional Description

Page 319

General Purpose Timer Modules (GPTA and GPTB)20-18 Freescale Semiconductor20.6.3 Output CompareSetting an I/O select bit, IOSn, configures channel n a

Page 320

General Purpose Timer Modules (GPTA and GPTB)Freescale Semiconductor 20-19The PA overflow flag, PAOVF, is set when the PA rolls over from 0xFFFF to 0x

Page 321

General Purpose Timer Modules (GPTA and GPTB)20-20 Freescale SemiconductorThe PORTTn data direction register controls the data direction of an input c

Page 322

General Purpose Timer Modules (GPTA and GPTB)Freescale Semiconductor 20-2120.7 ResetReset initializes the GPT registers to a known startup state as de

Page 323

OverviewFreescale Semiconductor 1-71.1.1 Version 2 ColdFire CoreThe processor core is comprised of two separate pipelines that are decoupled by an ins

Page 324

General Purpose Timer Modules (GPTA and GPTB)20-22 Freescale SemiconductorNOTEWhen the fast flag clear all bit, GPTSCR1[TFFCA], is set, an input captu

Page 325

General Purpose Timer Modules (GPTA and GPTB)Freescale Semiconductor 20-23NOTEWhen the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOFdoes

Page 326

General Purpose Timer Modules (GPTA and GPTB)20-24 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 327

Freescale Semiconductor 21-1Chapter 21 DMA Timers (DTIM0–DTIM3)21.1 IntroductionThis chapter describes the configuration and operation of the four di

Page 328

DMA Timers (DTIM0–DTIM3)21-2 Freescale SemiconductorFigure 21-1 is a block diagram of one of the four identical timer modules.Figure 21-1. DMA Timer B

Page 329

DMA Timers (DTIM0–DTIM3)Freescale Semiconductor 21-321.2 Memory Map/Register DefinitionThe timer module registers, shown in Table 21-1, can be modifie

Page 330

DMA Timers (DTIM0–DTIM3)21-4 Freescale SemiconductorTable 21-2. DTMRn Field DescriptionsField Description15–8PSPrescaler value. Divides the clock inpu

Page 331

DMA Timers (DTIM0–DTIM3)Freescale Semiconductor 21-521.2.2 DMA Timer Extended Mode Registers (DTXMRn)The DTXMRn registers program DMA request and incr

Page 332 - 0x114C Access: User read-only

DMA Timers (DTIM0–DTIM3)21-6 Freescale SemiconductorIPSBAROffset:0x00_0403 (DTER0)0x00_0443 (DTER1)0x00_0483 (DTER2)0x00_04C3 (DTER3)Access: User read

Page 333

DMA Timers (DTIM0–DTIM3)Freescale Semiconductor 21-721.2.4 DMA Timer Reference Registers (DTRRn)As part of the output-compare function, each DTRRn con

Page 334

OverviewColdFire CoreEnhanced Multiply-Accumulate Unit (EMAC)CacheStatic RAM (SRAM)ColdFire Flash Module (CFM)Power ManagementSystem Control Module (S

Page 335 - 17.5 Functional Description

Overview1-8 Freescale SemiconductorThe SRAM module is also accessible by non-core bus masters, for example the DMA and/or the FEC. Thedual-ported natu

Page 336 - 17-26 Freescale Semiconductor

DMA Timers (DTIM0–DTIM3)21-8 Freescale Semiconductor21.2.6 DMA Timer Counters (DTCNn)The current value of the 32-bit timer counter can be read at anyt

Page 337 - Data Length

DMA Timers (DTIM0–DTIM3)Freescale Semiconductor 21-9If the free run/restart bit (DTMRn[FRR]) is set, a new count starts. If it is clear, the timer kee

Page 338

DMA Timers (DTIM0–DTIM3)21-10 Freescale Semiconductor*[CE] = 00 disable capture event output*[OM] = 0 output=active-low pulse*[ORRI] = 0, disable ref

Page 339

DMA Timers (DTIM0–DTIM3)Freescale Semiconductor 21-11For example, if a 80-MHz timer clock is divided by 16, DTMRn[PS] equals 0x7F, and the timer is re

Page 340

DMA Timers (DTIM0–DTIM3)21-12 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 341

Freescale Semiconductor 22-1Chapter 22 Queued Serial Peripheral Interface (QSPI)22.1 IntroductionThis chapter describes the queued serial peripheral

Page 342 - Table 17-35. MII Mode

Queued Serial Peripheral Interface (QSPI)22-2 Freescale Semiconductor22.1.2 OverviewThe queued serial peripheral interface module provides a serial pe

Page 343 - 17.5.7 FEC Frame Transmission

Queued Serial Peripheral Interface (QSPI)Freescale Semiconductor 22-322.3 Memory Map/Register DefinitionTable 22-2 is the QSPI register memory map. Re

Page 344 - 17-34 Freescale Semiconductor

Queued Serial Peripheral Interface (QSPI)22-4 Freescale SemiconductorTable 22-3. QMR Field DescriptionsField Description15MSTRMaster mode enable. 0 Re

Page 345 - 17.5.8 FEC Frame Reception

Queued Serial Peripheral Interface (QSPI)Freescale Semiconductor 22-5Figure 22-3 shows an example of a QSPI clocking and data transfer.Figure 22-3. QS

Page 346 - 17-36 Freescale Semiconductor

OverviewFreescale Semiconductor 1-9base address register (RAMBAR), and system control registers that include low-power and core watchdogtimer control.

Page 347 - Freescale Semiconductor 17-37

Queued Serial Peripheral Interface (QSPI)22-6 Freescale Semiconductor22.3.3 QSPI Wrap Register (QWR)The QSPI wrap register provides halt transfer cont

Page 348 - 17.5.10 Hash Algorithm

Queued Serial Peripheral Interface (QSPI)Freescale Semiconductor 22-722.3.5 QSPI Address Register (QAR)The QAR is used to specify the location in the

Page 349 - Eqn. 17-2

Queued Serial Peripheral Interface (QSPI)22-8 Freescale Semiconductor22.3.6 QSPI Data Register (QDR)The QDR is used to access QSPI RAM indirectly. The

Page 350

Queued Serial Peripheral Interface (QSPI)Freescale Semiconductor 22-9NOTEThe command RAM is accessed only using the most significant byte of QDR and i

Page 351

Queued Serial Peripheral Interface (QSPI)22-10 Freescale Semiconductor• 32 receive data bytes (receive data RAM)The RAM is organized so that 1 byte of

Page 352 - 17.5.13 Collision Managing

Queued Serial Peripheral Interface (QSPI)Freescale Semiconductor 22-1122.4.1 QSPI RAMThe QSPI contains an 80-byte block of static RAM that can be acce

Page 353 - 17.5.15.2 Reception Errors

Queued Serial Peripheral Interface (QSPI)22-12 Freescale Semiconductorthe least significant bits of the RAM. Unused bits in a receive queue entry are

Page 354 - 17-44 Freescale Semiconductor

Queued Serial Peripheral Interface (QSPI)Freescale Semiconductor 22-13The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD

Page 355

Queued Serial Peripheral Interface (QSPI)22-14 Freescale Semiconductorwhere QDLYR[DTL] has a range of 1–255. A zero value for DTL causes a delay-after

Page 356 - 18.5.1 Memory Map

Queued Serial Peripheral Interface (QSPI)Freescale Semiconductor 22-15QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven QSP

Page 357 - Bits 15–8 Bits 7–0 Access

Overview1-10 Freescale Semiconductor1.1.8 SDRAM ControllerThe SDRAM controller provides all required signals for glueless interfacing to a variety ofJ

Page 358 - 765 4 3210

Queued Serial Peripheral Interface (QSPI)22-16 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 359

Freescale Semiconductor 23-1Chapter 23 UART Modules23.1 IntroductionThis chapter describes the use of the three universal asynchronous receiver/trans

Page 360

UART Modules23-2 Freescale SemiconductorNOTEThe DTINn pin can clock UARTn. However, if the timers are operating and the UART uses DTINn as a clock sou

Page 361

UART ModulesFreescale Semiconductor 23-3• Start/end break interrupt/status23.2 External Signal DescriptionTable 23-1 briefly describes the UART module

Page 362 - Register

UART Modules23-4 Freescale SemiconductorTable 23-2. UART Module Memory MapRegisterWidth(bit)Access Reset Value Section/PageUART0UART1UART20x000x00x0UA

Page 363 - 0x15_0000 (PCSR0)

UART ModulesFreescale Semiconductor 23-523.3.1 UART Mode Registers 1 (UMR1n)The UMR1n registers control UART module configuration. UMR1n can be read o

Page 364

UART Modules23-6 Freescale Semiconductor23.3.2 UART Mode Register 2 (UMR2n)The UMR2n registers control UART module configuration. UMR2n can be read or

Page 365 - 0x15_0002 (PMR0)

UART ModulesFreescale Semiconductor 23-7Table 23-4. UMR2n Field DescriptionsField Description7–6CMChannel mode. Selects a channel mode. Section 23.4.3

Page 366 - 0x15_0004 (PCNTR0)

UART Modules23-8 Freescale Semiconductor23.3.3 UART Status Registers (USRn)The USRn registers show the status of the transmitter, the receiver, and th

Page 367 - PCSRn[PRE]

UART ModulesFreescale Semiconductor 23-923.3.4 UART Clock Select Registers (UCSRn)The UCSRs select an external clock on the DTIN input (divided by 1 o

Page 368 - 19-8 Freescale Semiconductor

OverviewFreescale Semiconductor 1-11• Detection of breaks originating in the middle of a character• Start/end break interrupt/status1.1.11 DMA Timers

Page 369

UART Modules23-10 Freescale SemiconductorTable 23-7 describes UCRn fields and commands. Examples in Section 23.4.2, “Transmitter and Receiver Operatin

Page 370 - 20.2 Block Diagram

UART ModulesFreescale Semiconductor 23-1123.3.6 UART Receive Buffers (URBn)The receive buffers contain one serial shift register and three receiver ho

Page 371 - 20.4 Signal Description

UART Modules23-12 Freescale Semiconductor23.3.7 UART Transmit Buffers (UTBn)The transmit buffers consist of the transmitter holding register and the t

Page 372 - Bits 7–0 Access

UART ModulesFreescale Semiconductor 23-1323.3.9 UART Auxiliary Control Register (UACRn)The UACRs control the input enable.23.3.10 UART Interrupt Statu

Page 373

UART Modules23-14 Freescale SemiconductorNOTETrue status is provided in the UISRn regardless of UIMRn settings. UISRn is cleared when the UART module

Page 374

UART ModulesFreescale Semiconductor 23-1523.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)The UBG1n registers hold the MSB, and the UBG2n regis

Page 375

UART Modules23-16 Freescale Semiconductor23.3.13 UART Output Port Command Registers (UOP1n/UOP0n)The URTSn output can be asserted by writing a 1 to UO

Page 376 - 7 6543 0

UART ModulesFreescale Semiconductor 23-1723.4.1.1 Programmable DividerAs Figure 23-17 shows, the UARTn transmitter and receiver can use the following

Page 377 - 7 654321 0

UART Modules23-18 Freescale SemiconductorUsing a 80-MHz internal bus clock and letting baud rate equal 9600, thenEqn. 23-2Therefore, UBG1n equals 0x01

Page 378

UART ModulesFreescale Semiconductor 23-19optional parity bit, and the programmed number of stop bits. The lsb is sent first. Data is shifted from the

Page 379 - 7 65432 0

Overview1-12 Freescale Semiconductorbyte, word, longword or 16-byte burst line transfers. These transfers are triggered by software, explicitlysetting

Page 380

UART Modules23-20 Freescale SemiconductorFigure 23-19. Transmitter Timing Diagram23.4.2.2 ReceiverThe receiver is enabled through its UCRn, as describ

Page 381

UART ModulesFreescale Semiconductor 23-21framing error, overrun error, and received break conditions set the respective PE, FE, OE, and RB error and b

Page 382

UART Modules23-22 Freescale Semiconductorprogramming the ERR bit in the UART’s mode register (UMR1n), status is provided in character or block modes.U

Page 383

UART ModulesFreescale Semiconductor 23-2323.4.3.1 Automatic Echo ModeIn automatic echo mode, shown in Figure 23-21, the UART automatically resends rec

Page 384

UART Modules23-24 Freescale SemiconductorFigure 23-23. Remote Loopback23.4.4 Multidrop ModeSetting UMR1n[PM] programs the UART to operate in a wake-up

Page 385 - 20.6 Functional Description

UART ModulesFreescale Semiconductor 23-25Figure 23-24. Multidrop Mode Timing DiagramA character sent from the master station consists of a start bit,

Page 386 - 20.6.5 Event Counter Mode

UART Modules23-26 Freescale Semiconductor23.4.5 Bus OperationThis section describes bus operation during read, write, and interrupt acknowledge cycles

Page 387

UART ModulesFreescale Semiconductor 23-273. Unmask appropriate bits in the core’s status register (SR) to enable interrupts.4. If TXRDY or RXRDY gener

Page 388

UART Modules23-28 Freescale SemiconductorTo configure the UART for DMA requests:1. Initialize the DMAREQC in the SCM to map the desired UART DMA reque

Page 389 - 20.8 Interrupts

UART ModulesFreescale Semiconductor 23-2923.5.2 UART Module Initialization SequenceThe following shows the UART module initialization sequence.1. UCRn

Page 390 - 20.8.4 Timer Overflow (TOF)

OverviewFreescale Semiconductor 1-131.2.4 Queued Serial Peripheral Interface (QSPI)The queued serial peripheral interface module provides a synchronou

Page 391 - Freescale Semiconductor 20-23

UART Modules23-30 Freescale SemiconductorFigure 23-25. UART Mode Programming Flowchart (Sheet 1 of 5)Serial ModuleSINITInitiate:Channel InterruptsCHK1

Page 392 - 20-24 Freescale Semiconductor

UART ModulesFreescale Semiconductor 23-31Figure 23-25. UART Mode Programming Flowchart (Sheet 2 of 5)CHCHKCHCHKPlace Channel InLocal LoopbackModeEnabl

Page 393

UART Modules23-32 Freescale SemiconductorFigure 23-25. UART Mode Programming Flowchart (Sheet 3 of 5)ABBFRCHKHaveFraming Error?Set FramingError FlagPR

Page 394 - 21.1.2 Features

UART ModulesFreescale Semiconductor 23-33Figure 23-25. UART Mode Programming Flowchart (Sheet 4 of 5)WasIRQ CausedBy BeginningOf A Break?SIRQABRKINCle

Page 395 - 0x00_0400 (DTMR0)

UART Modules23-34 Freescale SemiconductorFigure 23-25. UART Mode Programming Flowchart (Sheet 5 of 5)OUTCHIsTransmitterReady?NYSend CharacterTo Transm

Page 396

Freescale Semiconductor 24-1Chapter 24 I2C Interface24.1 IntroductionThis chapter describes the I2C module, clock synchronization, and I2C programmin

Page 397 - 0x00_0402 (DTXMR0)

I2C Interface24-2 Freescale Semiconductor24.1.2 OverviewI2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data e

Page 398 - 0x00_0403 (DTER0)

I2C InterfaceFreescale Semiconductor 24-324.2 Memory Map/Register DefinitionThe below table lists the configuration registers used in the I2C interfac

Page 399 - 0x00_0408 (DTCR0)

I2C Interface24-4 Freescale Semiconductor24.2.3 I2C Control Register (I2CR)I2CR enables the I2C module and the I2C interrupt. It also contains bits th

Page 400 - 0x00_040C (DTCN0)

I2C InterfaceFreescale Semiconductor 24-524.2.4 I2C Status Register (I2SR)I2SR contains bits that indicate transaction direction and status.IPSBAROffs

Page 401 - 21.4.1 Code Example

Overview1-14 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 402 - Eqn. 21-1

I2C Interface24-6 Freescale Semiconductor24.2.5 I2C Data I/O Register (I2DR)In master-receive mode, reading I2DR allows a read to occur and for the ne

Page 403 - Freescale Semiconductor 21-11

I2C InterfaceFreescale Semiconductor 24-724.3 Functional DescriptionThe I2C module uses a serial data line (I2C_SDA) and a serial clock line (I2C_SCL)

Page 404 - 21-12 Freescale Semiconductor

I2C Interface24-8 Freescale SemiconductorFigure 24-7. I2C Standard Communication Protocol24.3.2 Slave Address TransmissionThe master sends the slave a

Page 405

I2C InterfaceFreescale Semiconductor 24-924.3.4 AcknowledgeThe transmitter releases the I2C_SDA line high during the acknowledge clock pulse as shown

Page 406 - 22.1.4 Modes of Operation

I2C Interface24-10 Freescale SemiconductorFigure 24-10. Repeated STARTVarious combinations of read/write formats are then possible:• The first example

Page 407 - Table 22-2. QSPI Memory Map

I2C InterfaceFreescale Semiconductor 24-1124.3.7 Clock Synchronization and ArbitrationI2C is a true multi-master bus that allows more than one master

Page 408

I2C Interface24-12 Freescale Semiconductor24.3.8 Handshaking and Clock StretchingThe clock synchronization mechanism can acts as a handshake in data t

Page 409

I2C InterfaceFreescale Semiconductor 24-13processor may need to wait until the I2C is busy after writing the calling address to the I2DR before procee

Page 410 - 15 141312 11 109876543 210

I2C Interface24-14 Freescale SemiconductorFor a master receiver to terminate a data transfer, it must inform the slave transmitter by not acknowledgin

Page 411

I2C InterfaceFreescale Semiconductor 24-15Figure 24-14. Flow-Chart of Typical I2C Interrupt RoutineClearMaster Mode? TX/Rx ?Last Byte Transmitted?RXAK

Page 412

Freescale Semiconductor 2-1Chapter 2 ColdFire Core2.1 IntroductionThis section describes the organization of the Version 2 (V2) ColdFire® processor c

Page 413 - 22.4 Functional Description

I2C Interface24-16 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 414 - 22-10 Freescale Semiconductor

Freescale Semiconductor 25-1Chapter 25 FlexCANThe FlexCAN module is a communication controller implementing the controller area network (CAN)protocol

Page 415 - 22.4.1 QSPI RAM

FlexCAN25-2 Freescale SemiconductorA block diagram describing the various submodules of the FlexCAN module is shown in Figure 25-1.Each submodule is d

Page 416 - 22.4.2 Baud Rate Selection

FlexCANFreescale Semiconductor 25-325.1.2 External SignalsThe FlexCAN module/CAN transceiver is composed of two signals: CANTX, which is the serialtra

Page 417 - 22.4.3 Transfer Delays

FlexCAN25-4 Freescale Semiconductor25.2 The CAN SystemA typical CAN system is shown below in Figure 25-2.Figure 25-2. Typical CAN systemEach CAN stati

Page 418 - 22.4.5 Data Transfer

FlexCANFreescale Semiconductor 25-5Figure 25-3. Extended ID Message Buffer StructureFigure 25-4. Standard ID Message Buffer Structure25.3.1.1 Common F

Page 419 - Freescale Semiconductor 22-15

FlexCAN25-6 Freescale SemiconductorTable 25-2. Common Extended/Standard Format FramesField DescriptionTime Stamp Contains a copy of the high byte of t

Page 420 - 22-16 Freescale Semiconductor

FlexCANFreescale Semiconductor 25-725.3.1.2 Fields for Extended Format FramesTable 25-5 describes the message buffer fields used only for extended ide

Page 421

FlexCAN25-8 Freescale SemiconductorFigure 25-5. FlexCAN Memory Map25.4 Functional OverviewThe FlexCAN module is flexible in that each one of its 16 me

Page 422 - 23.1.2 Features

FlexCANFreescale Semiconductor 25-9• Writing the Data bytes• Writing the Control/Status word (active Code, Length)NOTEThe first and last steps are man

Page 423

ColdFire Core2-2 Freescale Semiconductorinstruction, fetches the required operands and then executes the required function. Because the IFP and OEP pi

Page 424

FlexCAN25-10 Freescale SemiconductorNote that the received identifier field is always stored in the matching MB, thus the contents of theidentifier fi

Page 425 - 0x00_0200 (UMR10)

FlexCANFreescale Semiconductor 25-11Data should never be written into a receive message buffer. If this is done while a message is beingtransferred fr

Page 426 - 0x00_0200 (UMR20)

FlexCAN25-12 Freescale SemiconductorA received remote frame is not stored in a receive message buffer. It is only used to trigger the automatictransmi

Page 427

FlexCANFreescale Semiconductor 25-1325.4.8.1 Configuring the FlexCAN Bit TimingThe following considerations must be observed when programming bit timi

Page 428 - 0x00_0204 (USR0)

FlexCAN25-14 Freescale SemiconductorThe FlexCAN responds to any bus state as described in the protocol, e.g. transmit error active or errorpassive fla

Page 429 - 0x00_0204 (UCSR0)

FlexCANFreescale Semiconductor 25-155. Negate the HALT bit in the module configuration registera) At this point, the FlexCAN will attempt to synchroni

Page 430 - 0x00_0208 (UCR0)

FlexCAN25-16 Freescale SemiconductorTo exit low-power stop mode:• Reset the FlexCAN either by asserting RSTI or by setting the SOFTRST bit CANMCR.• Cl

Page 431

FlexCANFreescale Semiconductor 25-1725.4.11.3 Auto-Power Save ModeAuto-power save mode enables normal operation with optimized power savings. Once the

Page 432 - 0x00_0210 (UIPCR0)

FlexCAN25-18 Freescale Semiconductor25.5.1 CAN Module Configuration Register (CANMCR)Table 25-8 describes the CANMCR fields.15 14 13 12 11 10 9 8Field

Page 433 - 0x00_0210 (UACR0)

FlexCANFreescale Semiconductor 25-199SOFTRSTSoft reset. When this bit is asserted, the FlexCAN resets its internal state machines (sequencer, error co

Page 434 - 0x00_0214 (UISR0)

ColdFire CoreFreescale Semiconductor 2-3Accumulators and extension bytes can be loaded, copied, and stored, and results from EMAC arithmetic operation

Page 435 - 0x00_0234 (UIP0)

FlexCAN25-20 Freescale Semiconductor25.5.2 FlexCAN Control Register 0 (CANCTRL0)Table 25-9 describes the CANCTRL0 fields.76543210Field BOFFMSK ERRMSK

Page 436 - 0x00_0238 (UOP10)

FlexCANFreescale Semiconductor 25-2125.5.3 FlexCAN Control Register 1 (CANCTRL1)Table 25-11 describes the CANCTRL1 fields.76543210Field SAMP — TSYNC L

Page 437 - 23.4.1.1 Programmable Divider

FlexCAN25-22 Freescale Semiconductor25.5.4 Prescaler Divide Register (PRESDIV)Table 25-12 describes the PRESDIV fields.25.5.5 FlexCAN Control Register

Page 438 - 23.4.2.1 Transmitter

FlexCANFreescale Semiconductor 25-2325.5.6 Free Running Timer (TIMER)Table 25-14 describes the TIMER fields.25.5.7 Rx Mask RegistersThese registers ar

Page 439 - Freescale Semiconductor 23-19

FlexCAN25-24 Freescale Semiconductor25.5.7.1 Receive Mask Registers (RXGMASK, RX14MASK, RX15MASK)The Rx global mask register (RXGMASK) is composed of

Page 440 - 23.4.2.2 Receiver

FlexCANFreescale Semiconductor 25-2525.5.8 FlexCAN Error and Status Register (ESTAT)ESTAT reflects various error conditions, some general status of th

Page 441 - 23.4.2.3 FIFO

FlexCAN25-26 Freescale SemiconductorTable 25-17 describes the ESTAT fields.15 14 13 12 11 10 9 8Field BITERR ACKERR CRCERR FORMERR STUFFERR TXWARN RXW

Page 442 - 23.4.3 Looping Modes

FlexCANFreescale Semiconductor 25-2725.5.9 Interrupt Mask Register (IMASK)IMASK contains one interrupt mask bit per buffer. It enables the CPU to dete

Page 443 - 23.4.3.3 Remote Loopback Mode

FlexCAN25-28 Freescale SemiconductorThe interrupt mask register contains two 8-bit fields: bits 15-8 (IMASK_H) and bits 7-0 (IMASK_L). Theregister can

Page 444 - 23.4.4 Multidrop Mode

FlexCANFreescale Semiconductor 25-29Table 25-19 describes the IFLAG fields.25.5.11 FlexCAN Receive Error Counter (RXECTR)Table 25-20 describes the RXE

Page 445 - UMR1n[PM] = 11

Freescale Semiconductor vChapter 1Overview1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 446 - 23.4.5 Bus Operation

ColdFire Core2-4 Freescale Semiconductor2.2.1 Data Registers (D0–D7)D0–D7 data registers are for bit (1-bit), byte (8-bit), word (16-bit) and longword

Page 447 - Table 23-13. UART Interrupts

FlexCAN25-30 Freescale Semiconductor25.5.12 FlexCAN Transmit Error Counter (TXECTR)Table 25-21 describes the TXECTR fields.7 0Field TXECTRReset 0000_0

Page 448 - UISRn 0 Transmit DMA request

Freescale Semiconductor 26-1Chapter 26 General Purpose I/O Module26.1 IntroductionMany of the pins associated with the external interface may be used

Page 449 - Freescale Semiconductor 23-29

General Purpose I/O Module26-2 Freescale Semiconductor1. Although ports NQ, QA, QB, TA, and TB are not part of the ports module, they are included her

Page 450 - 23-30 Freescale Semiconductor

General Purpose I/O ModuleFreescale Semiconductor 26-31. Although ports NQ, QA, QB, TA, and TB are not part of the ports module, they are included her

Page 451 - Freescale Semiconductor 23-31

General Purpose I/O Module26-4 Freescale Semiconductor26.1.1 OverviewThe ports module controls the configuration for various external pins, including

Page 452 - 23-32 Freescale Semiconductor

General Purpose I/O ModuleFreescale Semiconductor 26-5Table 26-1. Ports External SignalsPrimary Function(Pin Name)1GPIO(DefaultFunction)Alternate Func

Page 453 - Freescale Semiconductor 23-33

General Purpose I/O Module26-6 Freescale SemiconductorSCASPSD[4] — SDRAM synchronous column address strobe / Port SD[4]DRAMW PSD[3] — — SDRAM write en

Page 454 - 23-34 Freescale Semiconductor

General Purpose I/O ModuleFreescale Semiconductor 26-7Refer to Chapter 14, “Signal Descriptions” for more detailed descriptions of these pins. The fun

Page 455

General Purpose I/O Module26-8 Freescale Semiconductor0x10_0008 PORTJ PORTDD PORTEH(Reserved on MCF521x)PORTEL S/U0x10_000C PORTAS PORTQS PORTSD PORTT

Page 456 - 24.1.3 Features

General Purpose I/O ModuleFreescale Semiconductor 26-9Port Data Direction Registers0x10_0014 DDRA DDRB DDRC DDRD S/U0x10_0018 DDRE DDRF DDRG DDRH S/U0

Page 457 - 24.2.2 I

ColdFire CoreFreescale Semiconductor 2-52.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7)This ColdFire architecture supports two independent stac

Page 458

General Purpose I/O Module26-10 Freescale Semiconductor26.3.2 Register Descriptions26.3.2.1 Port Output Data Registers (PORTn)The PORTn registers stor

Page 459 - C Status Register (I2SR)

General Purpose I/O ModuleFreescale Semiconductor 26-11PORTn bits are described in Table 26-3.26.3.2.2 Port Data Direction Registers (DDRn)The DDRs co

Page 460 - C Data I/O Register (I2DR)

General Purpose I/O Module26-12 Freescale Semiconductor76 0Field — DDRn6DDRn5DDRn4DDRn3DDRn2DDRn1DDRn0Reset 0000_0000R/W: R R/WAddress IPSBAR + 0x10_0

Page 461 - 24.3 Functional Description

General Purpose I/O ModuleFreescale Semiconductor 26-1326.3.2.3 Port Pin Data/Set Data Registers (PORTnP/SETn)The PORTnP/SETn registers reflect the cu

Page 462 - 24.3.3 Data Transfer

General Purpose I/O Module26-14 Freescale SemiconductorPORTnP/SETn bits are described in Table 26-5.26.3.2.4 Port Clear Output Data Registers (CLRn)Cl

Page 463 - 24.3.6 Repeated START

General Purpose I/O ModuleFreescale Semiconductor 26-15CLRn register bits are described in Table 26-6.76543210Field — CLRn6CLRn5CLRn4CLRn3CLRn2CLRn1CL

Page 464 - Figure 24-10. Repeated START

General Purpose I/O Module26-16 Freescale Semiconductor26.3.2.5 Port B/C/D Pin Assignment Register (PBCDPAR)The PBCDPAR controls the pin function of p

Page 465 - Freescale Semiconductor 24-11

General Purpose I/O ModuleFreescale Semiconductor 26-1726.3.2.6 Port E Pin Assignment Register (PEPAR)The PEPAR controls the pin function of port E.Th

Page 466 - 24.4.2 Generation of START

General Purpose I/O Module26-18 Freescale SemiconductorThe reset values for all bits and fields in PEPAR are shown in Table 26-10.6 PEPA3 Port E pin a

Page 467 - 24.4.4 Generation of STOP

General Purpose I/O ModuleFreescale Semiconductor 26-1926.3.2.7 Port F Pin Assignment Register (PFPAR)The PFPAR controls the pin function of port F[7:

Page 468 - 24.4.7 Arbitration Lost

ColdFire Core2-6 Freescale Semiconductor2.2.4 Condition Code Register (CCR)The CCR is the LSB of the processor status register (SR). Bits 4–0 act as i

Page 469 - C Interrupt Routine

General Purpose I/O Module26-20 Freescale Semiconductor26.3.2.8 Port J Pin Assignment Register (PJPAR)The PJPAR controls the pin function of port J.76

Page 470 - 24-16 Freescale Semiconductor

General Purpose I/O ModuleFreescale Semiconductor 26-2126.3.2.9 Port SD Pin Assignment Register (PSDPAR)The PSDPAR controls the pin function of port S

Page 471

General Purpose I/O Module26-22 Freescale Semiconductor26.3.2.11 Port EH/EL Pin Assignment Register (PEHLPAR)The PEHLPAR controls the pin function of

Page 472

General Purpose I/O ModuleFreescale Semiconductor 26-2326.3.2.12 Port QS Pin Assignment Register (PQSPAR)The PQSPAR controls the pin function of port

Page 473

General Purpose I/O Module26-24 Freescale Semiconductor26.3.2.13 Port TC Pin Assignment Register (PTCPAR)The PTCPAR controls the pin function of port

Page 474 - 25.3 Message Buffers

General Purpose I/O ModuleFreescale Semiconductor 26-2526.3.2.14 Port TD Pin Assignment Register (PTDPAR)The PTDPAR controls the pin function of port

Page 475

General Purpose I/O Module26-26 Freescale Semiconductor26.3.2.15 Port UA Pin Assignment Register (PUAPAR)The PUAPAR controls the pin function of port

Page 476

General Purpose I/O ModuleFreescale Semiconductor 26-2726.4 Functional Description26.4.1 OverviewThe initial pin function is determined during reset c

Page 477

General Purpose I/O Module26-28 Freescale SemiconductorFigure 26-30. Digital Input TimingData written to the PORTn register of any pin configured as a

Page 478 - Message Buffer 3

Freescale Semiconductor 27-1Chapter 27 Chip Configuration Module (CCM)The chip configuration module (CCM) controls the chip configuration and operati

Page 479 - 25.4.2 Receive Process

ColdFire CoreFreescale Semiconductor 2-72.2.5 Program Counter (PC)The PC contains the currently executing instruction address. During instruction exec

Page 480 - 25.4.2.1 Self-Received Frames

Chip Configuration Module (CCM)27-2 Freescale Semiconductor27.3 Block DiagramFigure 27-1. Chip Configuration Module Block Diagram27.4 Signal Descripti

Page 481 - 25.4.4 Remote Frames

Chip Configuration Module (CCM)Freescale Semiconductor 27-327.4.3 D[26:24, 21, 19:16] (Reset Configuration Override)If the external RCON pin is assert

Page 482 - 25.4.8 Bit Timing

Chip Configuration Module (CCM)27-4 Freescale Semiconductor27.5.3 Register DescriptionsThe following subsection describes the CCM registers.27.5.3.1 C

Page 483 - x ≤ 127

Chip Configuration Module (CCM)Freescale Semiconductor 27-527.5.3.2 Reset Configuration Register (RCON)At reset, RCON determines the default operation

Page 484 - 25-14 Freescale Semiconductor

Chip Configuration Module (CCM)27-6 Freescale Semiconductor27.5.3.3 Chip Identification Register (CIR)27.6 Functional DescriptionSix functions are def

Page 485 - 25.4.11.1 Debug Mode

Chip Configuration Module (CCM)Freescale Semiconductor 27-75. Clock mode selections6. Chip select configurationThese functions are described here.27.6

Page 486 - 25-16 Freescale Semiconductor

Chip Configuration Module (CCM)27-8 Freescale Semiconductor27.6.2 Chip Mode SelectionThe chip mode is selected during reset and reflected in the MODE

Page 487 - 25.5 Programmer’s Model

Chip Configuration Module (CCM)Freescale Semiconductor 27-9NOTEWhen Flash security is enabled, the chip will boot in single chip moderegardless of the

Page 488 - 15 14 13 12 11 10 9 8

Chip Configuration Module (CCM)27-10 Freescale Semiconductor27.6.6 Chip Select ConfigurationThe chip select configuration (CS[6:4]) is selected during

Page 489

Freescale Semiconductor 28-1Chapter 28 Queued Analog-to-Digital Converter (QADC)The queued analog-to-digital converter (QADC) is a 10-bit, unipolar,

Page 490

ColdFire Core2-8 Freescale Semiconductor2.2.9 Status Register (SR)The SR stores the processor status and includes the CCR, the interrupt priority mask

Page 491

Queued Analog-to-Digital Converter (QADC)28-2 Freescale Semiconductor28.2 Block Diagram Figure 28-1. QADC Block Diagram28.3 Modes of OperationThis su

Page 492 - 765 32 0

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-3• If during the execution of the current conversion, the queue operating mode for

Page 493 - 25.5.7 Rx Mask Registers

Queued Analog-to-Digital Converter (QADC)28-4 Freescale Semiconductor28.4.1.1 Port QA Analog Input SignalsWhen used as analog inputs, the four port QA

Page 494 - RX15MASK)

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-528.4.2.2 Port QB Digital I/O SignalsPort QB signals are referred to as PQB[3:0] w

Page 495 - 31 21 20 19 18 17 16

Queued Analog-to-Digital Converter (QADC)28-6 Freescale Semiconductor28.4.6 Voltage Reference SignalsVRH and VRL are the dedicated input signals for t

Page 496

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-728.6 Register DescriptionsThis subsection describes the QADC registers.28.6.1 QAD

Page 497

Queued Analog-to-Digital Converter (QADC)28-8 Freescale Semiconductor28.6.2 QADC Test Register (QADCTEST)The QADCTEST is a reserved register. Attempts

Page 498

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-9Note: The reset value for these fields is the current signal state if DDR is an

Page 499

Queued Analog-to-Digital Converter (QADC)28-10 Freescale Semiconductor 28.6.5 Control RegistersThis subsection describes the QADC control registers.28

Page 500

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-1111–7 — Reserved, should be cleared.6–0 QPR Prescaler clock divider. Selects the

Page 501

ColdFire CoreFreescale Semiconductor 2-92.3 Functional Description2.3.1 Version 2 ColdFire MicroarchitectureFrom the block diagram in Figure 2-1, the

Page 502 - 26-2 Freescale Semiconductor

Queued Analog-to-Digital Converter (QADC)28-12 Freescale Semiconductor28.6.5.2 QADC Control Register 1 (QACR1)QACR1 is the mode control register for q

Page 503 - Freescale Semiconductor 26-3

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-13Table 28-6. QACR1 Field DescriptionsBit(s) Name Description15 CIE1 Queue 1 compl

Page 504 - 26.1.3 Modes of Operation

Queued Analog-to-Digital Converter (QADC)28-14 Freescale Semiconductor28.6.5.3 QADC Control Register 2 (QACR2)QACR2 is the mode control register for q

Page 505

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-15for queue 1 and a trigger event occurs for queue 1 with BQ2 set to 0. Queue 1 ex

Page 506

Queued Analog-to-Digital Converter (QADC)28-16 Freescale SemiconductorTable 28-8. QACR2 Field DescriptionsBit(s) Name Description15 CIE2 Queue 2 compl

Page 507 - 31–24 23–16 15–8 7–0 Access

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-1728.6.6 Status RegistersThis subsection describes the QADC status registers.28.6.

Page 508

Queued Analog-to-Digital Converter (QADC)28-18 Freescale Semiconductor• When the currently completed CCW is in the last location of the CCW RAM.Once P

Page 509

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-19A queue is in the active state when a valid queue operating mode is selected, wh

Page 510

Queued Analog-to-Digital Converter (QADC)28-20 Freescale Semiconductor7 6 5 4 3210Field QS7 QS6 CWP5 CWP4 CWP3 CWP2 CWP1 CWP0Reset 0000_0000R/W: RAddr

Page 511

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-219–6 QS Queue status. Indicates the current condition of queue 1 and queue 2. The

Page 512

ColdFire Core2-10 Freescale SemiconductorFigure 2-10. Version 2 ColdFire Processor Operand Execution Pipeline DiagramThe instruction fetch pipeline pr

Page 513 - 76 5 4 3 2 1 0

Queued Analog-to-Digital Converter (QADC)28-22 Freescale Semiconductor0111 Queue 1 paused, queue 2 trigger pending1000 Queue 1 active, queue 2 idle100

Page 514

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-23Figure 28-12. Queue Status Transition28.6.6.2 QADC Status Register 1 (QASR1)Stop

Page 515

Queued Analog-to-Digital Converter (QADC)28-24 Freescale Semiconductor28.6.7 Conversion Command Word Table (CCW)The CCW table is 64 half-word (128 byt

Page 516

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-257 6 5 4 3210Field IST1 IST0 CHAN5 CHAN4 CHAN3 CHAN2 CHAN1 CHAN0Reset UndefinedR/

Page 517

Queued Analog-to-Digital Converter (QADC)28-26 Freescale SemiconductorTable 28-15. Input Sample TimesIST[1:0] Input Sample Times00 Input sample time =

Page 518

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-2728.6.8 Result RegistersThe result word table is a 64 half-word (128 byte) long b

Page 519

Queued Analog-to-Digital Converter (QADC)28-28 Freescale Semiconductor28.6.8.3 Left-Justified Unsigned Result Register (LJURR)28.7 Functional Descript

Page 520

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-29Specifically, this means that while the QADC is operating, the data in the resul

Page 521 - 15 12 11 10 9 8

Queued Analog-to-Digital Converter (QADC)28-30 Freescale Semiconductor Figure 28-18. External Multiplexing ConfigurationWhen externally multiplexed m

Page 522

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-31Figure 28-18 shows that the two MA signals may also be analog input signals. Whe

Page 523

ColdFire CoreFreescale Semiconductor 2-11instruction execution is performed in the second stage (EX) in one of the execute engines (e.g., ALU, barrel

Page 524

Queued Analog-to-Digital Converter (QADC)28-32 Freescale SemiconductorFigure 28-19. QADC Analog Subsystem Block Diagram28.7.3.2 Conversion Cycle Times

Page 525

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-33Figure 28-20. Conversion TimingIf the amplifier bypass mode is enabled for a con

Page 526

Queued Analog-to-Digital Converter (QADC)28-34 Freescale Semiconductor28.7.3.6 BiasThe bias circuit is controlled by the STOP signal to power-up and p

Page 527 - 26.4 Functional Description

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-35completion or the paused state, queue 2 begins executing again. The programming

Page 528

Queued Analog-to-Digital Converter (QADC)28-36 Freescale SemiconductorFigure 28-22. QADC Queue Operation with PauseTrigger events which occur during t

Page 529

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-37The following paragraphs and figures outline the prioritizing criteria used to d

Page 530 - 27.4 Signal Descriptions

Queued Analog-to-Digital Converter (QADC)28-38 Freescale SemiconductorThe first three examples in Figure 28-23 through Figure 28-25 (S1, S2, and S3) s

Page 531 - Bits 31–16 Bits 15–0 Access

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-39 Figure 28-25. CCW Priority Situation 3The next two situations consider trigger

Page 532 - 15 14 11 10 8 7 6 5 4 3 2 0

Queued Analog-to-Digital Converter (QADC)28-40 Freescale Semiconductor Figure 28-27. CCW Priority Situation 5The remaining situations, S6 through S11,

Page 533 - 15 109876 5 43 2 1 0

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-41 .Figure 28-29. CCW Priority Situation 7Situations S8 and S9 (Figure 28-30 and F

Page 534 - 27.6 Functional Description

ColdFire Core2-12 Freescale SemiconductorFigure 2-12. V2 OEP Embedded-Load Part 1Figure 2-13. V2 OEP Embedded-Load Part 2For register-to-memory (store

Page 535 - 27.6.1 Reset Configuration

Queued Analog-to-Digital Converter (QADC)28-42 Freescale SemiconductorFigure 28-31. CCW Priority Situation 9Situations S10 and S11 (Figure 28-32 and F

Page 536 - 27.6.2 Chip Mode Selection

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-43Figure 28-33. CCW Priority Situation 11The previous situations cover normal over

Page 537 - 27.6.5 Clock Mode Selection

Queued Analog-to-Digital Converter (QADC)28-44 Freescale SemiconductorFigure 28-35. CCW Freeze Situation 13Figure 28-36. CCW Freeze Situation 14Figure

Page 538 - 27.8 Interrupts

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-45Figure 28-39. CCW Freeze Situation 17Figure 28-40. CCW Freeze Situation 18Figure

Page 539

Queued Analog-to-Digital Converter (QADC)28-46 Freescale Semiconductor• BQ2 (beginning of queue 2) is set beyond the end of the CCW table (64–127) and

Page 540 - 28.3 Modes of Operation

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-4728.8.4 Disabled ModeWhen disabled mode is selected, the queue is not active. Tri

Page 541 - 28.4 Signals

Queued Analog-to-Digital Converter (QADC)28-48 Freescale Semiconductor28.8.6.1 Software-Initiated Single-Scan ModeSoftware can initiate the execution

Page 542 - 28-4 Freescale Semiconductor

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-49bit should be cleared before another scan of queue 1 is initiated during the nex

Page 543

Queued Analog-to-Digital Converter (QADC)28-50 Freescale SemiconductorIn the case of software-initiated continuous-scan mode, the trigger event is gen

Page 544 - MSB LSB Access

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-51polarity of the external trigger signal is programmable, so that a mode which be

Page 545

ColdFire CoreFreescale Semiconductor 2-13For read-modify-write instructions, the pipeline effectively combines an embedded-load with a store operation

Page 546

Queued Analog-to-Digital Converter (QADC)28-52 Freescale Semiconductortrigger events. Because both queues may be triggered by the periodic/interval ti

Page 547

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-53• Both queue 1 and queue 2 are programmed to any mode which does not use the per

Page 548 - 7 6 5 4 3210

Queued Analog-to-Digital Converter (QADC)28-54 Freescale SemiconductorFigure 28-43. QADC Conversion Queue OperationTo prepare the QADC for a scan sequ

Page 549 - Divide-by Values

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-55• ResolutionDuring initial sample, a buffered version of the selected input chan

Page 550 - Divide-by Values (continued)

Queued Analog-to-Digital Converter (QADC)28-56 Freescale SemiconductorNOTEAlthough the result RAM can be written, some write operations, like bitmanip

Page 551

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-57Figure 28-44. Equivalent Analog Input CircuitryBecause the sample amplifier is p

Page 552

Queued Analog-to-Digital Converter (QADC)28-58 Freescale SemiconductorFigure 28-45. Errors Resulting from Clipping28.9.3 Conversion Timing SchemesThis

Page 553

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-59Figure 28-46. External Positive Edge Trigger Mode Timing with PauseA time separa

Page 554

Queued Analog-to-Digital Converter (QADC)28-60 Freescale SemiconductorAt the end of Q1,the completion flag CF1 sets and the queue restarts. If the que

Page 555 - 28.6.6 Status Registers

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-6128.9.4 Analog Supply Filtering and GroundingTwo important factors influencing pe

Page 556 - 28-18 Freescale Semiconductor

vi Freescale Semiconductor2.2.9 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82.2.

Page 557

ColdFire Core2-14 Freescale SemiconductorFigure 2-15. V2 OEP Pipeline Execution Templates2.3.2 Instruction Set Architecture (ISA_A+)The original ColdF

Page 558

Queued Analog-to-Digital Converter (QADC)28-62 Freescale SemiconductorFigure 28-49. Star-Ground at the Point of Power Supply OriginOther suggestions f

Page 559 - Table 28-12. Queue Status

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-63Figure 28-50 shows an active parasitic bipolar NPN transistor when an input sign

Page 560

Queued Analog-to-Digital Converter (QADC)28-64 Freescale Semiconductor28.9.6 Analog Input ConsiderationsThe source impedance of the analog signal to b

Page 561

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-65 Figure 28-52. External Multiplexing of Analog Signal SourcesCPCSAMPCPCSAMPCIn =

Page 562 - 15 10 9 8

Queued Analog-to-Digital Converter (QADC)28-66 Freescale Semiconductor28.9.7 Analog Input PinsAnalog inputs should have low AC impedance at the pins.

Page 563

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-6728.9.7.1 Settling Time for the External CircuitThe values for RSRC, RF, and CF i

Page 564

Queued Analog-to-Digital Converter (QADC)28-68 Freescale SemiconductorCAUTIONLeakage below 200 nA is obtainable only within a limited temperaturerange

Page 565

Queued Analog-to-Digital Converter (QADC)Freescale Semiconductor 28-69result is written for a CCW with the pause bit set, the queue pause flag is set,

Page 566 - 28.7 Functional Description

Queued Analog-to-Digital Converter (QADC)28-70 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 567 - 28.7.2 External Multiplexing

Freescale Semiconductor 29-1Chapter 29 Reset Controller ModuleThe reset controller is provided to determine the cause of reset, assert the appropriat

Page 568 - 28-30 Freescale Semiconductor

ColdFire CoreFreescale Semiconductor 2-15Table 2-4 summarizes the instructions added to revision ISA_A to form revision ISA_A+. For more details see t

Page 569 - 28.7.3 Analog Subsystem

Reset Controller Module29-2 Freescale SemiconductorFigure 29-1. Reset Controller Block Diagram29.3 SignalsTable 29-1 provides a summary of the reset c

Page 570 - 28-32 Freescale Semiconductor

Reset Controller ModuleFreescale Semiconductor 29-329.4.1 Reset Control Register (RCR)The RCR allows software control for requesting a reset, for inde

Page 571 - 28.7.3.5 Comparator

Reset Controller Module29-4 Freescale Semiconductor29.4.2 Reset Status Register (RSR)The RSR contains a status bit for every reset source. When reset

Page 572 - 28.8.1.1 Queue Priority

Reset Controller ModuleFreescale Semiconductor 29-529.5 Functional Description29.5.1 Reset SourcesTable 29-5 defines the sources of reset and the sign

Page 573 - Freescale Semiconductor 28-35

Reset Controller Module29-6 Freescale SemiconductorAsynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control lo

Page 574 - 28-36 Freescale Semiconductor

Reset Controller ModuleFreescale Semiconductor 29-729.5.2 Reset Control FlowThe reset logic control flow is shown in Figure 29-4. In this figure, the

Page 575 - Table 28-23. Status Bits

Reset Controller Module29-8 Freescale SemiconductorFigure 29-4. Reset Control FlowRSTIPIN OR WD TIMEOUTOR SW RESET?LOSS OF CLOCK?LOSS OF LOCK?RSTI NEG

Page 576 - 28-38 Freescale Semiconductor

Reset Controller ModuleFreescale Semiconductor 29-929.5.2.1 Synchronous Reset RequestsIn this discussion, the reference in parentheses refer to the st

Page 577 - Freescale Semiconductor 28-39

Reset Controller Module29-10 Freescale Semiconductor29.5.3.2 Reset Status FlagsFor a POR reset, the POR and LVD bits in the RSR are set, and the SOFT,

Page 578 - 28-40 Freescale Semiconductor

Freescale Semiconductor 30-1Chapter 30 Debug SupportThis chapter describes the Revision A enhanced hardware debug support.30.1 OverviewThe debug modu

Page 579 - Freescale Semiconductor 28-41

ColdFire Core2-16 Freescale Semiconductor3. The processor saves the current context by creating an exception stack frame on the system stack. The exce

Page 580 - 28-42 Freescale Semiconductor

Debug Support30-2 Freescale Semiconductor30.2 Signal DescriptionTable 30-1 describes debug module signals. All ColdFire debug signals are unidirection

Page 581 - Freescale Semiconductor 28-43

Debug SupportFreescale Semiconductor 30-3branch target address calculation is based on the contents of a program-visible register (variantaddressing).

Page 582 - 28-44 Freescale Semiconductor

Debug Support30-4 Freescale Semiconductor30.3.1 Begin Execution of Taken Branch (PST = 0x5)PST is 0x5 when a taken branch is executed. For some opcode

Page 583 - 28.8.2 Boundary Conditions

Debug SupportFreescale Semiconductor 30-5target instruction. The PST can continue with the next instruction before the address has completelydisplayed

Page 584 - 28.8.3 Scan Modes

Debug Support30-6 Freescale SemiconductorFigure 30-4. Debug Programming ModelThese registers are accessed through the BDM port by the commands, WDMREG

Page 585 - 28.8.6 Single-Scan Modes

Debug SupportFreescale Semiconductor 30-7NOTEDebug control registers can be written by the external development systemor the CPU through the WDEBUG in

Page 586 - 28-48 Freescale Semiconductor

Debug Support30-8 Freescale SemiconductorTable 30-5 describes AATR fields.151413121110 8765432 0Field RM SZM TTM TMM R SZ TT TMReset 0000_0000_0000_01

Page 587 - 28.8.7 Continuous-Scan Modes

Debug SupportFreescale Semiconductor 30-930.4.3 Address Breakpoint Registers (ABLR, ABHR)The ABLR and ABHR, shown in Figure 30-6, define regions in th

Page 588 - 28-50 Freescale Semiconductor

Debug Support30-10 Freescale SemiconductorTable 30-6 describes ABLR fields. Table 30-7 describes ABHR fields.30.4.4 Configuration/Status Register (CSR

Page 589 - Freescale Semiconductor 28-51

Debug SupportFreescale Semiconductor 30-11Table 30-8 describes CSR fields. Table 30-8. CSR Field DescriptionsBit Name Description31–28 BSTAT Breakpoin

Page 590 - 28-52 Freescale Semiconductor

ColdFire CoreFreescale Semiconductor 2-17All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers. Th

Page 591 - Freescale Semiconductor 28-53

Debug Support30-12 Freescale Semiconductor30.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)The DBR, shown in Figure 30-8, specifies data patterns used

Page 592 - 28-54 Freescale Semiconductor

Debug SupportFreescale Semiconductor 30-13Table 30-9 describes DBR fields.Table 30-10 describes DBMR fields.The DBR supports both aligned and misalign

Page 593 - 28.8.11 Result Word Table

Debug Support30-14 Freescale SemiconductorTable 30-12 describes PBR fields.Figure 30-9 shows PBMR.Table 30-13 describes PBMR fields.30.4.7 Trigger Def

Page 594 - 28.9.2 Analog Power Signals

Debug SupportFreescale Semiconductor 30-15NOTEThe debug module has no hardware interlocks, so to prevent spuriousbreakpoint triggers while the breakpo

Page 595 - Freescale Semiconductor 28-57

Debug Support30-16 Freescale Semiconductor30.5 Background Debug Mode (BDM)The ColdFire Family implements a low-level system debugger in the microproce

Page 596 - 28-58 Freescale Semiconductor

Debug SupportFreescale Semiconductor 30-171. A catastrophic fault-on-fault condition automatically halts the processor.2. A hardware breakpoint can be

Page 597 - Freescale Semiconductor 28-59

Debug Support30-18 Freescale Semiconductor30.5.2 BDM Serial InterfaceWhen the CPU is halted and PST reflects the halt status, the development system c

Page 598 - 28-60 Freescale Semiconductor

Debug SupportFreescale Semiconductor 30-19.Table 30-15 describes receive BDM packet fields. 30.5.2.2 Transmit Packet FormatThe basic transmit packet,

Page 599 - Freescale Semiconductor 28-61

Debug Support30-20 Freescale SemiconductorUnassigned command opcodes are reserved by Freescale. All unused command formats within anyrevision level pe

Page 600 - 28-62 Freescale Semiconductor

Debug SupportFreescale Semiconductor 30-21Table 30-18 describes BDM fields.30.5.3.1.1 Extension Words as RequiredSome commands require extension words

Page 601 - Eqn. 28-2

ColdFire Core2-18 Freescale Semiconductor• The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor for all

Page 602 - 28-64 Freescale Semiconductor

Debug Support30-22 Freescale SemiconductorFigure 30-16. Command Sequence DiagramThe sequence is as follows:• In cycle 1, the development system comman

Page 603 - Freescale Semiconductor 28-65

Debug SupportFreescale Semiconductor 30-23NOTEThe BDM status bit (S) is 0 for normally completed commands; S = 1 forillegal commands, not-ready respon

Page 604 - 28.9.7 Analog Input Pins

Debug Support30-24 Freescale SemiconductorCommand SequenceFigure 30-20. WAREG/WDREG Command SequenceOperand Data Longword data is written into the spe

Page 605 - Filter Capacitor (CF)

Debug SupportFreescale Semiconductor 30-25Command/Result Formats:Command Sequence:Figure 30-22. READ Command SequenceOperand Data The only operand is

Page 606 - 28.10 Interrupts

Debug Support30-26 Freescale Semiconductor30.5.3.3.4 Write Memory Location (WRITE)Write data to the memory location specified by the longword address.

Page 607 - Freescale Semiconductor 28-69

Debug SupportFreescale Semiconductor 30-27Command Sequence:Figure 30-24. WRITE Command SequenceOperand Data This two-operand instruction requires a lo

Page 608 - 28-70 Freescale Semiconductor

Debug Support30-28 Freescale SemiconductorNOTEDUMP does not check for a valid address; it is a valid command only whenpreceded by NOP, READ, or anothe

Page 609

Debug SupportFreescale Semiconductor 30-29Command Sequence:Figure 30-26. DUMP Command SequenceOperand Data: NoneResult Data: Requested data is returne

Page 610 - 29.4 Memory Map and Registers

Debug Support30-30 Freescale SemiconductorCommand Sequence:Figure 30-28. FILL Command SequenceOperand Data: A single operand is data to be written to

Page 611 - Bits 7:0 Access

Debug SupportFreescale Semiconductor 30-3130.5.3.3.7 Resume Execution (GO)The pipeline is flushed and refilled before normal instruction execution res

Page 612

ColdFire CoreFreescale Semiconductor 2-19execution until all previous operations, including all pending write operations, are complete. If any previou

Page 613 - 29.5 Functional Description

Debug Support30-32 Freescale SemiconductorCommand/Result Formats:Rc encoding:15 12 11 8 7 4 3 0Command 0x2 0x9 0x8 0x00x0 0x0 0x0 0x00x0 RcResult D[31

Page 614 - 29-6 Freescale Semiconductor

Debug SupportFreescale Semiconductor 30-33Command Sequence:Figure 30-34. RCREG Command SequenceOperand Data: The only operand is the 32-bit Rc control

Page 615 - 29.5.2 Reset Control Flow

Debug Support30-34 Freescale Semiconductor rcreg accn; // read the desired accumulator wcreg #saved_data,macsr;// restore the

Page 616 - 29-8 Freescale Semiconductor

Debug SupportFreescale Semiconductor 30-35Command Sequence:Figure 30-36. WCREG Command SequenceOperand Data: This instruction requires two longword op

Page 617 - 29.5.3 Concurrent Resets

Debug Support30-36 Freescale SemiconductorCommand Sequence:Figure 30-38. RDMREG Command SequenceOperand Data: NoneResult Data: The contents of the sel

Page 618 - 29.5.3.2 Reset Status Flags

Debug SupportFreescale Semiconductor 30-3730.6 Real-Time Debug SupportThe ColdFire Family provides support debugging real-time applications. For these

Page 619

Debug Support30-38 Freescale Semiconductorenabled when interrupt sampling occurs. For address and data breakpoints, reporting is consideredimprecise b

Page 620 - 30.3 Real-Time Trace Support

Debug SupportFreescale Semiconductor 30-39complete before freeing the local bus for the debug module to perform its access. After the debug modulebus

Page 621

Debug Support30-40 Freescale Semiconductoraddq.l #imm,<ea>x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}addx.l Dy,Dx PST =

Page 622

Debug SupportFreescale Semiconductor 30-41extb.l Dx PST = 0x1ff1.l Dx PST = 0x1jmp <ea>x PST = 0x5, {PST = [0x9AB], DD = target address} 1jsr &l

Page 623 - 30.4 Programming Model

ColdFire Core2-20 Freescale SemiconductorIn the original M68000 ISA definition, lines A and F were effectively reserved for user-defined operations (l

Page 624 - RDMREG and WDMREG commands

Debug Support30-42 Freescale SemiconductorException ProcessingPST = 0xC,{PST = 0xB,DD = destination},// stack frame{PST = 0xB,DD = destination},// sta

Page 625

Debug SupportFreescale Semiconductor 30-43For all types of exception processing, the PST = 0xC value is driven at all times, unless the PST output isn

Page 626 - WDMREG command

Debug Support30-44 Freescale SemiconductorThe move-to-SR, STLDSR, and RTE instructions include an optional PST = 0x3 value, indicating an entryinto us

Page 627

Debug SupportFreescale Semiconductor 30-4530.8 Freescale-Recommended BDM PinoutThe ColdFire BDM connector, Figure 30-41, is a 26-pin Berg connector ar

Page 628 - 1514131211109 8 76543 0

Debug Support30-46 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 629

Freescale Semiconductor 31-1Chapter 31 IEEE 1149.1 Test Access Port (JTAG)The Joint Test Action Group, or JTAG, is a dedicated user-accessible test l

Page 630

IEEE 1149.1 Test Access Port (JTAG)31-2 Freescale Semiconductor31.1 FeaturesThe basic features of the JTAG module are the following:• Performs boundar

Page 631

IEEE 1149.1 Test Access Port (JTAG)Freescale Semiconductor 31-3When one module is selected, the inputs into the other module are disabled or forced to

Page 632

IEEE 1149.1 Test Access Port (JTAG)31-4 Freescale SemiconductorThe DSCLK pin clocks the serial communication port to the debug module. Maximum frequen

Page 633

IEEE 1149.1 Test Access Port (JTAG)Freescale Semiconductor 31-531.4.2.3 Bypass RegisterThe bypass register is a single-bit shift register path from TD

Page 634 - 30.5.1 CPU Halt

ColdFire CoreFreescale Semiconductor 2-213. The processor then generates a trace exception. The PC in the exception stack frame points to the instruct

Page 635 - Freescale Semiconductor 30-17

IEEE 1149.1 Test Access Port (JTAG)31-6 Freescale Semiconductor31.5.2 TAP Controller The TAP controller is a state machine that changes state based on

Page 636 - 30.5.2 BDM Serial Interface

IEEE 1149.1 Test Access Port (JTAG)Freescale Semiconductor 31-7 31.5.3.1 External Test Instruction (EXTEST)The EXTEST instruction selects the boundary

Page 637 - 30.5.3 BDM Command Set

IEEE 1149.1 Test Access Port (JTAG)31-8 Freescale Semiconductoraccessible by shifting it through the boundary scan register to the TDO output by using

Page 638

IEEE 1149.1 Test Access Port (JTAG)Freescale Semiconductor 31-931.5.3.8 CLAMP InstructionThe CLAMP instruction selects the bypass register and asserts

Page 639 - 15 1098765432 0

IEEE 1149.1 Test Access Port (JTAG)31-10 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 640 - 30-22 Freescale Semiconductor

Freescale Semiconductor 32-1Chapter 32 Mechanical DataThis chapter contains drawings showing the pinout and the packaging and mechanical characterist

Page 641 - WAREG/WDREG Command Format

Mechanical Data32-2 Freescale SemiconductorFigure 32-1. MCF528x Pinout (256 MAPBGA)123456 7 8 910111213 14 1516A VSS A15 A16 A18 A21 VPPETXD3 ETXCLK

Page 642 - WAREG/WDREG Command Sequence

Mechanical DataFreescale Semiconductor 32-3Figure 32-2 is the pinout for the MCF5214 and MCF5216. The shaded cells illustrate the differencesbetween t

Page 643

Mechanical Data32-4 Freescale SemiconductorTable 32-1 lists the MCF521x and MCF528x signals in pin number order for the 256 MAPBGA package.The shaded

Page 644 - WRITE Command Format

Mechanical DataFreescale Semiconductor 32-5B8 (MCF521x) NC — — K8 VSS — —B8 (MCF528x) ERXER PEL0 —B9 (MCF521x) PEL2 — — K9 VSS — —B9 (MCF528x) ERXD2 P

Page 645 - WRITE Command Sequence

ColdFire Core2-22 Freescale Semiconductor2.3.4.11 TRAP Instruction ExceptionThe TRAP #n instruction always forces an exception as part of its executio

Page 646

Mechanical Data32-6 Freescale SemiconductorC16 IRQ3PNQ3 — L16 CS3 PJ3 —D1 A9 PG1 — M1 D11 PC3 —D2 A8 PG0 — M2 D10 PC2 —D3 A7 PH7 — M3 D9 PC1 —D4 A6 PH

Page 647 - Freescale Semiconductor 30-29

Mechanical DataFreescale Semiconductor 32-7E12 VSS — — N12 GPTB0 PTB0 —E13 CANTX PAS2 UTXD2 N13 GPTA0 PTA0 —E14 SDA PAS1 URXD2 N14 SIZ1 PE3 SYNCAE15 S

Page 648

Mechanical Data32-8 Freescale SemiconductorG12 VDD — — R12 GPTB2 PTB2 —G13 QSPI_CS2 PQS5 — R13 GPTA2 PTA2 —G14 QSPI_CS3 PQS6 — R14 CLKMOD0 — —G15 DRAM

Page 649

Mechanical DataFreescale Semiconductor 32-9Figure 32-3. 256 MAPBGA Package Dimensions32.2 Ordering InformationTable 32-2. Orderable Part NumbersFreesc

Page 650

Mechanical Data32-10 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 651

Freescale Semiconductor 33-1Chapter 33 Electrical CharacteristicsThis chapter contains electrical specification tables and reference timing diagrams

Page 652

Electrical Characteristics33-2 Freescale Semiconductor33.2 Thermal CharacteristicsTable 33-2 lists thermal resistance values.2This device contains cir

Page 653 - 15 12 11 8 7 5 4 0

Electrical CharacteristicsFreescale Semiconductor 33-333.3 DC Electrical Specifications 5Thermal characterization parameter indicating the temperature

Page 654

Electrical Characteristics33-4 Freescale Semiconductor33.4 Power Consumption SpecificationsFigure 33-1 shows typical WAIT/DOZE and RUN mode power cons

Page 655 - 30.6 Real-Time Debug Support

Electrical CharacteristicsFreescale Semiconductor 33-5Figure 33-1. Typical WAIT/DOZE Mode Current ConsumptionTable 33-5 lists the estimated power cons

Page 656 - 30.6.1.1 Emulator Mode

ColdFire CoreFreescale Semiconductor 2-23ColdFire processors load hardware configuration information into the D0 and D1 general-purpose registers afte

Page 657 - 30.7.1 User Instruction Set

Electrical Characteristics33-6 Freescale SemiconductorTable 33-7 lists the maximum power consumption specifications.Table 33-6. Typical Application Po

Page 658

Electrical CharacteristicsFreescale Semiconductor 33-733.5 Phase Lock Loop Electrical Specifications Table 33-8. PLL Electrical Specifications(VDD and

Page 659

Electrical Characteristics33-8 Freescale Semiconductor33.6 QADC Electrical Characteristics6Load Capacitance determined from crystal manufacturer speci

Page 660

Electrical CharacteristicsFreescale Semiconductor 33-9Table 33-10. QADC Electrical Specifications (Operating) 1(VDDH and VDDA = 5.0 Vdc ± 0.5V, VDD =

Page 661

Electrical Characteristics33-10 Freescale Semiconductor33.7 Flash Memory CharacteristicsThe Flash memory characteristics are shown in Table 33-12 and

Page 662

Electrical CharacteristicsFreescale Semiconductor 33-1133.8 External Interface Timing CharacteristicsTable 33-14 lists processor bus input timings. NO

Page 663

Electrical Characteristics33-12 Freescale SemiconductorFigure 33-2. General Input Timing Requirements33.9 Processor Bus Output Timing SpecificationsTa

Page 664 - 30-46 Freescale Semiconductor

Electrical CharacteristicsFreescale Semiconductor 33-13Read/write bus timings listed in Table 33-15 are shown in Figure 33-3, Figure 33-4, and Figure

Page 665

Electrical Characteristics33-14 Freescale SemiconductorFigure 33-3. Read/Write (Internally Terminated) TimingFigure 33-4 shows a bus cycle terminated

Page 666 - 31.2 Modes of Operation

Electrical CharacteristicsFreescale Semiconductor 33-15Figure 33-4. Read Bus Cycle Terminated by TAFigure 33-5 shows a bus cycle terminated by TEA; it

Page 667

Freescale Semiconductor vii3.3.1.2 Saving and Restoring the EMAC Programming Model . . . . . . . . . . . . 3-113.3.1.3 MULS/MULU . . . . . . . . . . .

Page 668 - 15 12 11 10

ColdFire Core2-24 Freescale SemiconductorInformation loaded into D1 defines the local memory hardware configuration as shown in the figure below.11–8

Page 669 - 31.5 Functional Description

Electrical Characteristics33-16 Freescale SemiconductorFigure 33-5. Read Bus Cycle Terminated by TEAFigure 33-6 shows an SDRAM read cycle. CLKOUTCSnA[

Page 670 - 31.5.3 JTAG Instructions

Electrical CharacteristicsFreescale Semiconductor 33-17Figure 33-6. SDRAM Read CycleTable 33-16. SDRAM TimingNUM Characteristic11All timing specificat

Page 671 - 31.5.3.2 IDCODE Instruction

Electrical Characteristics33-18 Freescale SemiconductorFigure 33-7 shows an SDRAM write cycle. Figure 33-7. SDRAM Write Cycle33.10 General Purpose I/O

Page 672 - 31.5.3.6 HIGHZ Instruction

Electrical CharacteristicsFreescale Semiconductor 33-19Figure 33-8. GPIO Timing33.11 Reset and Configuration Override Timing 1GPIO pins include: Ports

Page 673 - 31.6.1 Restrictions

Electrical Characteristics33-20 Freescale Semiconductor Figure 33-9. RSTI and Configuration Override Timing33.12 I2C Input/Output Timing Specification

Page 674 - 31-10 Freescale Semiconductor

Electrical CharacteristicsFreescale Semiconductor 33-21Figure 33-10 shows timing for the values in Table 33-19 and Table 33-20.Figure 33-10. I2C Input

Page 675

Electrical Characteristics33-22 Freescale SemiconductorFigure 33-11 shows MII receive signal timings listed in Table 33-21. Figure 33-11. MII Receive

Page 676 - 32-2 Freescale Semiconductor

Electrical CharacteristicsFreescale Semiconductor 33-23Figure 33-12. MII Transmit Signal Timing Diagram33.13.3 MII Async Inputs Signal Timing (ECRS an

Page 677 - Freescale Semiconductor 32-3

Electrical Characteristics33-24 Freescale SemiconductorFigure 33-14. MII Serial Management Channel Timing Diagram33.14 DMA Timer Module AC Timing Spec

Page 678

Electrical CharacteristicsFreescale Semiconductor 33-25Figure 33-15. QSPI Timing33.16 JTAG and Boundary Scan TimingTable 33-27. JTAG and Boundary Scan

Page 679

ColdFire CoreFreescale Semiconductor 2-252.3.5 Instruction Execution TimingThis section presents processor instruction execution times in terms of pro

Page 680

Electrical Characteristics33-26 Freescale SemiconductorFigure 33-16. Test Clock Input TimingFigure 33-17. Boundary Scan (JTAG) Timing Figure 33-18. T

Page 681

Electrical CharacteristicsFreescale Semiconductor 33-27 Figure 33-19. TRST Timing Figure 33-20. BKPT Timing33.17 Debug AC Timing SpecificationsTable 3

Page 682

Electrical Characteristics33-28 Freescale SemiconductorFigure 33-21. Real-Time Trace AC TimingFigure 33-22 shows BDM serial port AC timing for the val

Page 683 - 32.2 Ordering Information

Freescale Semiconductor A-1Appendix ARegister Memory MapTable A-1 summarizes the address, name, and byte assignment for registers within the CPU space

Page 684 - 32-10 Freescale Semiconductor

Register Memory MapA-2 Freescale SemiconductorTable A-2. Module Memory Map OverviewAddress Module SizeIPSBAR + 0x00_0000 System Control Module 64 byte

Page 685

Register Memory MapFreescale Semiconductor A-3IPSBAR + 0x1C_0000 FlexCAN 64KIPSBAR + 0x1D_0000 CFM (Flash) Control Registers 64KIPSBAR + 0x400_0000 CF

Page 686 - 33.2 Thermal Characteristics

Register Memory MapA-4 Freescale SemiconductorIPSBAR + 0x054 DRAM Mask Register Block 1 DMR1 32Chip Select RegistersIPSBAR + 0x080 Chip Select Address

Page 687

Register Memory MapFreescale Semiconductor A-5IPSBAR + 0x14C Byte Count Register 1 BCR1132IPSBAR + 0x150 DMA Status Register 1 DSR1 8IPSBAR + 0x180 So

Page 688 - (continued)

Register Memory MapA-6 Freescale SemiconductorIPSBAR + 0x238 (Read) Reserved 8(Write) UART Output Port Bit Set Command Register 0UOP10 8IPSBAR + 0x23C

Page 689

Register Memory MapFreescale Semiconductor A-7IPSBAR + 0x288 (Read) Reserved 8(Write) UART Command Register 2 UCR2 8IPSBAR + 0x28C (Read) UART Receive

Page 690 - Program or Erase

ColdFire Core2-26 Freescale Semiconductor• R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation performing

Page 691

Register Memory MapA-8 Freescale SemiconductorDMA Timer RegistersIPSBAR + 0x400 DMA Timer Mode Register 0 DTMR0 16IPSBAR + 0x402 DMA Timer Extended Mo

Page 692

Register Memory MapFreescale Semiconductor A-9IPSBAR + 0xC18 Interrupt Level Request Register 0 ILRR0 8IPSBAR + 0XC19 Interrupt Acknowledge Level and

Page 693 - ± 0.5V, V

Register Memory MapA-10 Freescale SemiconductorIPSBAR + 0xC61 Interrupt Control Register 0-33 ICR033 8ISPBAR + 0xC62 Interrupt Control Register 0-34 I

Page 694

Register Memory MapFreescale Semiconductor A-11IPSBAR + 0xCEC Level 3 Interrupt Acknowledge Register 0 L3IACKR0 8IPSBAR + 0xCF0 Level 4 Interrupt Ackn

Page 695

Register Memory MapA-12 Freescale SemiconductorIPSBAR + 0xD5A Interrupt Control Register 1-26 ICR126 8IPSBAR + 0xDE0 Software Interrupt Acknowledge Re

Page 696

Register Memory MapFreescale Semiconductor A-13IPSBAR + 0x1118 Upper 32 bits of individual hash table IAUR 32IPSBAR + 0x111C Lower 32 bits of individu

Page 697

Register Memory MapA-14 Freescale SemiconductorIPSBAR + 0x10_000CPort AS Output Data Register PORTAS 8IPSBAR + 0x10_000DPort QS Output Data Register P

Page 698

Register Memory MapFreescale Semiconductor A-15IPSBAR + 0x10_0022Port SD Data Direction Register DDRSD 8IPSBAR + 0x10_0023Port TC Data Direction Regis

Page 699

Register Memory MapA-16 Freescale SemiconductorIPSBAR + 0x10_0038Port TD Pin Data/Set Data Register PORTTDP/SETTD8IPSBAR + 0x10_0039Port UA Pin Data/S

Page 700

Register Memory MapFreescale Semiconductor A-17IPSBAR + 0x10_0050Port B, C, and D Pin Assignment Register PBCDPAR 8IPSBAR + 0x10_0051Port F Pin Assign

Page 701 - Table 33-16. SDRAM Timing

ColdFire CoreFreescale Semiconductor 2-27The nomenclature xxx.wl refers to both forms of absolute addressing, xxx.w and xxx.l.ET with {<ea> = (d

Page 702 - Table 33-17. GPIO Timing

Register Memory MapA-18 Freescale SemiconductorEdge Port RegistersIPSBAR + 0x13_0000EPORT Pin Assignment Register EPPAR 16IPSBAR + 0x13_0002EPORT Data

Page 703 - Figure 33-8. GPIO Timing

Register Memory MapFreescale Semiconductor A-19IPSBAR + 0x17_0002PIT Modulus Register 2 PMR 2 16IPSBAR + 0x17_0004PIT Count Register 2 PCNTR 2 16Progr

Page 704 - Table 33-20. I

Register Memory MapA-20 Freescale SemiconductorIPSBAR + 0x1A_0002GPTA Output Compare 3 Mask Register GPTAOC3M 8IPSBAR + 0x1A_0003GPTA Output Compare 3

Page 705 - C Input/Output Timings

Register Memory MapFreescale Semiconductor A-21General Purpose Timer B RegistersIPSBAR + 0x1B_0000GPTB IC/OC Select Register GPTBIOS 8IPSBAR + 0x1B_00

Page 706

Register Memory MapA-22 Freescale SemiconductorIPSBAR + 0x1B_001APulse Accumulator Counter Register GPTBPACNT 16IPSBAR + 0x1B_001DGPTB Port Data Regis

Page 707

Register Memory MapFreescale Semiconductor A-23IPSBAR + 0x1D_0002CFM Clock Divider Register CFMCLKD 8IPSBAR + 0x1D_0008CFM Security RegisterCFMSEC32IP

Page 708

Register Memory MapA-24 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 709 - Symbol Min Max Unit

Freescale Semiconductor B-1Appendix B Revision HistoryThis appendix lists major changes between versions of the MCF5282UM document.B.1 Changes Betwee

Page 710

Revision HistoryB-2 Freescale SemiconductorB.2 Changes Between Rev. 0.1 and Rev. 1Figure 32-1 on page 32-2Changed “RAS0” and “RAS1” to “SDRAM_CS0” and

Page 711 - Figure 33-20. BKPT Timing

Revision HistoryFreescale Semiconductor B-3Chapter 8, “System Control Module (SCM) and 16.2/16-2Moved information in Section 8.4.6, “DMA Request Contr

Page 712

ColdFire Core2-28 Freescale Semiconductor2.3.5.3 Standard One Operand Instruction Execution Times2.3.5.4 Standard Two Operand Instruction Execution Ti

Page 713

Revision HistoryB-4 Freescale SemiconductorTable 25-12 on page 25-22Changed equation in PRES_DIV field description to the following:27.6.2/27-8 Added

Page 714

Revision HistoryFreescale Semiconductor B-5B.3 Changes Between Rev. 1 and Rev. 233.13/33-21 Added timing diagrams and tables to Section 33.13, “Fast E

Page 715

Revision HistoryB-6 Freescale SemiconductorTable 8-3/8-5 Add the following note to the BDE bit description: “The SPV bit in the CPU’s RAMBAR must also

Page 716

Revision HistoryFreescale Semiconductor B-7B.4 Changes Between Rev. 2 and Rev. 2.1B.5 Changes Between Rev. 2.1 and Rev. 2.2B.6 Changes Between Rev. 2.

Page 717

Revision HistoryB-8 Freescale SemiconductorB.7 Changes Between Rev. 2.3 and Rev. 3Table 25-19/25-32 Changed BUFnI field description from “To clear an

Page 718

Revision HistoryFreescale Semiconductor B-9Chapter 8 Remove any references to the core watchdog timer being able to reset the device. It is only able

Page 719

Revision HistoryB-10 Freescale SemiconductorSection 17.4.6/Page 17-7Add the following subsection entitled “Duplicate Frame Transmission”:The FEC fetch

Page 720

Revision HistoryFreescale Semiconductor B-11Table 26-1/Page 26-5Change description field for DTOUT1 from “DMA timer 1 output / Port TD[3]...” to “DMA

Page 721

Revision HistoryB-12 Freescale SemiconductorSection 33.13.2/Page 33-22Remove second sentence: “There is no minimum frequency requirement.”Remove secon

Page 722

Freescale Semiconductor Index-1Appendix CIndexAA/D converterbias 28-34block diagram 28-32channel decode 28-33comparator 28-33cycle times 28-32multiple

Page 723

ColdFire CoreFreescale Semiconductor 2-29ASL.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)ASR.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)BCHG Dy,<ea>

Page 724

Index-2 Freescale SemiconductorSACU 8-11Bus off interrupt (BOFFINT) 25-27BUSY 25-11BYPASS instruction 31-9CCacheblock diagram 4-2coherency 4-8fill buf

Page 725

Freescale Semiconductor Index-3reads 6-17setting CFMCLKD 6-17stop mode 6-21verify 6-18writes 6-17registersclock divider (CFMCLKD) 6-9setting 6-17comma

Page 726

Index-4 Freescale SemiconductorI2C input/output timing specifications 33-20I2C output timing between SCL and SDA 33-20JTAG and boundary scan timing 33

Page 727

Freescale Semiconductor Index-5Exceptionsaccess error 2-18divide-by-zero 2-20exception stack frame 2-17format error 2-21illegal instruction 2-19overvi

Page 728

Index-6 Freescale Semiconductorgated time accumulation 20-19registerschannel (GPTCn)20-13compare force (GPCFORC) 20-6control 1–2 (GPTCTLn) 20-9counter

Page 729

Freescale Semiconductor Index-7interruptsColdFire Flash module 6-23debug 2-21, 30-37FlexCAN 25-17overview 10-1PIT 19-7prioritization 10-4QADCoperation

Page 730

Index-8 Freescale SemiconductorColdFire Flash module 6-4, 6-7EMAC 3-3EPORT 11-3FlexCAN 25-2general purpose timers 20-4GPIO 26-7I2C 24-3interrupt contr

Page 731

Freescale Semiconductor Index-9low-power control (LPCR) 7-4low-power interrupt control (LPICR) 7-2Prescaler divide (PRESDIV) bits 25-22Processor statu

Page 732

Index-10 Freescale Semiconductormodel 22-11receive 22-11transmit 22-12registersaddress (QAR) 22-7command RAM (QCRn)22-8data (QDR) 22-8delay (QDLYR) 22

Page 733

Freescale Semiconductor Index-11error and status (ESTAT) 25-25free running timer (TIMER) 25-23interrupt flag (IFLAG) 25-28interrupt mask (IMASK) 25-27

Page 734

ColdFire Core2-30 Freescale Semiconductor2.3.5.5 Miscellaneous Instruction Execution TimesTable 2-16. Miscellaneous Instruction Execution TimesOpcode

Page 735

Index-12 Freescale Semiconductorinitialization 15-23settings 15-18timersDTIMcapture (DTCRn) 21-7counters (DTCNn)21-8event (DTERn)21-5mode (DTMRn) 21-3

Page 736 - A-24 Freescale Semiconductor

Freescale Semiconductor Index-13address multiplexing 15-9general guidelines 15-9overview 15-1registersaddress and control 1–0 (DACRn)15-6control (DCR)

Page 737

Index-14 Freescale Semiconductortest data input/development serial input (TDI/DSI) 31-3test data output/development serial output (TDO/DSO) 31-4test m

Page 738

Freescale Semiconductor Index-15set-and-forget 19-6registerscontrol and status (PCSR) 19-3count (PCNTR) 19-5modulus (PMR) 19-5timeout 19-7watchdog, se

Page 739

Index-16 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

Page 740

OverviewColdFire CoreEnhanced Multiply-Accumulate Unit (EMAC)CacheStatic RAM (SRAM)ColdFire Flash Module (CFM)Power ManagementSystem Control Module (S

Page 741

OverviewColdFire CoreEnhanced Multiply-Accumulate Unit (EMAC)CacheStatic RAM (SRAM)ColdFire Flash Module (CFM)Power ManagementSystem Control Module (S

Page 742

ColdFire CoreFreescale Semiconductor 2-312.3.5.6 EMAC Instruction Execution TimesTable 2-17. EMAC Instruction Execution TimesOpcode <EA>Effectiv

Page 743

ColdFire Core2-32 Freescale SemiconductorNOTEThe execution times for moving the contents of the Racc, Raccext[01,23], MACSR, or Rmask into a destinati

Page 744

Freescale Semiconductor 3-1Chapter 3 Enhanced Multiply-Accumulate Unit (EMAC)3.1 IntroductionThis chapter describes the functionality, microarchitect

Page 745

viii Freescale Semiconductor6.3.4.3 CFM Security Register (CFMSEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-106.3.4.4 CFM Protection Re

Page 746

Enhanced Multiply-Accumulate Unit (EMAC)3-2 Freescale SemiconductorFigure 3-1. Multiply-Accumulate Functionality Diagram3.1.1.1 Introduction to the MA

Page 747

Enhanced Multiply-Accumulate Unit (EMAC)Freescale Semiconductor 3-33.2 Memory Map/Register DefinitionThe following table and sections explain the MAC

Page 748

Enhanced Multiply-Accumulate Unit (EMAC)3-4 Freescale Semiconductor7OMCOverflow saturation mode. Enables or disables saturation mode on overflow. If s

Page 749 - Appendix C

Enhanced Multiply-Accumulate Unit (EMAC)Freescale Semiconductor 3-5Table 3-3 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.3.2.2 M

Page 750

Enhanced Multiply-Accumulate Unit (EMAC)3-6 Freescale SemiconductorThe and operator enables the MASK use and causes bit 5 of the extension word to be

Page 751

Enhanced Multiply-Accumulate Unit (EMAC)Freescale Semiconductor 3-7Figure 3-4. Accumulator Registers (ACC0–3)3.2.4 Accumulator Extension Registers (AC

Page 752

Enhanced Multiply-Accumulate Unit (EMAC)3-8 Freescale SemiconductorFigure 3-6. Accumulator Extension Register (ACCext23)3.3 Functional DescriptionThe

Page 753

Enhanced Multiply-Accumulate Unit (EMAC)Freescale Semiconductor 3-9Figure 3-7 and Figure 3-8 show relative alignment of input operands, the full 64-bi

Page 754

Enhanced Multiply-Accumulate Unit (EMAC)3-10 Freescale SemiconductorAlthough the multiplier array is implemented in a four-stage pipeline, all arithme

Page 755

Enhanced Multiply-Accumulate Unit (EMAC)Freescale Semiconductor 3-11• If R0.L is 0x8000, R0 is half-way between two 16-bit numbers. In this case, roun

Page 756

Freescale Semiconductor ix7.3.2.7 DMA Controller (DMAC0–DMA3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-77.3.2.8 UART Modules (UART

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Enhanced Multiply-Accumulate Unit (EMAC)3-12 Freescale Semiconductormovem.l (a7),#0x00ff ; restore the state from memorymove.l #0,macsr ; disable rou

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Enhanced Multiply-Accumulate Unit (EMAC)Freescale Semiconductor 3-133.3.3 EMAC Instruction Execution TimesThe instruction execution times for the EMAC

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Enhanced Multiply-Accumulate Unit (EMAC)3-14 Freescale SemiconductorAs with change or use stalls between accumulators and general-purpose registers, i

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Enhanced Multiply-Accumulate Unit (EMAC)Freescale Semiconductor 3-15• The optional 1-bit shift of the product is specified using the notation {<<

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Enhanced Multiply-Accumulate Unit (EMAC)3-16 Freescale Semiconductor/* sign-extend to 48 bits before performing any scaling */product[47:40] = {8{prod

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Enhanced Multiply-Accumulate Unit (EMAC)Freescale Semiconductor 3-17then operandX[31:0] = {Rx[31:16], 0x0000}else operandX[31:0] = {Rx[15:0], 0x0000}}

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Enhanced Multiply-Accumulate Unit (EMAC)3-18 Freescale Semiconductorthen operandX[31:0] = {0x0000, Rx[31:16]}else operandX[31:0] = {0x0000, Rx[15:0]}}

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Enhanced Multiply-Accumulate Unit (EMAC)Freescale Semiconductor 3-19result[47:0] = 0xffff_ffff_ffff}/* transfer the result to the accumulator */ACCx[4

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Enhanced Multiply-Accumulate Unit (EMAC)3-20 Freescale SemiconductorMCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

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Freescale Semiconductor 4-1 Chapter 4 Cache4.1 IntroductionThis chapter describes cache operation on the ColdFire processor.4.1.1 FeaturesFeatures in

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