Motorola MVME172 Manuel d'utilisateur

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Page 1 - Reference Guide

MVME172VME Embedded ControllerProgrammer’sReference GuideVME172A/PG2Edition of February 1999

Page 2 - Restricted Rights Legend

xMPU Status and DMA Interrupt Count Register ...2-63DMAC Status Register ...

Page 3 - Manual Terminology

2-22 Computer Group Literature Center Web SiteVMEchip22Table 2-1. VMEchip2 Memory Map - LCSR Summary (Sheet 1 of 2)DMA TBSNP MODEROMZEROSRAMSPEEDADDE

Page 4 - Recent Updates

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-232ARBROBNMASTDHBMASTDWBMSTFAIRMSTRWDMASTERVMEBUSDMAHALTDMAENDMATBLDMAFAIRDMRELMDMAVMEBUSADD

Page 5

2-24 Computer Group Literature Center Web SiteVMEchip22Table 2-1. VMEchip2 Memory Map - LCSR Summary (Sheet 2 of 2)ENIRQ31ENIRQ30ENIRQ29ENIRQ28ENIRQ2

Page 6 - Place holder

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-252This sheet begins on facing page.0123456789101112131415VMEACCESSTIMERLOCALBUSTIMERWD TIME

Page 7 - Contents

2-26 Computer Group Literature Center Web SiteVMEchip22Programming the VMEbus Slave Map DecodersThis section includes programming information for the

Page 8 - 1 ...2-29

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-272A VMEbus slave map decoder is programmed by loading the starting address of the segment i

Page 9 - 2 ...2-31

2-28 Computer Group Literature Center Web SiteVMEchip22$FFF40010. The adders allow any size board to be mapped on any 64KB boundary. The adders are di

Page 10

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-292VMEbus Slave Ending Address Register 2 This register is the ending address register for t

Page 11

2-30 Computer Group Literature Center Web SiteVMEchip22VMEbus Slave Address Translation Select Register 1 This register is the address translation sel

Page 12

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-312VMEbus Slave Address Translation Address Offset Register 2This register is the address tr

Page 13

xiInterrupt Level Register 4 (bits 24-31) ...2-94Interrupt Level Register 4 (bits 16-23) ...

Page 14

2-32 Computer Group Literature Center Web SiteVMEchip22VMEbus Slave Write Post and Snoop Control Register 2This register is the slave write post and s

Page 15

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-332VMEbus Slave Address Modifier Select Register 2This register is the address modifier sele

Page 16

2-34 Computer Group Literature Center Web SiteVMEchip22A32 When this bit is high, the second map decoder responds to VMEbus A32 (extended) access cycl

Page 17

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-352VMEbus Slave Write Post and Snoop Control Register 1This register is the slave write post

Page 18

2-36 Computer Group Literature Center Web SiteVMEchip22VMEbus Slave Address Modifier Select Register 1This register is the address modifier select reg

Page 19 - 1Board Description

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-372A32 When this bit is high, the first map decoder responds to VMEbus A32 (extended) access

Page 20

2-38 Computer Group Literature Center Web SiteVMEchip22Each of the four programmable local bus map decoders has a starting address, an ending address,

Page 21

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-392Write posting is enabled for the segment by setting the write post enable bit in the addr

Page 22 - Requirements

2-40 Computer Group Literature Center Web SiteVMEchip22Local Bus Slave (VMEbus Master) Starting Address Register 1This register is the starting addres

Page 23 - Block Diagrams

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-412Local Bus Slave (VMEbus Master) Ending Address Register 3 This register is the ending add

Page 24

xiiLocal Bus Timer... 3-8Memory Map of the MC2 Chip Regi

Page 25

2-42 Computer Group Literature Center Web SiteVMEchip22Local Bus Slave (VMEbus Master) Starting Address Register 4 This register is the starting addre

Page 26 - RESET switch control

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-432Local Bus Slave (VMEbus Master) Attribute Register 4 This register is the attribute regis

Page 27 - Memory Maps

2-44 Computer Group Literature Center Web SiteVMEchip22Local Bus Slave (VMEbus Master) Attribute Register 3 This register is the attribute register fo

Page 28

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-452Local Bus Slave (VMEbus Master) Attribute Register 2 This register is the attribute regis

Page 29

2-46 Computer Group Literature Center Web SiteVMEchip22Local Bus Slave (VMEbus Master) Attribute Register 1 This register is the attribute register fo

Page 30

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-472VMEbus Slave GCSR Group Address Register This register defines the group address of the G

Page 31

2-48 Computer Group Literature Center Web SiteVMEchip22VMEbus Slave GCSR Board Address Register This register defines the board address of the GCSR as

Page 32

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-492Local Bus to VMEbus Enable Control Register This register is the map decoder enable regis

Page 33 - (Continued)

2-50 Computer Group Literature Center Web SiteVMEchip22Local Bus to VMEbus I/O Control Register This register controls the VMEbus short I/O map and th

Page 34

http://www.mcg.mot.com/literature 2-512LCSR Programming Model2VMEchip22LCSR Programming ModelI2WP When this bit is high, write posting is enabled to t

Page 35

xiiiCHAPTER 4 IP2 ChipIntroduction...4-1S

Page 36

2-52 Computer Group Literature Center Web SiteVMEchip22Programming the VMEchip2 DMA ControllerThis section includes programming information on the DMA

Page 37

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-532Once the DMAC is enabled, the counter and control registers should not be modified by sof

Page 38

2-54 Computer Group Literature Center Web SiteVMEchip22PROM Decoder, SRAM and DMA Control Register This register controls the snoop control bits used

Page 39 - Detailed I/O Memory Maps

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-552Local Bus to VMEbus Requester Control Register This register controls the VMEbus request

Page 40

2-56 Computer Group Literature Center Web SiteVMEchip22DHB When this bit is high, the VMEbus has been acquired in response to the DWB bit being set. W

Page 41

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-572VMEbus. 3 Release when a BRx* signal is active on theVMEbus or the time on timer has expi

Page 42

2-58 Computer Group Literature Center Web SiteVMEchip22TVME This bit defines the direction in which the DMAC transfers data. When this bit is high, da

Page 43

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-592DMAC Control Register 2 (bits 0-7) This portion of the control register is loaded by the

Page 44 - 1514131211109876543210

2-60 Computer Group Literature Center Web SiteVMEchip223 The DMAC executes D64 block transfercycles on the VMEbus. In the block transfermode, the DMAC

Page 45 - RESET Switch

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-612DMAC Byte Counter In the direct mode, this counter is programmed with the number of byte

Page 46

xivIP to Local Bus Data Routing...4-52Memory Space Accesses...

Page 47

2-62 Computer Group Literature Center Web SiteVMEchip22This register controls the VMEbus interrupter. IRQL These bits define the level of the VMEbus i

Page 48 - (Continued)

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-632VMEbus Interrupter Vector Register This register controls the VMEbus interrupter vector.

Page 49

2-64 Computer Group Literature Center Web SiteVMEchip22DMAIC The DMAC interrupt counter is incremented when an interrupt is sent to the local bus inte

Page 50

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-652DLOB When this bit is set, the DMAC received a TEA and the status indicated off-board. Th

Page 51

2-66 Computer Group Literature Center Web SiteVMEchip22DMAC Ton/Toff Timers and VMEbus Global Time-out Control RegisterThis register controls the DMAC

Page 52

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-672VME Access, Local Bus, and Watchdog Time-out Control Register WDTO These bits define the

Page 53

2-68 Computer Group Literature Center Web SiteVMEchip22Prescaler Control Register The prescaler provides the various clocks required by the counters a

Page 54

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-692Tick Timer 1 Compare Register The tick timer 1 counter is compared to this register. When

Page 55

2-70 Computer Group Literature Center Web SiteVMEchip22Tick Timer 2 Compare Register The tick timer 2 counter is compared to this register. When they

Page 56

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-712Board Control Register RSWE The RESET switch enable bit is used with the “no VMEbus inter

Page 57

xvScrub Control Register...5-23Scrub Period Register Bits 15-8...

Page 58

2-72 Computer Group Literature Center Web SiteVMEchip22Watchdog Timer Control Register WDEN When this bit is high, the watchdog timer is enabled. When

Page 59 - 0Memory Maps

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-732WDCS When this bit is set high, the watchdog time-out status bit (WDTO bit in this regist

Page 60 - $FFFC1FF7 Checksum 1

2-74 Computer Group Literature Center Web SiteVMEchip22Tick Timer 1 Control Register EN When this bit is high, the counter increments. When this bit i

Page 61

http://www.mcg.mot.com/literature 2-752LCSR Programming Model2VMEchip2LCSR Programming ModelProgramming the Local Bus InterrupterThe local bus interru

Page 62

2-76 Computer Group Literature Center Web SiteVMEchip22Table 2-3. Local Bus Interrupter SummaryInterrupt VectorPriority for Simultaneous InterruptsVM

Page 63

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-772Notes 1. X = The contents of vector base register 0. 2. Y = The contents of vector base r

Page 64 - VMEbus Memory Map

2-78 Computer Group Literature Center Web SiteVMEchip22Local Bus Interrupter Status Register (bits 24-31) This register is the local bus interrupter s

Page 65

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-792Local Bus Interrupter Status Register (bits 16-23) This register is the local bus interru

Page 66 - Sources of Local BERR*

2-80 Computer Group Literature Center Web SiteVMEchip22Local Bus Interrupter Status Register (bits 8-15) This register is the local bus interrupter st

Page 67

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-812Local Bus Interrupter Status Register (bits 0-7) This register is the local bus interrupt

Page 68

xviFIGURESFigure 1-1. 200/300-Series MVME172 Block Diagram ...1-6Figure 1-2. 400/500-Series MVME172 Block Diag

Page 69

2-82 Computer Group Literature Center Web SiteVMEchip22Local Bus Interrupter Enable Register (bits 24-31) This register is the local bus interrupter e

Page 70

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-832Local Bus Interrupter Enable Register (bits 16-23) This register is the local bus interru

Page 71

2-84 Computer Group Literature Center Web SiteVMEchip22Local Bus Interrupter Enable Register (bits 8-15) This is the local bus interrupter enable regi

Page 72

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-852Local Bus Interrupter Enable Register (bits 0-7) This is the local bus interrupter enable

Page 73

2-86 Computer Group Literature Center Web SiteVMEchip22Software Interrupt Set Register (bits 8-15) This register is used to set the software interrupt

Page 74

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-872CVI1E Clear VMEbus IRQ1 edge-sensitive interrupt. CPE Not used on MVME172. CMWP Clear VME

Page 75

2-88 Computer Group Literature Center Web SiteVMEchip22Interrupt Clear Register (bits 8-15) This register is used to clear the edge software interrupt

Page 76

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-892Interrupt Level Register 1 (bits 16-23) This register is used to define the level of the

Page 77

2-90 Computer Group Literature Center Web SiteVMEchip22Interrupt Level Register 1 (bits 0-7) This register is used to define the level of the tick tim

Page 78

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-912Interrupt Level Register 2 (bits 16-23) This register is used to define the level of the

Page 79

xviiTable 5-1. MCECC Specifications...5-3Table 5-2. MCECC Internal Register

Page 80

2-92 Computer Group Literature Center Web SiteVMEchip22Interrupt Level Register 2 (bits 0-7) This register is used to define the level of the GCSR LM0

Page 81

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-932Interrupt Level Register 3 (bits 16-23) This register is used to define the level of the

Page 82 - Functional Blocks

2-94 Computer Group Literature Center Web SiteVMEchip22Interrupt Level Register 3 (bits 0-7) This register is used to define the level of the software

Page 83

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-952Interrupt Level Register 4 (bits 16-23) This register is used to define the level of the

Page 84

2-96 Computer Group Literature Center Web SiteVMEchip22Interrupt Level Register 4 (bits 0-7) This register is used to define the level of the VMEbus I

Page 85

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-972I/O Control Register 1 This register is a general purpose I/O control register. Bits 16-1

Page 86

2-98 Computer Group Literature Center Web SiteVMEchip22I/O Control Register 2 GPIOO1 Connects to pin 16 of the Remote Status and Control Register.GPIO

Page 87 - VMEbus to Local Bus Interface

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-992Miscellaneous Control Register DISBGN When this bit is high, the VMEbus BGIN filters are

Page 88

2-100 Computer Group Literature Center Web SiteVMEchip22from the retry and the board does not lose its turn on the VMEbus. For this reason, it is reco

Page 89

GCSR Programming Modelhttp://www.mcg.mot.com/literature 2-1012GCSR Programming ModelThis section describes the programming model for the Global Contro

Page 90

xviii

Page 91

2-102 Computer Group Literature Center Web SiteVMEchip22The location monitor status register provides the status of the location monitors. A location

Page 92 - Tick and Watchdog Timers

GCSR Programming Modelhttp://www.mcg.mot.com/literature 2-1032Programming the GCSRA complete description of the GCSR is provided in the following tabl

Page 93

2-104 Computer Group Literature Center Web SiteVMEchip22Table 2-4 shows a summary of the GCSR. Table 2-4. VMEchip2 Memory Map (GCSR Summary)VMEchip2

Page 94 - VMEbus Interrupter

GCSR Programming Modelhttp://www.mcg.mot.com/literature 2-1052VMEchip2 Revision Register This register is the VMEchip2 revision register. The revision

Page 95 - VMEbus System Controller

2-106 Computer Group Literature Center Web SiteVMEchip22SIG0 The SIG0 bit is set when a VMEbus master writes a one to it. When the SIG0 bit is set, an

Page 96

GCSR Programming Modelhttp://www.mcg.mot.com/literature 2-1072LM3 This bit is cleared by an LM3 cycle on the VMEbus. This bit is set when the local pr

Page 97

2-108 Computer Group Literature Center Web SiteVMEchip22General Purpose Register 0 This register is a general purpose register that allows a local bus

Page 98

GCSR Programming Modelhttp://www.mcg.mot.com/literature 2-1092General Purpose Register 2 This register is a general purpose register that allows a loc

Page 99

2-110 Computer Group Literature Center Web SiteVMEchip22General Purpose Register 4 This register is a general purpose register that allows a local bus

Page 100 - VMEchip2

3-133MC2 ChipIntroductionThe Memory Controller ASIC (MC2 chip) is one of three ASICs that are part of the MVME172 hardware set. Summary of Major Featu

Page 101 - LCSR Programming Model

1-111Board Descriptionand Memory MapsIntroductionThis manual provides programming information for the MVME172 Embedded Controller. Extensive programmi

Page 102

3-2 Computer Group Literature Center Web SiteMC2 Chip3Functional DescriptionThe following sections provide an overview of the functions provided by th

Page 103

Functional Descriptionhttp://www.mcg.mot.com/literature 3-33BBRAM InterfaceThe MC2 chip provides a read/write interface to the BBRAM by any bus master

Page 104

3-4 Computer Group Literature Center Web SiteMC2 Chip3MPU Channel Attention access is used to cause the 82596CA to begin executing memory resident Com

Page 105

Functional Descriptionhttp://www.mcg.mot.com/literature 3-53LANC InterruptThe MC2 chip provides an interrupt control register for normal LANC terminat

Page 106

3-6 Computer Group Literature Center Web SiteMC2 Chip3Note TEA is the MC68060 bus error transaction signal. “With TEA” indicates that a bus error cycl

Page 107 - OPER R/W

Functional Descriptionhttp://www.mcg.mot.com/literature 3-73addresses for the devices are defined as follows. Note that CSR bits were added to the Gen

Page 108

3-8 Computer Group Literature Center Web SiteMC2 Chip3Watchdog TimerA watchdog timer function is provided in the VMEchip2 and the MC2 chip. The watchd

Page 109

Memory Map of the MC2 Chip Registershttp://www.mcg.mot.com/literature 3-93MC2 chip Base Address = $FFF42000.Table 3-2. MC2 Chip Register MapOffset D3

Page 110

3-10 Computer Group Literature Center Web SiteMC2 Chip3Programming ModelThis section defines the programming model for the control and status register

Page 111

Programming Modelhttp://www.mcg.mot.com/literature 3-113MC2 Chip ID RegisterID7-ID0 The chip ID number is $84. This register is read only. It ignores

Page 112

NoticeWhile reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omission

Page 113

1-2 Computer Group Literature Center Web SiteBoard Description and Memory Maps1The I/O connection for the 400/500-Series serial ports is provided by t

Page 114

3-12 Computer Group Literature Center Web SiteMC2 Chip3General Control Register FAST This control bit tailors the control circuit for BBRAM to the sp

Page 115

Programming Modelhttp://www.mcg.mot.com/literature 3-133SCCIT<1:0>These bits define the IACK daisy chain time for the SCC chips. They must be se

Page 116

3-14 Computer Group Literature Center Web SiteMC2 Chip3The encoding for the interrupt sources is shown in the next table, where IV3-IV0 refer to bits

Page 117

Programming Modelhttp://www.mcg.mot.com/literature 3-153Programming the Tick Timers There are four programmable tick timers in the MC2 chip. These tim

Page 118

3-16 Computer Group Literature Center Web SiteMC2 Chip3Tick Timer 1 Compare RegisterTick Timer 1 CounterTick Timer 2 Compare RegisterADR/SIZ $FFF42004

Page 119

Programming Modelhttp://www.mcg.mot.com/literature 3-173Tick Timer 2 Counter LSB Prescaler Count RegisterThis register is used to generate the 1 MHz

Page 120

3-18 Computer Group Literature Center Web SiteMC2 Chip3Prescaler Clock Adjust RegisterThis register adjusts the prescaler so that it maintains a 1 MHz

Page 121

Programming Modelhttp://www.mcg.mot.com/literature 3-193Tick Timer 2 Control Register Tick Timer 1 Control RegisterCEN When this bit is high, the cou

Page 122

3-20 Computer Group Literature Center Web SiteMC2 Chip3Tick Timer Interrupt Control RegistersThere are four tick timer interrupt control registers. Th

Page 123

Programming Modelhttp://www.mcg.mot.com/literature 3-213Tick Timer 1 Interrupt Control Register IL2-IL0 These three bits select the interrupt level fo

Page 124

Overviewhttp://www.mcg.mot.com/literature 1-31The MCECC chip Memory Controller ASIC on the 200/300-Series MVME172 provides the programmable interface

Page 125

3-22 Computer Group Literature Center Web SiteMC2 Chip3DRAM Parity Error Interrupt Control RegisterThe DRAM Parity Error Interrupt Control Register co

Page 126

Programming Modelhttp://www.mcg.mot.com/literature 3-233SCC Interrupt Control RegisterIL2-IL0 These three bits select the interrupt level for the SCC

Page 127

3-24 Computer Group Literature Center Web SiteMC2 Chip3Tick Timer 3 and 4 Control RegistersTick Timer 4 Control Register Tick Timer 3 Control Register

Page 128

Programming Modelhttp://www.mcg.mot.com/literature 3-253DRAM and SRAM Memory Controller RegistersThe DRAM decode logic consists of a base register, a

Page 129

3-26 Computer Group Literature Center Web SiteMC2 Chip3SRAM Space Base Address RegisterB31-B17 B31 - B17 are compared to local bus address signals A31

Page 130

Programming Modelhttp://www.mcg.mot.com/literature 3-273DRAM/SRAM Options RegisterNote that this register is read only and is initialized at reset.DZ2

Page 131

3-28 Computer Group Literature Center Web SiteMC2 Chip3SZ1 - SZ0 are initialized at reset to a value which is determined by the contents of a factory-

Page 132 - WAIT RMW

Programming Modelhttp://www.mcg.mot.com/literature 3-293SRAM Space Size RegisterSEN SRAM ENABLE must be set to a one before the SRAM can be accessed.S

Page 133 - LVFAIR LVRW

3-30 Computer Group Literature Center Web SiteMC2 Chip3LANC Error Status RegisterSCLR Writing a 1 to this bit clears bits LTO, EXT, and PRTY. Reading

Page 134

Programming Modelhttp://www.mcg.mot.com/literature 3-31382596CA LANC Interrupt Control RegisterIL2-IL0 Interrupt Request Level. These three bits selec

Page 135

1-4 Computer Group Literature Center Web SiteBoard Description and Memory Maps1RequirementsThese boards are designed to conform to the requirements of

Page 136

3-32 Computer Group Literature Center Web SiteMC2 Chip3LANC Bus Error Interrupt Control RegisterIL2-IL0 Interrupt Request Level. These three bits sele

Page 137

Programming Modelhttp://www.mcg.mot.com/literature 3-333SCSI Error Status RegisterSCLR Writing a 1 to this bit clears bits LTO, EXT, and PRTY. Reading

Page 138

3-34 Computer Group Literature Center Web SiteMC2 Chip3 V10-V8 V10 - V8 are general purpose inputs which are connected to three jumpers on the MVME172

Page 139

Programming Modelhttp://www.mcg.mot.com/literature 3-353MVME172 Version RegisterThe contents of a PAL and the state of an 8-position jumper block are

Page 140

3-36 Computer Group Literature Center Web SiteMC2 Chip3V3 V3 set to a one indicates that the Ethernet interface is not present. V3 set to a zero indic

Page 141

Programming Modelhttp://www.mcg.mot.com/literature 3-373Tick Timer 3 and 4 Compare and Counter RegistersTick timers three and four are defined here be

Page 142

3-38 Computer Group Literature Center Web SiteMC2 Chip3Tick Timer 4 Compare Register Tick Timer 4 Counter Bus Clock RegisterThe Bus Clock Register sh

Page 143

Programming Modelhttp://www.mcg.mot.com/literature 3-393BCK5-BCK0 The refresh rate is defined by the following equation:Refresh Rate = BCK/BUS CLOCK *

Page 144

3-40 Computer Group Literature Center Web SiteMC2 Chip3ROM0 Refer to the table on the Local Bus Memory Map, Note 1, in Chapter 1.Flash Access Time Con

Page 145

Programming Modelhttp://www.mcg.mot.com/literature 3-413ABORT Switch Interrupt Control RegisterThe following table describes the ABORT switch interrup

Page 146

Block Diagramshttp://www.mcg.mot.com/literature 1-51Block DiagramsFigure 1-2 on page 1-7 is a general block diagram of the 200/300-Series MVME172. Fig

Page 147

3-42 Computer Group Literature Center Web SiteMC2 Chip3RESET Switch Control RegisterThe RESET switch on the MVME172 front panel and several status and

Page 148

Programming Modelhttp://www.mcg.mot.com/literature 3-433Watchdog Timer Control RegisterThe watchdog timer control logic in the MC2 chip is used with t

Page 149 - RESET switch is disabled

3-44 Computer Group Literature Center Web SiteMC2 Chip3Access and Watchdog Time Base Select RegisterThe watchdog timer control logic in the MC2 chip i

Page 150 - WDBFE WDS/L WDRSE

Programming Modelhttp://www.mcg.mot.com/literature 3-453signal is sent to the local bus. Note that the Version Register bit V1 must be set to a 1 to e

Page 151

3-46 Computer Group Literature Center Web SiteMC2 Chip3PAREN-PARINTNONE means no parity checking. Parity errors are not detected or reported. INTERRUP

Page 152

Programming Modelhttp://www.mcg.mot.com/literature 3-473MLTO When this bit is set, the MPU received a TEA and the status indicated a local bus time-ou

Page 153 - 2VMEchip2

3-48 Computer Group Literature Center Web SiteMC2 Chip332-bit Prescaler Count RegisterThe prescaler register is used to clock timing functions in the

Page 154

4-144IP2 ChipIntroductionThis chapter describes the IndustryPack Interface Controller (IP2 chip) ASIC for the MC68060 bus. The IP2 chip interfaces to

Page 155

4-2 Computer Group Literature Center Web SiteIP2 Chip4Functional DescriptionThe following sections provide an overview of the functions provided by th

Page 156

Functional Descriptionhttp://www.mcg.mot.com/literature 4-34Local Bus to IndustryPack DMA ControllersThe IP2 supports two basic types of DMA cycles: “

Page 157

1-6 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Figure 1-1. 200/300-Series MVME172 Block DiagramVMEchip2VMEbusInterfac

Page 158

4-4 Computer Group Literature Center Web SiteIP2 Chip4addresses are not aligned, so the local bus and the IndustryPack can operate at their maximum da

Page 159

Functional Descriptionhttp://www.mcg.mot.com/literature 4-54Clocking Environments and PerformanceThe IP2 chip has two clock domains. The majority of t

Page 160

4-6 Computer Group Literature Center Web SiteIP2 Chip4Notes 1. This column is a measure of IndustryPack bandwidth for back to back cycles for a local

Page 161

Functional Descriptionhttp://www.mcg.mot.com/literature 4-74Programmable ClockThe IP2 chip implements a general purpose programmable clock output for

Page 162

4-8 Computer Group Literature Center Web SiteIP2 Chip4indicates that a local bus error did occur as a consequence of a DMA operation. The contents of

Page 163

Overall Memory Maphttp://www.mcg.mot.com/literature 4-94Overall Memory MapThe following memory map table includes all devices selected by the IP2 chip

Page 164

4-10 Computer Group Literature Center Web SiteIP2 Chip4Programming ModelThis section defines the programming model for the control and status register

Page 165

Programming Modelhttp://www.mcg.mot.com/literature 4-114Table 4-3. IP2 Chip Memory Map - Control and Status RegistersIP2 Chip Base Address = $FFFBC00

Page 166

4-12 Computer Group Literature Center Web SiteIP2 Chip4$19 IP_b GENERAL CONTROLb_ERR 0 b_RT1 b_RT0 b_WIDTH1 b_WIDTH0 b_BTD b_MEN$1A IP_c GENERAL CONTR

Page 167

Programming Modelhttp://www.mcg.mot.com/literature 4-134DMAC for IndustryPack a, request 0. This register set is referred to as DMACa in the text.$20

Page 168

Functional Descriptionhttp://www.mcg.mot.com/literature 1-71Figure 1-2. 400/500-Series MVME172 Block DiagramVMEchip2VMEbusInterfaceIP2IndustryPackInt

Page 169

4-14 Computer Group Literature Center Web SiteIP2 Chip4DMAC for IndustryPack b, request 0 or for IndustryPack a, request 1. This register set is refer

Page 170

Programming Modelhttp://www.mcg.mot.com/literature 4-154DMAC for IndustryPack c, request 0. This register set is referred to as DMACc in the text.$50

Page 171

4-16 Computer Group Literature Center Web SiteIP2 Chip4DMAC for IndustryPack d, request 0 or for IndustryPack c, request 1, and for programmable CLOCK

Page 172

Programming Modelhttp://www.mcg.mot.com/literature 4-174Chip ID RegisterThe read-only Chip ID Register is hard-wired to a hexadecimal value of $23. Wr

Page 173

4-18 Computer Group Literature Center Web SiteIP2 Chip4Vector Base RegisterThe interrupt Vector Base Register is an 8-bit read/write register that is

Page 174

Programming Modelhttp://www.mcg.mot.com/literature 4-194A normal read access to the Vector Base Register yields the value $0F if the read happens befo

Page 175 - GPOEN3 GPOEN2 GPOEN1 GPOEN0

4-20 Computer Group Literature Center Web SiteIP2 Chip4Note Note that the Memory Bases for any of IP_a, IP_b, IP_c, IP_d, that are enabled, should not

Page 176 - GPIOO3 GPIOO2 GPIOO1 GPIOO0

Programming Modelhttp://www.mcg.mot.com/literature 4-214IP_c or Double Size IP_cd Memory Base Address Registers (Not used on 200/300-Series MVME172.)I

Page 177

4-22 Computer Group Literature Center Web SiteIP2 Chip4SIZE23-16 A, B, C, D SIZE should be programmed to match the size of the corresponding IndustryP

Page 178

Programming Modelhttp://www.mcg.mot.com/literature 4-234IP_a, IP_b, IP_c, and IP_d; IRQ0 and IRQ1 Interrupt Control RegistersThe registers which contr

Page 179 - GCSR Programming Model

1-8 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Notes 1. RESET switch control.2. Watchdog timer control.3. Access and w

Page 180

4-24 Computer Group Literature Center Web SiteIP2 Chip4PLTY When this bit is low, interrupt is activated by a falling edge/low level of the IndustryPa

Page 181 - Programming the GCSR

Programming Modelhttp://www.mcg.mot.com/literature 4-254BTD Setting BTD (bus turn around delay) to a one will insert one inactive clock period followi

Page 182 - Bit Numbers

4-26 Computer Group Literature Center Web SiteIP2 Chip4Note When programming b_WIDTH1-b_WIDTH0 for either 8-bits or 16-bits, a_WIDTH1-a_WIDTH0 must b

Page 183

Programming Modelhttp://www.mcg.mot.com/literature 4-274back I/O and/or ID accesses are ensured if a single size access is followed by a single size a

Page 184

4-28 Computer Group Literature Center Web SiteIP2 Chip4IP Clock RegisterIP32 Setting IP32 to a one enables the IndustryPack bus to operate synchronous

Page 185

Programming Modelhttp://www.mcg.mot.com/literature 4-294DMA Arbitration Control RegisterThe DMA arbitration control register contents determine whethe

Page 186

4-30 Computer Group Literature Center Web SiteIP2 Chip4IP RESET Register RES Setting RES to a one asserts the IP2 chip IPRESET* signal. IPRESET* is in

Page 187

Programming Modelhttp://www.mcg.mot.com/literature 4-314Programming the DMA ControllersThe IP2 chip implements four DMA channels. They can operate in

Page 188

4-32 Computer Group Literature Center Web SiteIP2 Chip4Each DMAC’s control is divided into two registers. The first register is only accessible by the

Page 189 - 3MC2 Chip

Programming Modelhttp://www.mcg.mot.com/literature 4-334DMA Enable FunctionThere are certain DMA channel contexts which are illegal. If an attempt is

Page 190 - Functional Description

Memory Mapshttp://www.mcg.mot.com/literature 1-91VMEbus Interface and VMEchip2The local bus to VMEbus interface and the VMEbus to local bus interface

Page 191 - 82596CA LAN Interface

4-34 Computer Group Literature Center Web SiteIP2 Chip4DMA Status RegisterDONE This bit is set when DMAC has finished executing commands and there wer

Page 192 - MC2 Chip

Programming Modelhttp://www.mcg.mot.com/literature 4-354IPEND When this bit is set, the DMA process was terminated if the DMAEND signal was asserted b

Page 193 - SRAM Memory Controller

4-36 Computer Group Literature Center Web SiteIP2 Chip4DEN Setting the DEN bit to a one will enable the DMA function. Software should not write to the

Page 194 - Z85230 SCC Interface

Programming Modelhttp://www.mcg.mot.com/literature 4-374DMA Control Register 1The registers which control IP_c and IP_d are not used on the 200/300-Se

Page 195 - Tick Timers

4-38 Computer Group Literature Center Web SiteIP2 Chip4bits in the General Control Registers, these width control bits define the width of both the me

Page 196 - Local Bus Timer

Programming Modelhttp://www.mcg.mot.com/literature 4-394DMA Control Register 2This register is loaded by the processor or by DMA when it loads the com

Page 197 - D31-D24 D23-D16 D15-D8 D7-D0

4-40 Computer Group Literature Center Web SiteIP2 Chip4DMAEI When DMAEI is set, DMA terminates if the assertion of DMAEND is detected and the sDMA fun

Page 198 - Programming Model

Programming Modelhttp://www.mcg.mot.com/literature 4-414DMA IndustryPack Address CounterIn the direct mode, this counter is programmed with the starti

Page 199 - MC2 Chip Revision Register

4-42 Computer Group Literature Center Web SiteIP2 Chip4The registers which control IP_c and IP_d are not used on the 200/300-Series MVME172. DMA Table

Page 200 - General Control Register

Programming Modelhttp://www.mcg.mot.com/literature 4-434Programming the Programmable ClockProgrammable clock registers are defined in the following pa

Page 201

1-10 Computer Group Literature Center Web SiteBoard Description and Memory Maps1map from $00000000 to $FFFFFFFF. Many areas of the map are user-progra

Page 202

4-44 Computer Group Literature Center Web SiteIP2 Chip4Programmable Clock General Control RegisterPS2-0 These three bits select the frequency of the p

Page 203 - Programming the Tick Timers

Programming Modelhttp://www.mcg.mot.com/literature 4-454enabling/disabling the pre-scaler’s counter. Note that clearing EN does not clear any of the p

Page 204 - Tick Timer 2 Compare Register

4-46 Computer Group Literature Center Web SiteIP2 Chip4Local Bus to IndustryPack AddressingThe following sections provide examples that illustrate loc

Page 205 - LSB Prescaler Count Register

Local Bus to IndustryPack Addressinghttp://www.mcg.mot.com/literature 4-47416-Bit Memory SpaceThis example is for IP_a, where the IP_a memory space is

Page 206

4-48 Computer Group Literature Center Web SiteIP2 Chip432-Bit Memory SpaceThis example is for IP_ab, where the IP_ab memory space is programmed with a

Page 207

Local Bus to IndustryPack Addressinghttp://www.mcg.mot.com/literature 4-494IP_a I/O SpaceThis example is for IP_a I/O space. The relationship of the I

Page 208

4-50 Computer Group Literature Center Web SiteIP2 Chip4IP_ab I/O SpaceThis example is for 32-bit, IP_ab I/O space. The relationship of the IndustryPac

Page 209

Local Bus to IndustryPack Addressinghttp://www.mcg.mot.com/literature 4-514IP_a ID SpaceThis example is for IP_a ID space. The relationship of the Ind

Page 210

4-52 Computer Group Literature Center Web SiteIP2 Chip4IP to Local Bus Data RoutingThis section shows data routing from an IP to the local bus. Memory

Page 211

IP to Local Bus Data Routinghttp://www.mcg.mot.com/literature 4-534 IPWIDTH LBSIZE LBA IPA LD<31-24> LD<23-16> LD<15-8> LD<7-0>

Page 212

Memory Mapshttp://www.mcg.mot.com/literature 1-111Notes 1. Devices mapped at $FFF80000-$FFF9FFFF also appear at $00000000- $001FFFFF when the ROM0 bit

Page 213

4-54 Computer Group Literature Center Web SiteIP2 Chip4I/O and ID Space AccessesThe following table shows the data routing when accessing IP I/O or ID

Page 214

5-155MCECCIntroductionThis chapter describes the ECC DRAM Controller ASIC (MCECC) used on the memory mezzanine boards with ECC protection. The MCECC i

Page 215

5-2 Computer Group Literature Center Web SiteMCECC5Functional DescriptionThe following sections provide an overview of the functions provided by the M

Page 216

Functional Descriptionhttp://www.mcg.mot.com/literature 5-35Random, non-burst writes are the slowest kind of access because they require that the MCEC

Page 217

5-4 Computer Group Literature Center Web SiteMCECC5When (SC1, SC0) do not indicate that snooping is inhibited, the MCECC pair responds differently to

Page 218 - LANC Error Status Register

Functional Descriptionhttp://www.mcg.mot.com/literature 5-55pair writes all 144 bits. When the local bus master requests a byte, word (two-byte), or l

Page 219

5-6 Computer Group Literature Center Web SiteMCECC5Triple (or Greater) Bit Error (Cycle Type = Burst Read or Non-Burst Read)Some of these errors are d

Page 220

Functional Descriptionhttp://www.mcg.mot.com/literature 5-75Notify the local MPU via interrupt if so enabled. Double Bit Error (Cycle Type = Scrub)Do

Page 221 - SCSI Error Status Register

5-8 Computer Group Literature Center Web SiteMCECC5occurs, the local bus master is notified if such interrupts are enabled in the control register. A

Page 222

Programming Modelhttp://www.mcg.mot.com/literature 5-95stream". The reset serial bit stream initializes the MCECC pair by setting or resetting th

Page 223 - MVME172 Version Register

PrefaceThis manual provides board level information and detailed ASIC chip information including register bit descriptions for the MVME172 Embedded Co

Page 224

1-12 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Notes 1. Reset enables the decoder for this space of the memory map so

Page 225 - Tick Timer 3 Counter

5-10 Computer Group Literature Center Web SiteMCECC5The possible states of the bits after local, software, and power-up reset are as defined below. P

Page 226 - Bus Clock Register

Programming Modelhttp://www.mcg.mot.com/literature 5-115A summary of the remaining CSR registers is shown in Table 5-3, following. As with the first e

Page 227

5-12 Computer Group Literature Center Web SiteMCECC5Table 5-3. MCECC Internal Register Memory Map, Part 2MCECC Base Address = $FFF43000 (1st); $FFF43

Page 228

Programming Modelhttp://www.mcg.mot.com/literature 5-135Register OffsetRegister NameRegister Bit Names D31 D30 D29 D28 D27 D26 D25 D24$54 SCRUB ADDR C

Page 229

5-14 Computer Group Literature Center Web SiteMCECC5Chip ID RegisterThe Chip ID Register is hard-wired to a hexadecimal value of $81. The MCECC can be

Page 230 - RESET Switch Control Register

Programming Modelhttp://www.mcg.mot.com/literature 5-155Memory Configuration RegisterMSIZ2-MSIZ0MSIZ2-MSIZ0 together define the size of the total memo

Page 231

5-16 Computer Group Literature Center Web SiteMCECC5RB3 Read Bit 3 is a read only bit that is always 0.Difference from MEMC040: bit = WPB (write-per-

Page 232

Programming Modelhttp://www.mcg.mot.com/literature 5-175Dummy Register 1Dummy Register 1 is hard-wired to all zeros. Writes to this register are ignor

Page 233 - DRAM Control Register

5-18 Computer Group Literature Center Web SiteMCECC5DRAM Control RegisterThe bit assignments for the DRAM Control Register are:RAMEN RAM Enable. This

Page 234 - MPU Status Register

Programming Modelhttp://www.mcg.mot.com/literature 5-195Difference from MEMC040: bit = WWP (write-wrong-parity) for MEMC040; bit = RWB (general purpo

Page 235

Memory Mapshttp://www.mcg.mot.com/literature 1-131Register at address $FFF42048, bit 24. PROM/Flash is disabled at the low address space with PROM Con

Page 236

5-20 Computer Group Literature Center Web SiteMCECC5Difference from MEMC040: bit = DMCTL (data-mux-control) for MEMC040; bit = RWB (general purpose r

Page 237 - 4IP2 Chip

Programming Modelhttp://www.mcg.mot.com/literature 5-215Note None of the remaining registers have counterparts in the MEMC040 because they are associ

Page 238

5-22 Computer Group Literature Center Web SiteMCECC51. Stop all scrub operations by clearing all of the STON bits and setting all of the STOFF bits in

Page 239

Programming Modelhttp://www.mcg.mot.com/literature 5-235Scrub Control RegisterIDIS When cleared, the Image DISable bit allows writes to the upper MCEC

Page 240 - IP2 Chip

5-24 Computer Group Literature Center Web SiteMCECC5HITDIS This bit controls a function that is not currently used in the MCECC. RADATA This bit contr

Page 241

Programming Modelhttp://www.mcg.mot.com/literature 5-255Chip Prescaler CounterThis register reflects the current value in the prescaler counter. The P

Page 242

5-26 Computer Group Literature Center Web SiteMCECC5STON2-STON0STON2-STON0 control the amount of time that the scrubber occupies the DRAM before provi

Page 243 - Error Reporting

Programming Modelhttp://www.mcg.mot.com/literature 5-275Note that if STON2-0 is zero, the scrubber always releases the DRAM after one memory cycle, ev

Page 244 - Interrupts

5-28 Computer Group Literature Center Web SiteMCECC5Scrub Prescaler Counter (Bits 15-8)This register reflects the current value in the scrub prescaler

Page 245 - Overall Memory Map

Programming Modelhttp://www.mcg.mot.com/literature 5-295Scrub Timer Counter (Bits 7-0)This register reflects the current value in the Scrub Timer Coun

Page 246

1-14 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Table 1-5 below and Table 1-6 on page 1-18 describe the "Local I/

Page 247

5-30 Computer Group Literature Center Web SiteMCECC5Scrub Address Counter (Bits 23-16)This register reflects the current value in the Scrub Address Co

Page 248

Programming Modelhttp://www.mcg.mot.com/literature 5-315Scrub Address Counter (Bits 7-4)This register reflects the current value in the Scrub Address

Page 249

5-32 Computer Group Literature Center Web SiteMCECC5EALT EALT indicates that the last logging of an error occurred on a DRAM access by an alternate (M

Page 250

Programming Modelhttp://www.mcg.mot.com/literature 5-335Error Address (Bits 23-16)This register reflects the value that was on bits 23-16 of the local

Page 251

5-34 Computer Group Literature Center Web SiteMCECC5Error Syndrome RegisterS7-S0 SYNDROME7-0 reflects the syndrome value at the last logging of an err

Page 252

Programming Modelhttp://www.mcg.mot.com/literature 5-355The states of RSIZ2-0 after power-up, soft, or local reset, match those of the RSIZ2-0 bits fr

Page 253 - Chip Revision Register

5-36 Computer Group Literature Center Web SiteMCECC5clock, unless they are already slowed by NCEBEN being set. FSTRD is cleared by Power-up or Local R

Page 254 - Vector Base Register

Programming Modelhttp://www.mcg.mot.com/literature 5-375initialized by power-up, soft, or local reset to match the NOCACHE bit in the reset serial bit

Page 255

5-38 Computer Group Literature Center Web SiteMCECC5operating at 25 MHz. This sequence may have to be altered to perform the scrub more slowly if the

Page 256

Syndrome Decodehttp://www.mcg.mot.com/literature 5-395Syndrome DecodeA syndrome code value of $00 indicates no error found. All other syndrome code va

Page 257 - NAME($0B)

Memory Mapshttp://www.mcg.mot.com/literature 1-151$FFF58280 - $FFF582FF IP2 IP_c ID D16 128B 7$FFF58300 - $FFF5837F IP2 IP_d I/O D16 128B 7$FFF58380 -

Page 258 - NAME($0F)

5-40 Computer Group Literature Center Web SiteMCECC5Bank in Error Bit in Error Syndrome CodeBANK C BIT 0/16 $23BANK C BIT 1/17 $43BANK C BIT 2/18 $83B

Page 259 - Registers

Syndrome Decodehttp://www.mcg.mot.com/literature 5-415Bank in Error Bit in Error Syndrome CodeBANK A BIT 0/16 $32BANK A BIT 1/17 $34BANK A BIT 2/18 $3

Page 260 - NAME($1B)

5-42 Computer Group Literature Center Web SiteMCECC5

Page 261

AA-1ARelated DocumentationMotorola Computer Group DocumentsThe Motorola publications listed below are applicable to the MVME172. To obtain paper or el

Page 262

A-2Related DocumentationALiterature UpdatesOnline product information, including manuals, is updated as necessary. Please consult the MCG literature

Page 263

Manufacturers’ DocumentsA-3A82596CA Local Area Network Coprocessor data sheet82596 User’s ManualIntel Corporation, Literature Sales, P.O. Box 58130, S

Page 264 - IP Clock Register

A-4Related DocumentationA

Page 265

BB-1BUsing Interrupts onthe MVME172IntroductionThis appendix demonstrates how to use interrupts on the MVME172. It gives an example of how to generate

Page 266 - IP RESET Register

VMEchip2 Tick Timer 1 Periodic Interrupt ExampleB-2 Computer Group Literature Center Web SiteB2. Set up local bus interrupter:Periodic Tick Timer 1 in

Page 267

Using Interrupts on the MVME172http://www.mcg.mot.com/literature B-3B3. Set up an interrupt handler routine:Step Action and ReferenceYour interrupt ha

Page 268

1-16 Computer Group Literature Center Web SiteBoard Description and Memory Maps1$FFFBC800 - $FFFBC81F Reserved - - 2KB 1$FFFBD000 - $FFFBFFFF Reserved

Page 269

VMEchip2 Tick Timer 1 Periodic Interrupt ExampleB-4 Computer Group Literature Center Web SiteB

Page 270 - IPEND CHANI

IN-1IndexNumerics32-bit Prescaler Count Register 3-4853C710 SCSI controller interface 3-582596CA LAN interface 3-382596CA LANC Interrupt Control Regis

Page 271

IndexIN-2 Computer Group Literature Center Web SiteINDEXblock diagram200/300-Series 1-6400/500-Series 1-7VMEchip2 2-5block diagrams 1-5block transferc

Page 272 - OPER RRRRRRRS

http://www.mcg.mot.com/literature IN-3INDEXDMA continuedInterrupt Control Register, IP2 chip 4-35Local Bus Address Counter, IP2 chip4-40Status Registe

Page 273 - WIDTH1 WIDTH0

IndexIN-4 Computer Group Literature Center Web SiteINDEXIP ID space 4-51setting up interrupt handler routine B-2setting up local bus interrupter B-2us

Page 274

http://www.mcg.mot.com/literature IN-5INDEXIndustryPackaddressing 4-46error reporting 4-8ID 1-45Iinterface 4-1Interface Controller ASIC (IP2 chip)4-1,

Page 275 - DMAEI DMAEO

IndexIN-6 Computer Group Literature Center Web SiteINDEXlocal busaccesses 1-47address counter, DMAC 2-60address range 2-39base address, GCSR 2-101inte

Page 276

http://www.mcg.mot.com/literature IN-7INDEXMC2 chip/VMEchip2 redundancies 1-5MC68060bus master support for 82596CA 3-4indivisible cycles 1-58indivisib

Page 277

IndexIN-8 Computer Group Literature Center Web SiteINDEXperiodic interrupt example B-1power monitor 2-17powerup resetVMEchip2 2-71Prescaler Clock Adju

Page 278

http://www.mcg.mot.com/literature IN-9INDEXScrub Prescaler Counter(Bits 15-8) 5-28(Bits 21-16) 5-27(Bits 7-0) 5-28Scrub Time On/Time Off Register 5-25

Page 279

Memory Mapshttp://www.mcg.mot.com/literature 1-171Notes 1. For a complete description of the register bits, refer to the data sheet for the specific c

Page 280

IndexIN-10 Computer Group Literature Center Web SiteINDEXtick timerinterrupters 2-19periodic interrupt example B-1Tick Timer 1 and 2Compare and Counte

Page 281

http://www.mcg.mot.com/literature IN-11INDEXVMEbus requester, DMAC 2-13VMEbus slave 2-9VMEbus SlaveAddress Modifier Select Register 1 2-36Address Modi

Page 282 - 8-Bit Memory Space

IndexIN-12 Computer Group Literature Center Web SiteINDEX

Page 283 - 16-Bit Memory Space

®™®™®™®™MVME172 Programmer’s Reference GuideMVME172Embedded ControllerProgrammer’sReference Guide34 pages1/8” spine36 - 84 pages3/16” & 1/4” spine

Page 285 - IP_a I/O Space

1-18 Computer Group Literature Center Web SiteBoard Description and Memory Maps1 Table 1-6. 400/500-Series MVME172 Local I/O Devices Memory MapAddres

Page 286 - IP_ab I/O Space

Memory Mapshttp://www.mcg.mot.com/literature 1-191$FFF58980 - $FFF589FF Reserved -- 128B 1$FFF58A00 - $FFF58A7F Reserved -- 128B 1$FFF58A80 - $FFF58AF

Page 287 - IP_a ID Space

1-20 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Notes 1. For a complete description of the register bits, refer to the

Page 288 - IP to Local Bus Data Routing

Memory Mapshttp://www.mcg.mot.com/literature 1-211Detailed I/O Memory MapsTables 1-7 through 1-17 give the detailed memory maps for: Note Manufacturer

Page 289

In this manual, assertion and negation are used to specify forcing a signal to a particular state. In particular, assertion and assert refer to a sign

Page 290 - I/O and ID Space Accesses

1-22 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Table 1-7. VMEchip2 Memory Map (Sheet 1 of 3)DMA TBSNP MODEROMZEROSRA

Page 291 - Features

Memory Mapshttp://www.mcg.mot.com/literature 1-231This sheet begins on facing page.ARBROBNMASTDHBMASTDWBMSTFAIRMSTRWDMASTERVMEBUSDMAHALTDMAENDMATBLDMA

Page 292

1-24 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Table 1-7. VMEchip2 Memory Map (Sheet 2 of 3)ENIRQ31ENIRQ30ENIRQ29ENI

Page 293 - Cache Coherency

Memory Mapshttp://www.mcg.mot.com/literature 1-251This sheet begins on facing page.0123456789101112131415VMEACCESSTIMERLOCALBUSTIMERWD TIME OUTSELECTP

Page 294

1-26 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Table 1-7. VMEchip2 Memory Map (Sheet 3 of 3) VMEchip2 GCSR Base Addr

Page 295

http://www.mcg.mot.com/literature 1-271Memory Maps1Board Description and Memory Maps0Memory MapsTable 1-8. MC2 Chip Register MapMC2 Chip Base Address

Page 296

1-28 Computer Group Literature Center Web SiteBoard Description and Memory Maps1The following memory map table includes all devices selected by the IP

Page 297 - Error Logging

Memory Mapshttp://www.mcg.mot.com/literature 1-291 Table 1-10. IP2 Chip Memory Map - Control and Status RegistersIP2 Chip Base Address = $FFFBC000Reg

Page 298 - Chip Defaults

1-30 Computer Group Literature Center Web SiteBoard Description and Memory Maps1$18 IP_a GENERAL CONTROLa_ERR 0 a_RT1 a_RT0 a_WIDTH1 a_WIDTH0 a_BTD a_

Page 299

Memory Mapshttp://www.mcg.mot.com/literature 1-311DMAC for IndustryPack a, request 0. This register set is referred to as DMACa in the text.$20 DMA_a

Page 300 - Offset Name

The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., first published 1990, and may be us

Page 301

1-32 Computer Group Literature Center Web SiteBoard Description and Memory Maps1DMAC for IndustryPack b, request 0 or for IndustryPack a, request 1. T

Page 302 - Register Bit Names

Memory Mapshttp://www.mcg.mot.com/literature 1-331DMAC for IndustryPack c, request 0. This register set is referred to as DMACc in the text.$50 DMA_c

Page 303

1-34 Computer Group Literature Center Web SiteBoard Description and Memory Maps1DMAC for IndustryPack d, request 0 or for IndustryPack c, request 1, a

Page 304

Memory Mapshttp://www.mcg.mot.com/literature 1-351The following MCECC memory map applies only to the 200/300-Series MVME172 boards. $80 PACER INT CON

Page 305 - Memory Configuration Register

1-36 Computer Group Literature Center Web SiteBoard Description and Memory Maps1$40SCRUB PRESCALESPS7 SPS6 SPS5 SPS4 SPS3 SPS2 SPS1 SPS0$44SCRUB TIMER

Page 306 - Dummy Register 0

Memory Mapshttp://www.mcg.mot.com/literature 1-371Note A bug in MVME172s that have MC2 chip revision $01 does not allow the data registers to be acces

Page 307 - Base Address Register

1-38 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Notes 1. Refer to the MPU Port and MPU Channel Attention registers in

Page 308

Memory Mapshttp://www.mcg.mot.com/literature 1-391 Note Accesses may be 8-bit or 32-bit, but not 16-bit. Table 1-14. 53C710 SCSI Memory Map Base Addr

Page 309

1-40 Computer Group Literature Center Web SiteBoard Description and Memory Maps1BBRAM/TOD Clock Memory MapThe MK48T58 BBRAM (also called Non-Volatile

Page 310 - BCLK Frequency Register

http://www.mcg.mot.com/literature 1-411Memory Maps1Board Description and Memory Maps0Memory MapsTable 1-16. BBRAM Configuration Area Memory MapAddres

Page 312

1-42 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Note IP_c and IP_d are not used on 200/300-Series MVME172 modules. Not

Page 313 - Scrub Control Register

Memory Mapshttp://www.mcg.mot.com/literature 1-431The data structure of the configuration bytes starts at $FFFC1EF8 and is as follows. struct brdi_cnf

Page 314

1-44 Computer Group Literature Center Web SiteBoard Description and Memory Maps1minor version numbers. For example, if the version of this structure i

Page 315 - Chip Prescaler Counter

Memory Mapshttp://www.mcg.mot.com/literature 1-4519. Eight bytes are reserved for the printed wiring board (PWB) number assigned to the memory mezzani

Page 316 - STON2-STON0

1-46 Computer Group Literature Center Web SiteBoard Description and Memory Maps120. Eight bytes are reserved for the serial number, in ASCII, assigned

Page 317

Software Support Considerationshttp://www.mcg.mot.com/literature 1-471VMEbus Accesses to the Local BusThe VMEchip2 includes a user-programmable map de

Page 318

1-48 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Cache CoherencyThe MC68060 has the ability to watch local bus cycles e

Page 319

Software Support Considerationshttp://www.mcg.mot.com/literature 1-491VMEbus Access Time-outA VMEbus Access Time-out occurs whenever a VMEbus bound tr

Page 320

1-50 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Generally, the bus error handler can interrogate the status bits and p

Page 321 - Error Logger Register

Software Support Considerationshttp://www.mcg.mot.com/literature 1-511MPU Off-board ErrorDescription:An error occurred while the MPU was attempting to

Page 322 - Error Address (Bits 31-24)

viiContentsCHAPTER 1 Board Description and Memory MapsIntroduction...

Page 323 - Error Address Bits (7-4)

1-52 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Status:Bit 7 of the MPU Status and DMA Interrupt Count Register, (actu

Page 324 - Defaults Register 1

Software Support Considerationshttp://www.mcg.mot.com/literature 1-531Comments:If the TBL bit is set (address $FFF40048 bit 2) the error occurred duri

Page 325

1-54 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Comments:This indicates the DMAC attempted to access a local bus addre

Page 326 - Defaults Register 2

Software Support Considerationshttp://www.mcg.mot.com/literature 1-551Comments:The LANCE has no ability to respond to TEA so the error interrupt and s

Page 327 - Initialization

1-56 Computer Group Literature Center Web SiteBoard Description and Memory Maps1SCSI Parity ErrorNote The 400/500-Series MVME172 models do not contain

Page 328

Software Support Considerationshttp://www.mcg.mot.com/literature 1-571MPU Notification:53C710 Interrupt.Status:53C710 DMA Status Register 53C710 DMA I

Page 329 - Syndrome Decode

1-58 Computer Group Literature Center Web SiteBoard Description and Memory Maps1and when VMEbus mastership has been granted. Because we have found in

Page 330

Software Support Considerationshttp://www.mcg.mot.com/literature 1-591The MVME172 makes the following assumptions and supports a limited subset of RMW

Page 331

1-60 Computer Group Literature Center Web SiteBoard Description and Memory Maps1

Page 332

2-122VMEchip2IntroductionThis chapter describes the VMEchip2 ASIC, local bus to VMEbus interface chip. The VMEchip2 interfaces the local bus to the VM

Page 333 - ARelated Documentation

viiiDMAC TEA - Cause Unidentified...1-54LAN Parity Error...

Page 334 - Manufacturers’ Documents

2-2 Computer Group Literature Center Web SiteVMEchip22❏ VMEbus Bus to Local Bus Interface: – Programmable VMEbus map decoder. – Programmable AM decode

Page 335 - Publication

Introductionhttp://www.mcg.mot.com/literature 2-32❏ VMEbus Interrupter: – Software-configured IRQ1-IRQ7 interrupt request level. – 8-bit software-prog

Page 336 - Related Documentation

2-4 Computer Group Literature Center Web SiteVMEchip22Functional BlocksThe following sections provide an overview of the functions provided by the VME

Page 337 - BUsing Interrupts on

Functional Blockshttp://www.mcg.mot.com/literature 2-52Figure 2-1. VMEchip2 Block Diagram1344 9403DATACONTROLADDRESSCONTROLDATACONTROLADDRESSDATACONT

Page 338

2-6 Computer Group Literature Center Web SiteVMEchip22Using the four programmable map decoders, separate VMEbus maps can be created, each with its own

Page 339

Functional Blockshttp://www.mcg.mot.com/literature 2-72have been accessed. This enhances the portability of software because it allows software to run

Page 340

2-8 Computer Group Literature Center Web SiteVMEchip22The requester requests the bus if any of the following conditions occur: 1. The local bus master

Page 341 - Numerics

Functional Blockshttp://www.mcg.mot.com/literature 2-92VMEbus to Local Bus InterfaceThe VMEbus to local bus interface allows an off-board VMEbus maste

Page 342

2-10 Computer Group Literature Center Web SiteVMEchip22Each map decoder includes an alternate address register and an alternate address select registe

Page 343

Functional Blockshttp://www.mcg.mot.com/literature 2-112Using control register bits in the LCSR, the DMAC can be configured to provide the following V

Page 344

ixVMEbus Slave Address Translation Select Register 1 ...2-30VMEbus Slave Address Translation Address Offset Register 2 ...

Page 345

2-12 Computer Group Literature Center Web SiteVMEchip22The DMAC also supports command chaining through the use of a singly- linked list built in local

Page 346

Functional Blockshttp://www.mcg.mot.com/literature 2-132transfers which are not an even byte count or start at an odd address, with respect to the por

Page 347 - MCECC internal register 1-35

2-14 Computer Group Literature Center Web SiteVMEchip22The DMAC requester requests the bus as required to transfer data to or from the FIFO buffer. Th

Page 348

Functional Blockshttp://www.mcg.mot.com/literature 2-152Tick TimersThe VMEchip2 includes two general purpose tick timers. These timers can be used to

Page 349

2-16 Computer Group Literature Center Web SiteVMEchip22VMEbus InterrupterThe interrupter provides all the signals necessary to allow software to reque

Page 350

Functional Blockshttp://www.mcg.mot.com/literature 2-172VMEbus System ControllerWith the exception of the optional SERCLK Driver and the Power Monitor

Page 351

2-18 Computer Group Literature Center Web SiteVMEchip22In addition to the VMEbus timer, the chip contains a local bus timer. This timer asserts the lo

Page 352

Functional Blockshttp://www.mcg.mot.com/literature 2-192The write post bus error interrupter is an edge-sensitive interrupter connected to the local b

Page 353 - Embedded Controller

2-20 Computer Group Literature Center Web SiteVMEchip22and monitor. On the local bus, the interrupt handler is designed to comply with the interrupt h

Page 354

LCSR Programming Modelhttp://www.mcg.mot.com/literature 2-212❏ Line 4 defines the operations possible on the register bits as follows: ❏ Line 5 define

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