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MPC564EVB User’s Manual 1-5

System Memory

may erase or corrupt the debug monitor. If the debug monitor becomes corrupted and it’s operation

is desired, the firmware must be programmed into the flash by applying a development port tool

such as BDM or Nexus. User should use caution to avoid this situation. The upper 1 MByte is used

to store the MPC564EVB dBUG debugger/monitor firmware (0x0090_0000 to 0x009F_FFFF).

1.2.2 SRAM

The MPC564EVB has one 512 KByte device on the board (U2). It’s starting address is

0xFFF0_0000.

The synchronous SRAM Memory Bank is composed of one (optional 2) 128K x 32 memory

devices. These memory devices are connected in linear order from U2 to U3 if more than one is

available, so that the low order address of the memory bank will access U2 and the high order

addresses of the memory bank will access U3. This memory bank must be configured as a 32 bit

wide port but is byte, half word, and word accessible for read or write operations.

Also see Section 1.2.5, “MPC564EVB Memory Map”.

1.2.3 Internal SRAM

The MPC564 processor has 32-KBtyes of internal memory which may be used as data or

instruction memory. This memory is mapped to 0x003F_8000 and configured as data space but is

not used by the dBUG monitor except during system initialization. After system initialization is

complete, the internal memory is available to the user. The memory is relocatable to any 32-KByte

boundary.

1.2.4 Internal Flash

The MPC564 has a U-bus CDR3 flash EEPROM module (UC3F). The primary function of the

UC3F flash EEPROM module is to serve as electrically programmable and erasable non-volitle

memory (NVM) to store program instructions and/or data. The MPC564 flash EEPROM array has

512 Kbytes of NVM that is divided into eight 64-Kbyte array blocks. If the flash array is disabled

in the IMMR register (FLEN=0), then neither the UC3F array or the UC3F control registers are

accessible. This feature allows the MPC564 to emulate the MPC561/562.

Please refer to the MPC564 User’s Manual for more details.

NOTE:

The internal flash can not be programmed at 66MHz. Please see the

MPC564CZP66 Electrical Spec for other limitations at 66MHz.

1.2.5 MPC564EVB Memory Map

Interface signals to support interface to external memory and peripheral devices are generated by

the memory controller. It supports four regions on four chip-select pins. The general purpose

chip-selects are available on lines CS[0] through CS[3]. CS[0] also functions as the global (boot)

chip-select for booting out of external flash.

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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Motorola MPC564EVB Manuel d'utilisateur Page 15

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