Motorola MPC564EVB Manuel d'utilisateur télécharger pdf (Page 19)

MPC564EVB User’s Manual 1-9

Support Logic

1.3.4 Exception Sources

The MPC500 family of processors can receive exceptions as a result of external signals, errors,

interrupts, or unusual conditions arising in the execution of instructions. When the processor

receives an exception, information about the state of the processor is saved and, after switching to

supervisor mode, the processor begins handling the exception based on instructions in the

Exception Vector Table in memory. Exceptions are handled in program order based on PowerPC

architecture requirements. When an exception occurs that was caused by an instruction, any

unexecuted instructions that appear earlier in the instruction stream are required to complete before

the exception is taken. Exceptions no associated with a specific instruction (asynchronous

exceptions) are recognized when they occur. Exception handlers should save the information in

SRR0 and SRR1 soon after the exception is taken to prevent this information from being lost due

to another exception being taken.

The processor goes to an exception routine via the exception table. This table is stored in the Flash

EEPROM. The address of the table location is set by the IP bit (switch 5 of MAP_SWITCH). The

dBUG ROM monitor writes a copy of the exception table into the RAM starting at 0xFFF0_0000.

To set an exception vector, the user places the address of the exception handler in the appropriate

vector in the vector table located at 0xFFF0_0000.

The MPC564’s interrupt controller supports up to 8 external interrups (0 - 7), eight levels for all

internal USIU interrupt sources and 32 levels for internal peripheral modules. It has an enhanced

mode of operation, which simplifies the MPC564 interrupt structure and speeds up interrupt

processing.

NOTE:

No interrupt sources should have the same level and priority as

another. Programming two interrupt sources with the same level and

priority can result in undefined operation.

The MPC564EVB hardware uses IRQ

[0]/SGPIOC[0] to support the ABORT (Non Maskable

Interrupt) function using the ABORT switch (SWITCH1 when BRK_EN jumper is inserted). This

switch is used to force a non-maskable interrupt if the user's program execution should be aborted

without issuing a RESET.

Refer to MPC564 User’s Manual for more information about the interrupt controller.

1.3.5 TA Generation

The TA signal is driven by the slave device from which the current transaction was addressed. It

indicates that the slave has received the data on the write cycle or returned data on the read cycle.

If the transaction is a burst, TA should be asserted for each one of the transaction beats. The

MPC564 drives TA when the slave device is controlled by the on-chip memory controller or when

an external master initiated a transaction to an internal slave module. TA is used to indicate the

completion of the bus cycle. It also allows devices with different access times to communicate with

the processor properly (i.e. asynchronously) like the Ethernet controller. The internal TA generator

is used for all external memories. External TA is only used for Ethernet/LCD.

1.3.6 User’s Program

Switch 5 on the MAP_SW bank of switches allows users to test code from boot/PORESET without

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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Motorola MPC564EVB Manuel d'utilisateur Page 19

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