Motorola CPCI-6115 Manuel de service Page 129
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Noté. / 5. Basé sur avis des utilisateurs
Default PCI Memory Map Memory Maps
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
127
This is a suggested map only. Motorola developed firmware and software adheres to the
following mapping, but end user applications are free to select an alternate mapping.
1. The internal registers only occupy the first 64 KB but minimum address decoding resolution
is 1 MB.
8.2.3 Default PCI Memory Map
The MV64360 presents the following default PCI memory map after RESET negation.
Table 8-2 Suggested PPC Memory Map
Processor Address
Size Definition NotesStart End
0000 0000 top_dram-1 dram_size System Memory (onboard DRAM)
8000 0000 9FFF FFFF 512 MB PCI Bus 0 Memory Space
B000 0000 CFFF FFFF 512 MB PCI Bus 1 Memory Space
F000 0000 F07F FFFF 8 MB PCI Bus 0 I/O Space
F080 0000 F0FF FFFF 8 MB PCI Bus 1 I/O Space
F100 0000 F10F FFFF 1 MB MV64360 Internal Registers 1
F110 0000 F11F FFFF 1 MB Device CS1* I/O System
Regs/NVRAM/RTC/UART
F200 0000 F5FF FFFF 64 MB Flash Bank A
FF800 0000 FFFF FFFF 8 MB Flash Bank B
Table 8-3 Default PCI Address Map
PCI Address
Size Definition
Notes
Start End
0000 0000 007F FFFF 8 MB DRAM Bank 0
0080 0000 00FF FFFF 8 MB DRAM Bank 1
0100 0000 017F FFFF 8 MB DRAM Bank 2
0180 0000 01FF FFFF 8 MB DRAM Bank 3
0200 0000 0FFF FFFF 224 MB Unassigned
1000 0000 11FF FFFF 32 MB PCI Bus 1 P2P I/O Space
1200 0000 13FF FFFF 32 MB PCI Bus 1 P2P Memory Space 0
1400 0000 1400 FFFF 64 KB Internal Registers
1401 0000 1BFF FFFF 128 MB- 64 KB Unassigned
1C00 0000 1C7F FFFF 8 MB Device CS0*
1C80 0000 1CFF FFFF 8 MB Device CS1*
1D00 0000 1DFF FFFF 16 MB Device CS2*
- CPCI-6115 CompactPCI 1
- Single Board Computer 1
- Trademarks 2
- Contents 3
- List of Tables 10
- List of Figures 11
- About this Manual 13
- Abbreviations 14
- Conventions 16
- Summary of Changes 17
- Comments and Suggestions 18
- Safety Notes 19
- Operation 20
- Installation 20
- Cabling and Connectors 21
- Environment 22
- Sicherheitshinweise 23
- Schaltereinstellungen/Jumper 24
- Kabel und Stecker 26
- Umweltschutz 26
- Batterie 26
- Introduction 27
- 1.2 Standard Compliances 28
- 1.3 Ordering Information 29
- 2.1 Overview 31
- Requirements 32
- 2.3.2 Power Requirements 34
- 2.3.3 Thermal Requirements 34
- 2.4 Getting Started 37
- 2.5 Baseboard Preparation 38
- 2.5.3 J6, Bus Mode Selection 40
- 2.5.7 J20, Safe Start Header 42
- 2.6 Operating Modes 44
- 2.7 Installing Hardware 44
- Procedure 45
- Personal Injury or Death 46
- 2.9 Applying Power 49
- 3.1 Overview 51
- 3.2 Board Layout 52
- 3.4 ABORT/Reset Switch 54
- 3.5.7 CompactPCI Connector 58
- PCI_RSVD = PCI Reserved pin 62
- 3.5.14 Safe Start Header 67
- 3.5.15 Bus Mode Select Header 67
- 3.5.18 +/-12 V Present Header 68
- Functional Description 69
- 4.2 Block Diagram 70
- 4.3 General Description 71
- 4.3.2 Processor 72
- 4.3.3 L3 Cache 72
- 4.3.4.12 Interrupt Controller 76
- 4.3.4.13 PCI Bus Arbitration 76
- 4.3.4.14 Board Reset Logic 77
- 4.3.5 System Memory 81
- 4.3.6 Flash Memory 82
- 4.3.8 TL16C550C UART Devices 83
- 4.3.9 System Registers 83
- 4.3.10 Serial EEPROM Devices 83
- 4.3.11 PCI Bus 0.0 83
- 4.3.12 PCI Bus 1.0 83
- 4.3.13 IDE Controller 84
- 4.3.15 CompactPCI Bus 84
- 4.3.16 PMC Slots 84
- 4.4 Miscellaneous 86
- 4.4.3 Onboard Power Supplies 89
- 4.4.4 Hot Swap Support 89
- 4.4.5 Hot Swap Process 89
- 5.2 Block Diagram 92
- 5.4 Rear Panel Connectors 94
- 5.5.2.1 Host IO Connectors 96
- 5.5.2.2 PMC I/O Connectors 98
- 5.6 Jumper Settings 104
- 5.7 Functional Description 105
- 5.7.3 Hot-Swap Support 106
- 5.7.4 Serial EEPROM 106
- 5.7.5 PMC I/O Modules 106
- 5.7.7 PMC I/O Module 110
- 5.7.9 PMC I/O Connector 112
- 5.7.10 Host I/O Connector 112
- 5.8 Installing the PIM 113
- Figure 5-9 Installing the PIM 114
- Remote Start via the PCI Bus 117
- MOTLoad Firmware 119
- 7.4 MOTLoad Commands 120
- 7.6 MOTLoad Tests 120
- 7.7 Using MOTLoad 121
- 7.7.2 Command Line Help 122
- 7.7.3 Command Line Rules 122
- 7.8 MOTLoad Command List 123
- Memory Maps 127
- 8.2.2 Processor Memory Map 128
- 8.2.3 Default PCI Memory Map 129
- 8.2.5 System I/O Memory Map 131
- 8.2.7 CompactPCI Memory Map 131
- 8.2.9 L1, L2 and L3 Cache 132
- 8.2.10 System Memory 132
- A Related Documentation 133
- A.3 Related Specifications 134
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