Motorola CPCI-6115 Manuel de service Page 54
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CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Controls, LEDs, and Connectors ABORT/Reset Switch
52
3.4 ABORT/Reset Switch
The CPCI-6115 contains a single push button switch that provides both ABORT and RESET
functions. When the switch is depressed for less than 3 seconds, an ABORT interrupt is
generated to the processor. If the switch is held for more than 3 seconds, a board hard reset is
generated.
3.5 On-Board Connectors and Headers
The CPCI-6115 CPU board provides the on-board connectors and jumper headers listed in the
next table. Use the links in the Location column to go to the description and pin assignment for
each connector.
3.5.1 J19, Front Panel Asynchronous Serial Port
An RJ-45 receptacle is located on the front panel of the CPCI-6115 CPU board to provide the
interface to the COM1 serial port. This port is configured as DTE. The pin assignments for this
connector are as follows:
Connector/Header Location
CPCI-6115 CompactPCI Connectors ( J1/J2 ) Table 3-4 on page 54
CPCI-6115 CompactPCI User I/O Connector (J3) Table 3-5 on page 54
CPCI-6115 CompactPCI Connector (J4) N/A
CPCI-6115 CompactPCI User I/O Connector (J5) Table 3-7 on page 57
CPCI-6115 PCI Mezzanine Card (PMC) Connectors (J11/J21) Table 3-8 on page 59
CPCI-6115 PCI Mezzanine Card (PMC) Connectors (J12/J22) Table 3-9 on page 60
CPCI-6115 PCI Mezzanine Card (PMC) Connectors (J13/J23) Table 3-10 on page 61
CPCI-6115 PCI Mezzanine Card (PMC) Connectors (J14/J24) Table 3-11 on page 62
Boundary Scan JTAG Header (J16) Table 3-12 on page 63
CPCI-6115 Riscwatch Header (J17) Table 3-13 on page 63
Standalone Operation Select Header (J9) Table 3-14 on page 64
CPCI-6115 Flash Boot Bank Select Header (J10) Table 3-15 on page 64
Safe Start Header (J20) Table 3-16 on page 65
Bus Mode Select Header (J6) Table 3-17 on page 65
SROM Init Enable Header (J25) Table 3-18 on page 65
Flash Bank A Write Protect Header (J99) Table 3-19 on page 66
+/-12 V Present Header (J15) Table 3-20 on page 66
Table 3-2 COM1 Pin Assignments, J19
Pin # Signal Direction
1DCD INPUT
- CPCI-6115 CompactPCI 1
- Single Board Computer 1
- Trademarks 2
- Contents 3
- List of Tables 10
- List of Figures 11
- About this Manual 13
- Abbreviations 14
- Conventions 16
- Summary of Changes 17
- Comments and Suggestions 18
- Safety Notes 19
- Operation 20
- Installation 20
- Cabling and Connectors 21
- Environment 22
- Sicherheitshinweise 23
- Schaltereinstellungen/Jumper 24
- Kabel und Stecker 26
- Umweltschutz 26
- Batterie 26
- Introduction 27
- 1.2 Standard Compliances 28
- 1.3 Ordering Information 29
- 2.1 Overview 31
- Requirements 32
- 2.3.2 Power Requirements 34
- 2.3.3 Thermal Requirements 34
- 2.4 Getting Started 37
- 2.5 Baseboard Preparation 38
- 2.5.3 J6, Bus Mode Selection 40
- 2.5.7 J20, Safe Start Header 42
- 2.6 Operating Modes 44
- 2.7 Installing Hardware 44
- Procedure 45
- Personal Injury or Death 46
- 2.9 Applying Power 49
- 3.1 Overview 51
- 3.2 Board Layout 52
- 3.4 ABORT/Reset Switch 54
- 3.5.7 CompactPCI Connector 58
- PCI_RSVD = PCI Reserved pin 62
- 3.5.14 Safe Start Header 67
- 3.5.15 Bus Mode Select Header 67
- 3.5.18 +/-12 V Present Header 68
- Functional Description 69
- 4.2 Block Diagram 70
- 4.3 General Description 71
- 4.3.2 Processor 72
- 4.3.3 L3 Cache 72
- 4.3.4.12 Interrupt Controller 76
- 4.3.4.13 PCI Bus Arbitration 76
- 4.3.4.14 Board Reset Logic 77
- 4.3.5 System Memory 81
- 4.3.6 Flash Memory 82
- 4.3.8 TL16C550C UART Devices 83
- 4.3.9 System Registers 83
- 4.3.10 Serial EEPROM Devices 83
- 4.3.11 PCI Bus 0.0 83
- 4.3.12 PCI Bus 1.0 83
- 4.3.13 IDE Controller 84
- 4.3.15 CompactPCI Bus 84
- 4.3.16 PMC Slots 84
- 4.4 Miscellaneous 86
- 4.4.3 Onboard Power Supplies 89
- 4.4.4 Hot Swap Support 89
- 4.4.5 Hot Swap Process 89
- 5.2 Block Diagram 92
- 5.4 Rear Panel Connectors 94
- 5.5.2.1 Host IO Connectors 96
- 5.5.2.2 PMC I/O Connectors 98
- 5.6 Jumper Settings 104
- 5.7 Functional Description 105
- 5.7.3 Hot-Swap Support 106
- 5.7.4 Serial EEPROM 106
- 5.7.5 PMC I/O Modules 106
- 5.7.7 PMC I/O Module 110
- 5.7.9 PMC I/O Connector 112
- 5.7.10 Host I/O Connector 112
- 5.8 Installing the PIM 113
- Figure 5-9 Installing the PIM 114
- Remote Start via the PCI Bus 117
- MOTLoad Firmware 119
- 7.4 MOTLoad Commands 120
- 7.6 MOTLoad Tests 120
- 7.7 Using MOTLoad 121
- 7.7.2 Command Line Help 122
- 7.7.3 Command Line Rules 122
- 7.8 MOTLoad Command List 123
- Memory Maps 127
- 8.2.2 Processor Memory Map 128
- 8.2.3 Default PCI Memory Map 129
- 8.2.5 System I/O Memory Map 131
- 8.2.7 CompactPCI Memory Map 131
- 8.2.9 L1, L2 and L3 Cache 132
- 8.2.10 System Memory 132
- A Related Documentation 133
- A.3 Related Specifications 134
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