Motorola CPCI-6115 Manuel de service télécharger pdf (Page 72)

CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

Functional Description Processor

The MPC7457 processor uses +2.5 V signal levels on the processor bus. Care should be taken

that probe boards attached to the debug connector do not pull up or drive signals in violation of

this.

The JTAG port is tolerant of +3.3 V signals.

Arbitration on the processor bus is provided by the MV64360 chip.

4.3.2 Processor

The CPCI-6115 has the 360-pin CBGA foot print that supports the MPC7457 family of

processors. The MPC7457 processors have integrated L1 and L2 caches and has a L3 cache

interface with on-chip tags to support up to 2MB of off-chip cache. The CPCI-6115 initially

supports processor core frequencies of 866 MHz and 1 GHz and an external processor bus

speed of 133 MHz. The common processor configuration will support variable core voltages

between +0.8 V and +1.6V.

4.3.3 L3 Cache

The CPCI-6115 external L3 cache/private memory is implemented using two 8 megabit DDR

SRAM devices. The MPC7457 allows a maximum of 2 MB of memory on the L3 cache bus,

which may be allocated as L3 cache, private memory or a combination of both.

The L3 cache bus is 72-bits wide (64 bits of data and 8 bits of parity). The MPC7457 has an on-

chip, 8-way, set-associative tag memory. The external SRAMs are accessed through a

dedicated L3 cache port which supports one bank of SRAM. The L3 cache normally operates

in copyback mode and supports system cache coherency through snooping. Parity generation

and checking may be disabled by programming the L3CR register of the Apollo (MPC7457)

device. Refer to the PowerPC Apollo Microprocessor Implementation Definition Book IV, listed

in Appendix A, Related Documentation, for more information (Addendum to SC-Vger Book IV

Version - 1.0 04/21/00).

4.3.4 MV64360 System Controller

The MV64360 is an integrated system controller for high performance embedded control

applications. The following features of the MV64360 are supported by the CPCI-6115. The

MV64360 has a five bus architecture comprised of:

z 72-bit interface to the CPU bus (with parity)

z 72-bit interface to DDR SDRAM (with ECC)

z 32-bit interface to devices

z Two 64-bit PCI/PCI-X interfaces

In addition to the above the MV64360 integrates the following:

z Three gigabit Ethernet MACs

z Interrupt controller

z Four general-purpose 32-bit timers/counters

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Motorola CPCI-6115 Manuel de service Page 72