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CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Functional Description MV64360 System Controller
74
the second function, the controller is used by the system software to read the contents of the
VPD EEPROM contained on the CPCI-6115 board, along with the SPD EEPROMs for the
onboard memory banks, to further initialize the memory controller and other interfaces. See the
programming model section of this document for more information including I
2
C bus device
addressing.
The CPCI-6115 board has the following I
2
C serial devices connected to this I
2
C bus:
z 8 KB EEPROM for user defined MV64360 initialization
z 8 KB EEPROM for VPD
z 8 KB EEPROM for user data
z Two 256-byte EEPROMs for SPD
z DS1621 Temperature Sensor
The 8 KB devices are Atmel AT24C04N Serial EEPROMs.
4.3.4.12 Interrupt Controller
The CPCI-6115 uses the interrupt controller integrated into MV64360 to manage the MV64360
internal interrupts, as well as external interrupt requests. The interrupts are routed to the
MV64360 MPP pins from onboard resources as shown in Figure 4-2 on page 75. The external
interrupt sources include the following:
z Onboard PCI device interrupts
z PMC slot interrupts
z RTC interrupt
z Watchdog timer interrupts
z ABORT switch interrupt
z External UART interrupts
z CompactPCI interrupts
z Ethernet PHY interrupts
For added information on external interrupt assignments, refer to the MCPN905 CompactPCI
Single Board Computer Programmer’s Reference Guide.
4.3.4.13 PCI Bus Arbitration
PCI arbitration is performed by the MV64360 chip. The MV64360 integrates two PCI arbiters,
one for each PCI interface (PCI Bus 0.0/1.0). Each arbiter can handle up to six external agents
plus one internal agent (PCI Bus 0.0/1.0 master). The internal PCI arbiter REQ#/GNT# signals
are multiplexed on the MV64360 MPP pins. The internal PCI arbiter is disabled by default (the
MPP pins function as general purpose inputs). Software will configure the MPP pins to function
as request/grant pairs for the internal PCI arbiter. The arbitration pairs for the CPCI-6115 are
assigned to the MPP pins as shown in the following table.
- CPCI-6115 CompactPCI 1
- Single Board Computer 1
- Trademarks 2
- Contents 3
- List of Tables 10
- List of Figures 11
- About this Manual 13
- Abbreviations 14
- Conventions 16
- Summary of Changes 17
- Comments and Suggestions 18
- Safety Notes 19
- Operation 20
- Installation 20
- Cabling and Connectors 21
- Environment 22
- Sicherheitshinweise 23
- Schaltereinstellungen/Jumper 24
- Kabel und Stecker 26
- Umweltschutz 26
- Batterie 26
- Introduction 27
- 1.2 Standard Compliances 28
- 1.3 Ordering Information 29
- 2.1 Overview 31
- Requirements 32
- 2.3.2 Power Requirements 34
- 2.3.3 Thermal Requirements 34
- 2.4 Getting Started 37
- 2.5 Baseboard Preparation 38
- 2.5.3 J6, Bus Mode Selection 40
- 2.5.7 J20, Safe Start Header 42
- 2.6 Operating Modes 44
- 2.7 Installing Hardware 44
- Procedure 45
- Personal Injury or Death 46
- 2.9 Applying Power 49
- 3.1 Overview 51
- 3.2 Board Layout 52
- 3.4 ABORT/Reset Switch 54
- 3.5.7 CompactPCI Connector 58
- PCI_RSVD = PCI Reserved pin 62
- 3.5.14 Safe Start Header 67
- 3.5.15 Bus Mode Select Header 67
- 3.5.18 +/-12 V Present Header 68
- Functional Description 69
- 4.2 Block Diagram 70
- 4.3 General Description 71
- 4.3.2 Processor 72
- 4.3.3 L3 Cache 72
- 4.3.4.12 Interrupt Controller 76
- 4.3.4.13 PCI Bus Arbitration 76
- 4.3.4.14 Board Reset Logic 77
- 4.3.5 System Memory 81
- 4.3.6 Flash Memory 82
- 4.3.8 TL16C550C UART Devices 83
- 4.3.9 System Registers 83
- 4.3.10 Serial EEPROM Devices 83
- 4.3.11 PCI Bus 0.0 83
- 4.3.12 PCI Bus 1.0 83
- 4.3.13 IDE Controller 84
- 4.3.15 CompactPCI Bus 84
- 4.3.16 PMC Slots 84
- 4.4 Miscellaneous 86
- 4.4.3 Onboard Power Supplies 89
- 4.4.4 Hot Swap Support 89
- 4.4.5 Hot Swap Process 89
- 5.2 Block Diagram 92
- 5.4 Rear Panel Connectors 94
- 5.5.2.1 Host IO Connectors 96
- 5.5.2.2 PMC I/O Connectors 98
- 5.6 Jumper Settings 104
- 5.7 Functional Description 105
- 5.7.3 Hot-Swap Support 106
- 5.7.4 Serial EEPROM 106
- 5.7.5 PMC I/O Modules 106
- 5.7.7 PMC I/O Module 110
- 5.7.9 PMC I/O Connector 112
- 5.7.10 Host I/O Connector 112
- 5.8 Installing the PIM 113
- Figure 5-9 Installing the PIM 114
- Remote Start via the PCI Bus 117
- MOTLoad Firmware 119
- 7.4 MOTLoad Commands 120
- 7.6 MOTLoad Tests 120
- 7.7 Using MOTLoad 121
- 7.7.2 Command Line Help 122
- 7.7.3 Command Line Rules 122
- 7.8 MOTLoad Command List 123
- Memory Maps 127
- 8.2.2 Processor Memory Map 128
- 8.2.3 Default PCI Memory Map 129
- 8.2.5 System I/O Memory Map 131
- 8.2.7 CompactPCI Memory Map 131
- 8.2.9 L1, L2 and L3 Cache 132
- 8.2.10 System Memory 132
- A Related Documentation 133
- A.3 Related Specifications 134
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