Motorola CPCI-6115 Manuel de service Page 82
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CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Functional Description Flash Memory
80
4.3.6 Flash Memory
The CPCI-6115 contains two banks of flash memory accessed via the device controller bus
contained within the MV64360 chip. Bank B consists of two Intel StrataFlash +3.3 V devices,
configured to operate in 16-bit mode, to form a 32-bit flash bank. Bank B provides a minimum
of 8 MB of flash memory.
Bank A consists of two Intel StrataFlash +3.3 V devices, configured to operate in 16-bit mode,
to form a 32-bit flash bank. The following table defines the flash type and size options for Bank
A. The CPCI-6115 standard product is built with the 128 megabit devices. These Intel
StrataFlash devices support page read mode operations with a 8-byte page size per device.
Since the StrataFlash initial access time is 150ns, onboard hardware is used to guarantee initial
access timing using the Device port READY# signal.
A flash write protect header is provided on the CPCI-6115 to enable write protection of the
entire Bank A flash via the device VPEN pins when the jumper is not installed. Bank A write
protection can also be enabled by software using the System Register 2 FLASH_WP bit in the
MV64360 when the jumper is installed.
There is a boot bank select jumper on the CPCI-6115 that selects either Flash Bank A or Bank
B as the boot bank. This jumper effectively routes the MV64360 BOOTCS# pin to either Bank
A/Bank B and chip select CS0# to the other bank (Bank B/Bank A).
4.3.7 NVRAM, Real-Time Clock, Watchdog Timer
An SGS-Thompson M48T37V device is connected to the MV64360 device controller bus. This
device provides 32 KB of nonvolatile static RAM, a real-time clock and a watchdog function.
Refer to the M48T37V Data Sheet for programming information. The M48T37V consists of two
parts:
z One 44-pin 330mil SO device that contains the RTC, the oscillator, the power fail detection,
the watchdog timer logic, 32 KB of SRAM and gold-plated sockets for the SNAPHAT
battery.
z One SNAPHAT that houses the battery and the crystal.
The SNAPHAT package is mounted on top of the SO MT48T37V device after the completion
of the surface mount process.
The watchdog timer can generate a timeout period of 62.5 msec to 128 seconds. The output of
the watchdog timer can be programmed to generate an interrupt or reset the board if enabled.
Table 4-5 Bank A Flash Options
Flash Bank Size Intel Part Number Device Size
8 MB 28F320J3D 32 megabit
16 MB 28F640J3D 64 megabit
32 MB 28F128J3D 128 megabit
64 MB 28F256P3 256 megabit
- CPCI-6115 CompactPCI 1
- Single Board Computer 1
- Trademarks 2
- Contents 3
- List of Tables 10
- List of Figures 11
- About this Manual 13
- Abbreviations 14
- Conventions 16
- Summary of Changes 17
- Comments and Suggestions 18
- Safety Notes 19
- Operation 20
- Installation 20
- Cabling and Connectors 21
- Environment 22
- Sicherheitshinweise 23
- Schaltereinstellungen/Jumper 24
- Kabel und Stecker 26
- Umweltschutz 26
- Batterie 26
- Introduction 27
- 1.2 Standard Compliances 28
- 1.3 Ordering Information 29
- 2.1 Overview 31
- Requirements 32
- 2.3.2 Power Requirements 34
- 2.3.3 Thermal Requirements 34
- 2.4 Getting Started 37
- 2.5 Baseboard Preparation 38
- 2.5.3 J6, Bus Mode Selection 40
- 2.5.7 J20, Safe Start Header 42
- 2.6 Operating Modes 44
- 2.7 Installing Hardware 44
- Procedure 45
- Personal Injury or Death 46
- 2.9 Applying Power 49
- 3.1 Overview 51
- 3.2 Board Layout 52
- 3.4 ABORT/Reset Switch 54
- 3.5.7 CompactPCI Connector 58
- PCI_RSVD = PCI Reserved pin 62
- 3.5.14 Safe Start Header 67
- 3.5.15 Bus Mode Select Header 67
- 3.5.18 +/-12 V Present Header 68
- Functional Description 69
- 4.2 Block Diagram 70
- 4.3 General Description 71
- 4.3.2 Processor 72
- 4.3.3 L3 Cache 72
- 4.3.4.12 Interrupt Controller 76
- 4.3.4.13 PCI Bus Arbitration 76
- 4.3.4.14 Board Reset Logic 77
- 4.3.5 System Memory 81
- 4.3.6 Flash Memory 82
- 4.3.8 TL16C550C UART Devices 83
- 4.3.9 System Registers 83
- 4.3.10 Serial EEPROM Devices 83
- 4.3.11 PCI Bus 0.0 83
- 4.3.12 PCI Bus 1.0 83
- 4.3.13 IDE Controller 84
- 4.3.15 CompactPCI Bus 84
- 4.3.16 PMC Slots 84
- 4.4 Miscellaneous 86
- 4.4.3 Onboard Power Supplies 89
- 4.4.4 Hot Swap Support 89
- 4.4.5 Hot Swap Process 89
- 5.2 Block Diagram 92
- 5.4 Rear Panel Connectors 94
- 5.5.2.1 Host IO Connectors 96
- 5.5.2.2 PMC I/O Connectors 98
- 5.6 Jumper Settings 104
- 5.7 Functional Description 105
- 5.7.3 Hot-Swap Support 106
- 5.7.4 Serial EEPROM 106
- 5.7.5 PMC I/O Modules 106
- 5.7.7 PMC I/O Module 110
- 5.7.9 PMC I/O Connector 112
- 5.7.10 Host I/O Connector 112
- 5.8 Installing the PIM 113
- Figure 5-9 Installing the PIM 114
- Remote Start via the PCI Bus 117
- MOTLoad Firmware 119
- 7.4 MOTLoad Commands 120
- 7.6 MOTLoad Tests 120
- 7.7 Using MOTLoad 121
- 7.7.2 Command Line Help 122
- 7.7.3 Command Line Rules 122
- 7.8 MOTLoad Command List 123
- Memory Maps 127
- 8.2.2 Processor Memory Map 128
- 8.2.3 Default PCI Memory Map 129
- 8.2.5 System I/O Memory Map 131
- 8.2.7 CompactPCI Memory Map 131
- 8.2.9 L1, L2 and L3 Cache 132
- 8.2.10 System Memory 132
- A Related Documentation 133
- A.3 Related Specifications 134
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