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CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Functional Description IDE Controller
82
This bus is limited to 33 MHz PCI because the IDE controller is a 33 MHz-only device. PCI Bus
1.0 is compliant to PCI Revision 2.1. VIO is limited to +5 V only. Do not alter the location of
PMC1 keying pin.
4.3.13 IDE Controller
The CPCI-6115 uses the CMD Technology PCI646U2 IDE Controller to provide a single IDE
channel for external storage devices. The IDE Controller supports ATA/33 transfer rates. This
IDE channel is routed to connector J5 for rear-panel I/O or to a transition module. The transition
module allows connection of an IDE hard disk or CompactFlash module.
The PCI646U2 PCI-IDE Controller is a 32-bit/33 MHz PCI device and is the limiting device when
determining the operating frequency of PCI bus 1.0.
4.3.14 Intel 21555 PCI-to-PCI Bridge
The CPCI-6115 uses the Intel 21555 PCI-to-PCI bridge, which is connected to PCI bus 1.0. The
21555 bridge is compliant to PCI Revision 2.2. The following are key features of the 21555:
z Non-transparent PCI-to-PCI bridge
z Mixed-frequency bus operation (33/66 MHz PCI on either primary or secondary)
z CompactPCI hot-swap compliant
z Secondary bus arbiter (not used on CPCI-6115)
z +3.3 V I/O, +5 V tolerant
The 21555 provides a MicroWire serial ROM interface. On power-up or reset, the 21555 can
load its configuration registers from a serial EEPROM on this interface. A 512-byte (93LC66A)
device is present on the CPCI-6115 for this purpose.
4.3.15 CompactPCI Bus
The CompactPCI bus interface is implemented using the 21555 bridge with a 32-bit secondary
data bus (local side - PCI bus 1.0) and a 64-bit primary data bus (CompactPCI side). The 21555
supports +3.3 V or +5 V signalling at the CompactPCI bus, allowing the CPCI-6115 to operate
in a +3.3 V or +5 V chassis.
The CPCI-6115 is designed for use in a CompactPCI peripheral slot, so the 21555 non-
transparent bridge is used. The CPCI-6115 receives the CompactPCI clock, reset and bus
grant signals, and generates bus requests and interrupts as a peripheral board.
The CPCI-6115 supports a 33/66 MHz PCI interface to the CompactPCI backplane.
4.3.16 PMC Slots
The CPCI-6115 CPU board contains four EIA-E700 AAAB connectors for each PMC slot.
These connectors provide a PCI interface to two IEEE P1386.1-compliant PMC slots.
Connectors J11-J13 and J21-J23 provide the PCI interface while J14 and J24 provide a user
I/O path from the PMC slots to the CompactPCI backplane. PMC user I/O signals are routed
- CPCI-6115 CompactPCI 1
- Single Board Computer 1
- Trademarks 2
- Contents 3
- List of Tables 10
- List of Figures 11
- About this Manual 13
- Abbreviations 14
- Conventions 16
- Summary of Changes 17
- Comments and Suggestions 18
- Safety Notes 19
- Operation 20
- Installation 20
- Cabling and Connectors 21
- Environment 22
- Sicherheitshinweise 23
- Schaltereinstellungen/Jumper 24
- Kabel und Stecker 26
- Umweltschutz 26
- Batterie 26
- Introduction 27
- 1.2 Standard Compliances 28
- 1.3 Ordering Information 29
- 2.1 Overview 31
- Requirements 32
- 2.3.2 Power Requirements 34
- 2.3.3 Thermal Requirements 34
- 2.4 Getting Started 37
- 2.5 Baseboard Preparation 38
- 2.5.3 J6, Bus Mode Selection 40
- 2.5.7 J20, Safe Start Header 42
- 2.6 Operating Modes 44
- 2.7 Installing Hardware 44
- Procedure 45
- Personal Injury or Death 46
- 2.9 Applying Power 49
- 3.1 Overview 51
- 3.2 Board Layout 52
- 3.4 ABORT/Reset Switch 54
- 3.5.7 CompactPCI Connector 58
- PCI_RSVD = PCI Reserved pin 62
- 3.5.14 Safe Start Header 67
- 3.5.15 Bus Mode Select Header 67
- 3.5.18 +/-12 V Present Header 68
- Functional Description 69
- 4.2 Block Diagram 70
- 4.3 General Description 71
- 4.3.2 Processor 72
- 4.3.3 L3 Cache 72
- 4.3.4.12 Interrupt Controller 76
- 4.3.4.13 PCI Bus Arbitration 76
- 4.3.4.14 Board Reset Logic 77
- 4.3.5 System Memory 81
- 4.3.6 Flash Memory 82
- 4.3.8 TL16C550C UART Devices 83
- 4.3.9 System Registers 83
- 4.3.10 Serial EEPROM Devices 83
- 4.3.11 PCI Bus 0.0 83
- 4.3.12 PCI Bus 1.0 83
- 4.3.13 IDE Controller 84
- 4.3.15 CompactPCI Bus 84
- 4.3.16 PMC Slots 84
- 4.4 Miscellaneous 86
- 4.4.3 Onboard Power Supplies 89
- 4.4.4 Hot Swap Support 89
- 4.4.5 Hot Swap Process 89
- 5.2 Block Diagram 92
- 5.4 Rear Panel Connectors 94
- 5.5.2.1 Host IO Connectors 96
- 5.5.2.2 PMC I/O Connectors 98
- 5.6 Jumper Settings 104
- 5.7 Functional Description 105
- 5.7.3 Hot-Swap Support 106
- 5.7.4 Serial EEPROM 106
- 5.7.5 PMC I/O Modules 106
- 5.7.7 PMC I/O Module 110
- 5.7.9 PMC I/O Connector 112
- 5.7.10 Host I/O Connector 112
- 5.8 Installing the PIM 113
- Figure 5-9 Installing the PIM 114
- Remote Start via the PCI Bus 117
- MOTLoad Firmware 119
- 7.4 MOTLoad Commands 120
- 7.6 MOTLoad Tests 120
- 7.7 Using MOTLoad 121
- 7.7.2 Command Line Help 122
- 7.7.3 Command Line Rules 122
- 7.8 MOTLoad Command List 123
- Memory Maps 127
- 8.2.2 Processor Memory Map 128
- 8.2.3 Default PCI Memory Map 129
- 8.2.5 System I/O Memory Map 131
- 8.2.7 CompactPCI Memory Map 131
- 8.2.9 L1, L2 and L3 Cache 132
- 8.2.10 System Memory 132
- A Related Documentation 133
- A.3 Related Specifications 134
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