Motorola CPCI-6115 Manuel de service Page 89
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Onboard Power Supplies Functional Description
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
87
For software compatibility with the GT-64120/130 devices, the MV64360 maintains
MByteSwap and MWordSwap bits in the PCI Command register. If the PCI Command register’s
MSwapEn bit is set to "1", the MV64360 PCI master performs data swapping according to
PCISwap bits setting. If set to "0" (default), it works according to MByteSwap and MWordSwap
bits setting, as in the GT-64120/130 devices.
Refer to the MV64360 data sheet for additional information and programming details.
4.4.3 Onboard Power Supplies
The CPCI-6115 CPU board requires +5 V and +3.3 V input power. The +/-12 V input voltages
are optional and are routed to the PMC slots. All other required voltages are generated onboard
from the +3.3 V or +5 V power. The processor core voltage regulator has a variable output
which is set using feedback resistors. In addition to the processor core voltage regulator, there
are regulators for +1.8 V, +2.5 V, CPU_VIO, +1.25 V and L3_VIO.
4.4.4 Hot Swap Support
The CPCI-6115 provides hardware to support the physical connection process and the
hardware connection process of the full hot swap system model defined in the CompactPCI
Hot-Swap Specification PICMG 2.1 R2.0. Hot swap support is only applicable when the CPCI-
6115 is installed into a CompactPCI peripheral slot.
4.4.5 Hot Swap Process
The CPCI-6115 may be safely inserted and extracted from a hot-swap system chassis while
power is applied. Hot-swap circuitry protects the board from electrical damage.
The BD_SEL# signal from CPCI bus J1 pin D15 must be driven true (low) for the back end
power supplies to switch on. When BD_SEL# is not asserted only a small portion of the CPCI-
6115 circuitry is powered.
For a system without +/-12 V, the HLTY# signal is driven true (low) to the CPCI bus J1 pin B4
when the +5.0 V and +3.3 V input power supplies are within tolerance. For a system with +/-12
V, these supply voltages can also be monitored and included into the HLTY# signal generation.
A jumper selects whether the +/-12 V should be monitored in this way. The HLTY# signal can
be used as a status indicator.
4.4.6 Intel 21555 Hot Swap Support
The 21555 Bridge contains a CompactPCI Hot Swap Control Register which includes the
following functions:
z The 21555 drives the ENUM# signal during a hot-swap event if the ENUM# Interrupt Mask
(ENUM_MASK) bit in the CompactPCI Hot-Swap Control Register is cleared.
z The 21555 supports the LED On/OFF (LOO) status/control bit in the CompactPCI Hot
Swap Control Register which enables the host to determine the status of the blue Hot Swap
LED and/or force the LED on.
- CPCI-6115 CompactPCI 1
- Single Board Computer 1
- Trademarks 2
- Contents 3
- List of Tables 10
- List of Figures 11
- About this Manual 13
- Abbreviations 14
- Conventions 16
- Summary of Changes 17
- Comments and Suggestions 18
- Safety Notes 19
- Operation 20
- Installation 20
- Cabling and Connectors 21
- Environment 22
- Sicherheitshinweise 23
- Schaltereinstellungen/Jumper 24
- Kabel und Stecker 26
- Umweltschutz 26
- Batterie 26
- Introduction 27
- 1.2 Standard Compliances 28
- 1.3 Ordering Information 29
- 2.1 Overview 31
- Requirements 32
- 2.3.2 Power Requirements 34
- 2.3.3 Thermal Requirements 34
- 2.4 Getting Started 37
- 2.5 Baseboard Preparation 38
- 2.5.3 J6, Bus Mode Selection 40
- 2.5.7 J20, Safe Start Header 42
- 2.6 Operating Modes 44
- 2.7 Installing Hardware 44
- Procedure 45
- Personal Injury or Death 46
- 2.9 Applying Power 49
- 3.1 Overview 51
- 3.2 Board Layout 52
- 3.4 ABORT/Reset Switch 54
- 3.5.7 CompactPCI Connector 58
- PCI_RSVD = PCI Reserved pin 62
- 3.5.14 Safe Start Header 67
- 3.5.15 Bus Mode Select Header 67
- 3.5.18 +/-12 V Present Header 68
- Functional Description 69
- 4.2 Block Diagram 70
- 4.3 General Description 71
- 4.3.2 Processor 72
- 4.3.3 L3 Cache 72
- 4.3.4.12 Interrupt Controller 76
- 4.3.4.13 PCI Bus Arbitration 76
- 4.3.4.14 Board Reset Logic 77
- 4.3.5 System Memory 81
- 4.3.6 Flash Memory 82
- 4.3.8 TL16C550C UART Devices 83
- 4.3.9 System Registers 83
- 4.3.10 Serial EEPROM Devices 83
- 4.3.11 PCI Bus 0.0 83
- 4.3.12 PCI Bus 1.0 83
- 4.3.13 IDE Controller 84
- 4.3.15 CompactPCI Bus 84
- 4.3.16 PMC Slots 84
- 4.4 Miscellaneous 86
- 4.4.3 Onboard Power Supplies 89
- 4.4.4 Hot Swap Support 89
- 4.4.5 Hot Swap Process 89
- 5.2 Block Diagram 92
- 5.4 Rear Panel Connectors 94
- 5.5.2.1 Host IO Connectors 96
- 5.5.2.2 PMC I/O Connectors 98
- 5.6 Jumper Settings 104
- 5.7 Functional Description 105
- 5.7.3 Hot-Swap Support 106
- 5.7.4 Serial EEPROM 106
- 5.7.5 PMC I/O Modules 106
- 5.7.7 PMC I/O Module 110
- 5.7.9 PMC I/O Connector 112
- 5.7.10 Host I/O Connector 112
- 5.8 Installing the PIM 113
- Figure 5-9 Installing the PIM 114
- Remote Start via the PCI Bus 117
- MOTLoad Firmware 119
- 7.4 MOTLoad Commands 120
- 7.6 MOTLoad Tests 120
- 7.7 Using MOTLoad 121
- 7.7.2 Command Line Help 122
- 7.7.3 Command Line Rules 122
- 7.8 MOTLoad Command List 123
- Memory Maps 127
- 8.2.2 Processor Memory Map 128
- 8.2.3 Default PCI Memory Map 129
- 8.2.5 System I/O Memory Map 131
- 8.2.7 CompactPCI Memory Map 131
- 8.2.9 L1, L2 and L3 Cache 132
- 8.2.10 System Memory 132
- A Related Documentation 133
- A.3 Related Specifications 134
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