Motorola CPCI-6115 Manuel de service télécharger pdf (Page 34)

CPX8216 and CPX8216T Installation and Use (6806800A52C)

Chapter 2 System Architecture

Typical Insertion and Extraction Processes

Many of the steps in the insertion and extraction processes are automated by software. After

the operator installs a board, it automatically advances to P1, see The Hot Swap Process. The

hardware connection process proceeds automatically and asserts the ENUM# signal to initiate

the software connection process. The host responds to the bussed ENUM# signal by reading

the Hot Swap Control Status Register of each board to find out which one is signaling an

insertion or extraction (INS or EXT bit asserted). Upon detecting an insertion, the host responds

by adding software drivers to support the newly inserted board.

Extraction is initiated when the operator opens the board ejector handle, which activates a

mechanical switch to assert ENUM#. The hot plug system driver senses ENUM# and notifies

software that board activity must be quiesced and that software device drivers should be

unloaded. The application that is using the board is informed that the resource is no longer

available. When the board is ready for extraction, software informs the operator by illuminating

the blue LED. After extraction, all system resources previously assigned to that board are made

available for other uses.

The Hot Swap Process

PICMG divided the complete hot swap process into physical, hardware and software

connection processes. These processes are formally broken down further into a group of

transitional states, which are illustrated in the following figure.

When a board is inserted it goes through all states from P0 to S3. Conversely, a board

transitions from S3 to P0 before being extracted. During normal operation, no states are

skipped. Extracting a board in a software connection state other than S0 is likely to disrupt

software enough to crash the system, but the CompactPCI bus, from a purely electrical point of

view, will not be disrupted enough to cause logic levels to be violated.

Certain states are overlapping. For example, when the board is fully seated (completed P1), but

has not yet started the hardware connection process (H0), it said to be in the P1/H0 state.

Similarly, a board can also be in the H2/S0 state.

4288 0504

Physical

Connection States

Hardware

Connection States

Software

Connection States

P0 P1

H0 H1

H1F S0 S1 S2 S3

S2Q S3Q

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Motorola CPCI-6115 Manuel de service Page 34