Motorola CPCI-6115 Manuel de service Page 167

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Memory Maps and Addresses
CPCI-6200 Installation and Use (6806800J66C)
167
WDG_COUNT–Count; These bits define the watchdog timer count value. When the watchdog
counter is enabled or there is a write to the load register, the watchdog counter is set to the
count value. When enabled, the watchdog counter will decrement at a rate defined by the
resolution register. The counter will continue to decrement until it reaches zero or the software
writes to the load register. If the counter reaches zero, a system or board level reset is
generated.
7.4.23 PLD Revision Register
This register may be read by the system software to determine the current revision of the
timers/registers PLD.
Table 7-47 PLD Revision Register, 0xF200_0030
Bit Field Operation Reset
7MAJOR_REVR XX
6
5
4MINOR_REVR XX
3
2
1
0
Table 7-48 PLD Revision Register Field Definition
MAJOR_REV PLD's Major Revision Bits. It starts from 00.
MINOR_REV PLD's Minor Revision Bits. It starts with 01.
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