Motorola CPCI-6115 Manuel de service Page 174

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Memory Maps and Addresses
CPCI-6200 Installation and Use (6806800J66C)
174
The following figure shows how PCI interrupts are mapped to processor interrupts.
7.6 I
2
C Device Addresses
A two-wire serial interface for the CPCI-6200 is provided by an I
2
C compatible serial controller
integrated into the MPC8572. The MPC8572 I
2
C controller is used by the system software to
read the contents of the various I
2
C devices located on the CPCI-6200.
Figure 7-2 PCI Interrupt Mapping to Processor
Primary
INTA_N
INTB_N
INTC_N
INTD_N
Secondary
INTA_N
INTB_N
INTC_N
INTD_N
Primary
INTA_N
INTB_N
INTC_N
INTD_N
Secondary
INTA_N
INTB_N
INTC_N
INTD_N
CPCI
INTA_N
INTB_N
INTC_N
INTD_N
INTA_N
INTB_N
INTC_N
8572
(Processor)
INTA_N
INTB_N
INTC_N
INTD_N
Tsi384 (PCI 1)
Tsi384 (PCI 2)
Tsi384 (PCI 3)
Tsi381 (PCI 4)
INTA_N
INTB_N
INTC_N
INTD_N
PEX8624
Port 5Port 6Port 8Port 9
IRQ0_N
IRQ1_N
IRQ2_N
IRQ3_N
PMC1
PMC2
CPCI CPLD
USB CONT.
INT A_ N
INT B_ N
INT C_N
INT D_N
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