Motorola CPCI-6115 Manuel de service Page 75
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Functional Description
CPCI-6200 Installation and Use (6806800J66C)
75
DDR3 memory is implemented using external SO-UDIMM, unbuffered, ECC-supported
modules.
4.5 Timers
The timing functions are provided by eight 32-bit timers that are integrated into the processor.
These timers are clocked by the real-time clock (RTC) input, which is driven by a 1 MHz clock.
There are also four independent 32-bit timers in a programmable logic device (PLD). The clock
source for the four 32-bit timers in the PLD is derived from 25 MHz. The timer prescaler register
must be configured to generate the desired timer reference (default is 1 MHz).
4.6 Ethernet Interfaces
This board provides four 10/100/1000 full duplex Ethernet interfaces using the MPC8572
integrated Ethernet controllers. Two Broadcom BCM5482S PHYs are used. The Ethernet ports
on the processor are configured to operate in reduced Gigabit media independence interface
(RGMII) mode. Two Gigabit Ethernet interfaces are routed to the RJ-45 connectors on the face
plate. These connectors have integrated LEDs. The other two Gigabit Ethernet interfaces are
routed to J3 for rear I/O.
4.7 Local Bus Interface
This board uses the processor's local bus controller (LBC) for access to onboard flash memory
and I/O registers. The LBC has programmable timing modes to support devices of different
access times, as well as device widths of 8, 16, and 32 bits. The CPCI-6200 uses the LBC in
general purpose chip select machine (GPCM) mode to interface to two physical banks of
onboard flash, MRAM, and onboard 32-bit timers, along with control and status registers.
4.7.1 Flash Memory
This board provides 128 MB of soldered NOR flash memory. Two AMD Spansion MirrorBit 3.0 V
devices are configured to operate in 16-bit mode to form a 32-bit flash bank. This flash bank is
connected to LBC Chip Select 0, and it also acts as the boot bank.
CPCI-6200 also includes a second NAND flash bank that is connected to LBC Chip Select 1. This
bank can be up to 16 GB. However, only 4 and 8 GB are supported at this time.
- CPCI-6200 1
- Trademarks 2
- Contact Address 2
- Contents 3
- List of Tables 10
- List of Figures 13
- About this Manual 15
- Conventions 18
- Summary of Changes 19
- Introduction 21
- 1.2 Standard Compliances 24
- 1.3 Mechanical Data 26
- 1.4 Ordering Information 26
- 1.5 Product Identification 27
- Chapter 2 29
- 2.1 Overview 29
- 2.4 Power Requirements 31
- 2.5 Installing Accessories 32
- PMC Filler Plate 33
- PMC Alignment 33
- Voltage Key 33
- 2.6.3 Hardware Configuration 35
- 2.10 Factory-Installed Linux 42
- Chapter 3 45
- 3.1 Board Layout 45
- 3.2 Front Panel 46
- 3.3 Connectors and Headers 47
- 3.3.1 CPCI Bus Connector, J1 48
- 3.3.2 CPCI Bus Connector, J2 49
- 3.3.4 CPCI Connector, J4 51
- 3.3.7 Ethernet Connector 58
- 3.3.8 USB Connector 58
- 3.4 Switches 66
- 3.5 Front Panel LEDs 67
- 3.6 Status Indicators 68
- Functional Description 71
- 4.4 System Memory 74
- 4.5 Timers 75
- 4.6 Ethernet Interfaces 75
- 4.7 Local Bus Interface 75
- 4.7.3 Control and Timers PLD 77
- 4.8 DUART Interface 78
- 4.9 PCI Express Port 79
- 4.10 PCI/PCI-X Bus 80
- 4.11 Operation Modes 81
- 4.11.1 System Controller Mode 82
- 4.11.2 Peripheral Mode 82
- 4.11.3 Stand Alone Mode 83
- 4.12 PCI Express Expansion 84
- 4.13 System Interrupts 85
- 4.14 Clock Distribution 86
- 4.15 MPC8572 System Clock 87
- 4.16 Reset Control Logic 87
- 4.16.1 Abort/Reset Switch 89
- 4.16.2 Reset Timing 90
- 4.17 RTC Battery 91
- 4.18 IPMI Controller 91
- 4.19 Programmable Devices 93
- 4.19.1 Local Bus Control CPLD 94
- 4.19.2 Reset CPLD 94
- 4.19.3 CPCI Control CPLD 94
- 5.4 MOTLoad Commands 96
- 5.6 MOTLoad Tests 96
- 5.7 Using MOTLoad 97
- 5.7.2 Command Line Help 99
- 5.7.3 Command Line Rules 99
- 5.8 MOTLoad Command List 100
- MOTLoad Firmware 101
- Control via IPMI 107
- 6.1.3 IPMI Messaging Commands 108
- 6.1.4 SEL Device Commands 108
- 6.1.5 SDR Repository Commands 109
- 6.1.6 FRU Inventory Commands 109
- 6.1.7 Sensor Device Commands 110
- 6.2 PICMG 2.9 Commands 111
- 6.3 Emerson Specific Commands 112
- 6.3.2 OEM Commands 115
- 6.3.2.1 BMC/PM Change Role 116
- 6.4 FRU Information 118
- 6.5 Sensor Description 118
- Memory Maps and Addresses 137
- 7.2 CPCI-6200 Memory Map 138
- 7.4 System I/O Memory Map 140
- 7.4.1 System Status Register 143
- 7.4.2 System Control Register 144
- 7.4.5 Interrupt Register 1 148
- 7.4.6 Interrupt Register 2 149
- 7.4.7 Interrupt Mask Register 150
- 7.4.23 PLD Revision Register 167
- 7.4.24 PLD Date Code Register 168
- 7.4.25 Test Register 1 168
- 7.4.26 Test Register 2 169
- 7.4.27.2 Control Registers 170
- 7.4.27.3 Compare Registers 171
- 7.4.27.4 Counter Registers 172
- 7.5 Interrupt Controller 173
- C Device Addresses 174
- 7.7 PCI/PCI-X Configuration 175
- Replacing the Battery 179
- A.2 Replacing the Battery 180
- Related Documentation 181
- B.3 Related Specifications 183
- Safety Notes 185
- Installation 186
- Operation 187
- Hot Swap 188
- Sicherheitshinweise 189
- System Installation 191
- Batterie 192
- © 2009 Emerson Electric Co 196
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