Motorola CPCI-6115 Manuel de service Page 80

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Functional Description
CPCI-6200 Installation and Use (6806800J66C)
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4.10 PCI/PCI-X Bus
Four separate PCI/PCI-X bus segments are implemented. These segments are connected to the
processor through PCI Express bridges and a PCI Express switch.
PCI-X bus 1 and PCI-X bus 2 connect to PMC site 1 and PMC site 2, respectively, using a Tsi384
bridge. Both buses are configured dynamically to operate in 25/33/66 MHz PCI or
100/133 MHz PCI-X mode depending on the PMC installed.
PCI bus 3 connects to the PCI bridge (PCI6466) using a Tsi384 bridge and is configured for
66 MHz PCI mode.
PCI bus 4 connects to the USB controller using a Tsi381 bridge and is configured for 33 MHz PCI
mode.
4.10.1 PCI Mezzanine Card Sites (PCI-X Bus 1 and 2)
This board provides two PMC sites that support standard PMCs or PrPMCs. Each PMC site has a
separate PCI Express to PCI-X bridge.
The PMC connectors are placed to support two single-width PMCs or one double-width PMC.
Both PMC sites 1 and 2 support front PMC I/O and rear PMC I/O via the J3/J5 connectors. PMC
1 I/O is routed to the J3 connector while PMC 2 I/O is routed to J5 connector.
Only 3.3 V I/O PMC modules are supported.
4.10.2 PCI 6466 Universal Bridge (PCI Bus 3)
The Compact PCI interface for CPCI-6200 is provided by the PLX PCI6466 universal bridge.
The PCI6466 can operate in transparent and non-transparent mode, allowing CPCI-6200 to
operate in the system slot or peripheral slot of a chassis. The primary side PCI bus operates with
64-bit, 66 MHz with PCI Express to PCI-X bridge. The secondary side (CPCI bus) can operate at
32-bit/33 MHz and 32—64 bit/66 MHz depending on the system configuration.
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