CPCI-6200 Installation and Use (6806800J66C)
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4.16.2 Reset Timing
Different devices have different reset timing requirements. CPCI-6200 uses a Reset Control PLD
to meet their requirements.
Table 4-5 Reset Timing Requirements
Device Reset Signal Source of Reset
Minimum Reset
Time
Actual Reset
Time
8572 CPU_HRESET_N
1
Reset CPLD 100 μs260μs
SRESET_N
2
Reset CPLD 45 ns
PEX8624
1
HRESET_N Reset CPLD 100 μs125μs
Ts i38 4
1
HRESET_N Reset CPLD 1 μs125μs
Ts i38 4
1
HRESET_N Reset CPLD 1 μs125μs
Ts i38 4
1
HRESET_N Reset CPLD 1 μs125μs
Ts i38 4
1
HRESET_N Reset CPLD 1 μs125μs
5482, PHY_1
1
HRESET_N Reset CPLD 2 μs125μs
5482, PHY_2
1
HRESET_N Reset CPLD 2 μs125μs
CPCI CPLD
1
HRESET_N Reset CPLD 1 μs125μs
SMUX CPLD
1
HRESET_N Reset CPLD 1 μs125μs
LBPC CPLD
1
HRESET_N Reset CPLD 1 μs125μs
Reset CPLD 5V_PGOOD MAX811M 200 ms
3.3V_PGOOD MAX811S 225 ms
LT1646, HSC HSC_RST_REQ_N Reset CPLD
PCI-E Conn
1
HRESET_N Reset CPLD 125 μs
TL16C2550
1
HRESET Reset CPLD 1 μs125μs
JTAG Router 3.3V_PGOOD MAX811S 225 ms
PCI6466 P_PB_RST_N Reset CPLD 1.35 ms
S_PB_RST_N Reset CPLD 1.35 ms
PMC_1
2
PCI1_RST_N Tsi384_1 1 ms 1.35 ms
PMC_2
3
PCI2_RST_N Tsi384_2 1 ms 1.35 ms
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