Motorola T1/E1 Spécifications

1 of 122 REV: 121707 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple

DS26503 T1/E1/J1 BITS Element 10 of 122 Table 2-2. E1-Related Telecommunications Specifications ITUT G.703 Physical/Electrical Characteristics of G.

DS26503 T1/E1/J1 BITS Element Figure 16-2. TAP Controller State Diagram 1001111111111110000010000110000SelectDR-ScanCapture DRShi

DS26503 T1/E1/J1 BITS Element INSTRUCTION INSTRUCTION CODES 16.1 Instruction Register The instruction register contains a shift register as well as

DS26503 T1/E1/J1 BITS Element Table 16-2IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test

DS26503 T1/E1/J1 BITS Element Table 16-4. Boundary Scan Control Bits CELL # NAME TYPE CONTROL CELL 0 AD1 Output3 1 1 AD1_7_CTRL Controlr 2 AD0 Ou

DS26503 T1/E1/J1 BITS Element CELL # NAME TYPE CONTROL CELL 29 TNEGO observe_only TCLKO observe_only 31 TCLK observe_only 32 ALE_A7 observe_only

DS26503 T1/E1/J1 BITS Element Figure 17-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 17. FUNCTIONAL TIMING DIAGRAMS 17.1 Processor Inter

DS26503 T1/E1/J1 BITS Element Figure 17-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 SCK CS 1 A7 0 0 0 0 0 0 D7 D6 D5 D4

DS26503 T1/E1/J1 BITS Element Figure 17-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 0 0 LSB MSB MOSI MISO D7 D6 D5 D4 D3 D2 D

DS26503 T1/E1/J1 BITS Element 108 of 122 18. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………

DS26503 T1/E1/J1 BITS Element 109 of 122 Table 18-5. DC Characteristics (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26503L; VDD = 3.3V ±5%, TA = -40°C

DS26503 T1/E1/J1 BITS Element 11 of 122 3. BLOCK DIAGRAMS Figure 3-1. Block Diagram RX LIURX LIUT1/E1 SSM FRAMERCLOCK- DATATX LIUT1/E1 SSMFORMATTE

DS26503 T1/E1/J1 BITS Element (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26503L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26503LN.) (Note 1, Figure 19

DS26503 T1/E1/J1 BITS Element Figure 19-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00) ASHPWtCYCtASDtASDPWPWEHELttttttAHLCHCSASLASEDCSAD0

DS26503 T1/E1/J1 BITS Element 112 of 122 Figure 19-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00) t ASD ASHPW t t ASL AHLtCSt ASL ttt DSWDHW t CH

DS26503 T1/E1/J1 BITS Element 113 of 122 19.2 Nonmultiplexed Bus Table 19-2. AC Characteristics, Non-Mux Parallel Port (VDD = 3.3V ±5%, TA = 0°C to

DS26503 T1/E1/J1 BITS Element Figure 19-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01) Address Valid Data Valid A0 to A7 D0 to D7

DS26503 T1/E1/J1 BITS Element Figure 19-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01) Address Valid Data Valid A0 to A7 D0 to

DS26503 T1/E1/J1 BITS Element Figure 19-819.3 Serial Bus Table 19-3. AC Characteristics, Serial Bus (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26503L

DS26503 T1/E1/J1 BITS Element Figure 19-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 MSB LSBBITS 6-1SLAVE MSB SLAVE LSBBITS

DS26503 T1/E1/J1 BITS Element Table 19-4. Receive Side AC Characteristics Figure 19-1019.4 Receive Side AC Characteristics (VDD = 3.3V ±5%, TA = 0°

DS26503 T1/E1/J1 BITS Element Figure 19-1119.5 Transmit Side AC Characteristics Table 19-5. Transmit Side AC Characteristics (VDD = 3.3V ±5%, TA =

DS26503 T1/E1/J1 BITS Element 12 of 122 Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) FROM RXLIUTO TXLIUCLOCK+ DATA- D

DS26503 T1/E1/J1 BITS Element Figure 19-11. Transmit Timing, T1/E1 TSERTS_8K_41tD2tHDtSUTS_8K_42tSUtFtRTCLKttCLtCHCPTX CLOCK3PLL_OUTtD3RCLK, JA CLO

DS26503 T1/E1/J1 BITS Element 121 of 122 20. REVISION HISTORY REVISION DESCRIPTION 070904 New product release. 032405 Updated Table 2-1 and Table 2

DS26503 T1/E1/J1 BITS Element 122 of 122 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entir

DS26503 T1/E1/J1 BITS Element 13 of 122 Figure 3-4. Master Clock PLL Diagram

DS26503 T1/E1/J1 BITS Element 14 of 122 4. PIN FUNCTION DESCRIPTION 4.1 Transmit PLL NAME TYPE FUNCTION PLL_OUT O Transmit PLL Output. This pin c

DS26503 T1/E1/J1 BITS Element 15 of 122 4.3 Receive Side NAME TYPE FUNCTION RCLK O Receive Clock. Recovered 1.544MHz (T1), 2.048MHz (E1), or 6312kH

DS26503 T1/E1/J1 BITS Element 16 of 122 4.4 Controller Interface NAME TYPE FUNCTION INT/ JACKS0 I/O Active-Low Interrupt/Jitter Attenuator Clock S

DS26503 T1/E1/J1 BITS Element 17 of 122 NAME TYPE FUNCTION AD[5]/ RMODE1 I/O Data Bus D[5] or Address/Data Bus AD[5]/Receive Framing Mode Select Bi

DS26503 T1/E1/J1 BITS Element 18 of 122 NAME TYPE FUNCTION AD[1]/ RMODE3/ MOSI I/O Data Bus D[1] or Address/Data Bus AD[1]/Receive Mode Select 3/Ma

DS26503 T1/E1/J1 BITS Element 19 of 122 NAME TYPE FUNCTION A4/CPHA/ L2 I Address Bus Bit A[4]/Serial Port Clock Phase Select/Line Build-Out Select

DS26503 T1/E1/J1 BITS Element TABLE OF CONTENTS 1. FEATURES ...

DS26503 T1/E1/J1 BITS Element 20 of 122 NAME TYPE FUNCTION BTS/HBE I Bus Type Select/Transmit and Receive B8ZS/HDB3 Enable BTS: Strap high to selec

DS26503 T1/E1/J1 BITS Element 21 of 122 4.5 JTAG NAME TYPE FUNCTION JTCLK I JTAG Clock. This clock input is typically a low frequency (less than 10

DS26503 T1/E1/J1 BITS Element 22 of 122 4.7 Power NAME TYPE FUNCTION DVDD — Digital Positive Supply. 3.3V ±5%. Should be tied to the RVDD and TVDD

DS26503 T1/E1/J1 BITS Element 23 of 122 5. PINOUT Table 5-1. LQFP Pinout MODE PIN TYPE PARALLEL PORT SERIAL PORT HARDWARE FUNCTION 1 I/O AD2 SCL

DS26503 T1/E1/J1 BITS Element 24 of 122 MODE PIN TYPE PARALLEL PORT SERIAL PORT HARDWARE FUNCTION 18 O TCLKO TCLKO TCLKO Transmit Clock Output 1

DS26503 T1/E1/J1 BITS Element 25 of 122 MODE PIN TYPE PARALLEL PORT SERIAL PORT HARDWARE FUNCTION 60 I CS CS RLB Parallel Port Mode: Active-Low Chi

DS26503 T1/E1/J1 BITS Element 26 of 122 6. HARDWARE CONTROLLER INTERFACE In Hardware Controller mode, the parallel and serial port pins are reconfi

DS26503 T1/E1/J1 BITS Element 27 of 122 6.3 Line Build-Out Table 6-3. E1 Line Build-Out L2 PIN 13 L1 PIN 12 L0 PIN 11 APPLICATION N (NOTE 1) RETURN

DS26503 T1/E1/J1 BITS Element 28 of 122 6.5 Transmitter Operating Modes Table 6-6.Transmit Path Operating Mode TMODE3 PIN 62 TMODE2 PIN 48 TMODE1 P

DS26503 T1/E1/J1 BITS Element 29 of 122 Table 6-8. MCLK Pre-Scaler for E1 Mode MPS1 PIN 16 MPS0 PIN 15 JACKS0 PIN 46 MCLK (MHz) 0 0 0 2.048 0 0 1 Re

DS26503 T1/E1/J1 BITS Element 3 of 122 9. E1 FRAMER/FORMATTER CONTROL REGISTERS ...46

DS26503 T1/E1/J1 BITS Element 30 of 122 7. PROCESSOR INTERFACE The DS26503 is controlled via a nonmultiplexed (BIS[1:0] = 01) or a multiplexed (BIS[

DS26503 T1/E1/J1 BITS Element 31 of 122 are terminated when CS is removed. If CS is removed before all 8 bits of the data are read, the remaining da

DS26503 T1/E1/J1 BITS Element 32 of 122 7.3 Register Map Table 7-2. Register Map Sorted By Address ADDRESS TYPE REGISTER NAME REGISTER ABBREVIATION

DS26503 T1/E1/J1 BITS Element 33 of 122 ADDRESS TYPE REGISTER NAME REGISTER ABBREVIATION 44 R/W Transmit Remote Alarm Bits TRA 45 R/W Transmit

DS26503 T1/E1/J1 BITS Element 34 of 122 7.3.1 Power-Up Sequence The DS26503 contains an on-chip power-up reset function, which automatically clears

DS26503 T1/E1/J1 BITS Element 35 of 122 7.3.3 Mode Configuration Register Register Name: MCREG Register Description: Mode Configuration Register Re

DS26503 T1/E1/J1 BITS Element 36 of 122 Bits 4 to 7: Transmit Mode Configuration (TMODE[3:0]). Used to select the operating mode of the transmit pat

DS26503 T1/E1/J1 BITS Element 37 of 122 Register Name: TPCR Register Description: Transmit PLL Control Register Register Address: 09h Bit # 7 6

DS26503 T1/E1/J1 BITS Element 38 of 122 7.4 Interrupt Handling Various alarms, conditions, and events in the DS26503 can cause interrupts. For simpl

DS26503 T1/E1/J1 BITS Element 39 of 122 7.6 Information Registers Information registers operate the same as status registers except they cannot caus

DS26503 T1/E1/J1 BITS Element 4 of 122 19.2 NONMULTIPLEXED BUS...

DS26503 T1/E1/J1 BITS Element 40 of 122 8. T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS26503 is configured via a set of fiv

DS26503 T1/E1/J1 BITS Element 41 of 122 Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6

DS26503 T1/E1/J1 BITS Element 42 of 122 Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7

DS26503 T1/E1/J1 BITS Element 43 of 122 Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7

DS26503 T1/E1/J1 BITS Element 44 of 122 Register Name: T1CCR Register Description: T1 Common Control Register Register Address: 07h Bit # 7 6 5

DS26503 T1/E1/J1 BITS Element 45 of 122 Table 8-1. T1 Alarm Criteria ALARM SET CRITERIA CLEAR CRITERIA Blue Alarm (AIS) (Note 1) Over a 3ms windo

DS26503 T1/E1/J1 BITS Element 46 of 122 9. E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS26503 is configured via a set of two

DS26503 T1/E1/J1 BITS Element 47 of 122 Table 9-1. E1 Sync/Resync Criteria FRAME OR MULTIFRAME LEVEL SYNC CRITERIA RESYNC CRITERIA ITU SPEC. FAS

DS26503 T1/E1/J1 BITS Element 48 of 122 9.2 E1 Information Registers Register Name: INFO2 Register Description: Information Register 2 Register Ad

DS26503 T1/E1/J1 BITS Element 49 of 122 Table 9-2. E1 Alarm Criteria ALARM SET CRITERIA CLEAR CRITERIA ITU SPEC. RLOF An RLOF condition exists on

DS26503 T1/E1/J1 BITS Element 5 of 122 LIST OF FIGURES Figure 3-1. Block Diagram...

DS26503 T1/E1/J1 BITS Element 50 of 122 Register Name: SR2 Register Description: Status Register 2 Register Address: 16h Bit # 7 6 5 4 3 2 1 0 Na

DS26503 T1/E1/J1 BITS Element 51 of 122 Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 17h Bit # 7 6 5 4 3

DS26503 T1/E1/J1 BITS Element 52 of 122 10. I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configuration Register 1

DS26503 T1/E1/J1 BITS Element 53 of 122 Table 10-1. TS Pin Functions TRANSMIT MODE IOCR.3 IOCR.2 IOCR.1 TS FUNCTION T1/E1 0 0 0 Frame sync input T

DS26503 T1/E1/J1 BITS Element 54 of 122 Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 5

DS26503 T1/E1/J1 BITS Element 11. T1 SYNCHRONIZATION STATUS MESSAGE The DS26503 has a BOC controller to handle SSM services in T1 mode. Table 11-1.

DS26503 T1/E1/J1 BITS Element 11.3 Receive BOC The receive BOC function is enabled by setting BOCC.4 = 1. The RFDL register will now operate as the r

DS26503 T1/E1/J1 BITS Element Register Name: BOCC Register Description: BOC Control Register Register Address: 1Fh Bit # 7 6 5 4 3 2 1 0 Name — —

DS26503 T1/E1/J1 BITS Element Register Name: RFDL (RFDL register bit usage when BOCC.4 = 1) Register Description: Receive FDL Register Register Add

DS26503 T1/E1/J1 BITS Element Register Name: SR3 Register Description: Status Register 3 Register Address: 18h Bit # 7 6 5 4 3 2 1 0 Name RAI

DS26503 T1/E1/J1 BITS Element 6 of 122 LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications...

DS26503 T1/E1/J1 BITS Element Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 19h Bit # 7 6 5 4 3 2 1 0 Nam

DS26503 T1/E1/J1 BITS Element Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ah Bit # 7 6 5 4 3 2 1 0 Name — RSA1 R

DS26503 T1/E1/J1 BITS Element Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Bh Bit # 7 6 5 4 3 2 1 0 Name

DS26503 T1/E1/J1 BITS Element Register Name: TFDL Register Description: Transmit FDL Register Register Address: 51h Bit # 7 6 5 4 3 2 1 0 Name T

DS26503 T1/E1/J1 BITS Element 12. E1 SYNCHRONIZATION STATUS MESSAGE The DS26503 provides access to both the transmit and receive Sa/Si bits. In E1,

DS26503 T1/E1/J1 BITS Element Register Name: RSiAF Register Description: Receive Si Bits of the Align Frame Register Address: 58h Bit # 7 6 5 4 3

DS26503 T1/E1/J1 BITS Element Register Name: RRA Register Description: Receive Remote Alarm Register Address: 5Ah Bit # 7 5 4 3 2 1 0 Name RRAF

DS26503 T1/E1/J1 BITS Element Register Name: RSa5 Register Description: Receive Sa5 Bits Register Address: 5Ch Bit # 7 6 5 4 3 2 1 0 Name RSa5F

DS26503 T1/E1/J1 BITS Element Register Name: RSa7 Register Description: Receive Sa7 Bits Register Address: 5Eh Bit # 7 6 5 4 3 2 1 0 Name RSa7F

DS26503 T1/E1/J1 BITS Element Register Name: TSiAF Register Description: Transmit Si Bits of the Align Frame Register Address: 42h Bit # 7 6 5 4 3

DS26503 T1/E1/J1 BITS Element 7 of 122 1. FEATURES 1.1 General  64-pin, 10mm x 10mm LQFP package  3.3V supply with 5V-tolerant inputs and outputs

DS26503 T1/E1/J1 BITS Element 2 1 TRAF1 Register Name: TRA Register Description: Transmit Remote Alarm Register Address: 44h Bit # 7 6 5 4 3 0 Na

DS26503 T1/E1/J1 BITS Element Register Name: TSa5F9 TSa5 Register Description: Transmit Sa5 Bits Register Address: 46h Bit # 7 6 5 4 3 2 1 0 Name

DS26503 T1/E1/J1 BITS Element TSa7F3 Register Name: TSa7 Register Description: Transmit Sa7 Bits Register Address: 48h Bit # 7 6 5 4 3 2 1 0 Name

DS26503 T1/E1/J1 BITS Element Sa7 Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address: 4Ah Bit # 7 6 5 4

DS26503 T1/E1/J1 BITS Element 3 FAS6 12.2 Alternate Sa/Si Bit Access Based on Double-Frame On the receive side, the RAF and RNAF registers will alwa

DS26503 T1/E1/J1 BITS Element Register Address: 5 Sa7 Register Name: RNAF Register Description: Receive Non-Align Frame Register 57h Bit # 7 6 4

DS26503 T1/E1/J1 BITS Element Register Name: TNAF Register Description: Transmit Non-Align Frame Register Register Address: 41h Bit # 7 6 5 4 3 2

DS26503 T1/E1/J1 BITS Element Figure 13-113. LINE INTERFACE UNIT (LIU) The LIU in the DS26503 contains three sections: the receiver, which handles c

DS26503 T1/E1/J1 BITS Element Figure 13-413.1 LIU Operation The LIU interfaces the T1, E1, and 6312kHz signals to the various types of network media

DS26503 T1/E1/J1 BITS Element 13.2.2 Receive G.703 Section 10 Synchronization Signal The DS26503 can receive a 2.048MHz square-wave synchronization

DS26503 T1/E1/J1 BITS Element 8 of 122 1.4 Framer/Formatter  Full receive and transmit path transparency  T1 framing formats include D4 and ESF 

DS26503 T1/E1/J1 BITS Element 80 of 122 The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain mode, t

DS26503 T1/E1/J1 BITS Element the incoming jitter exceeds either 120 UIP-P (buffer depth is 128 bits) or 28 UIP-P (buffer depth is 32 bits), then the

DS26503 T1/E1/J1 BITS Element 82 of 122 13.7 LIU Control Registers Register Name: LIC1 Register Description: Line Interface Control 1 Register Add

DS26503 T1/E1/J1 BITS Element T1 Mode L2 L1 L0 APPLICATION N (NOTE 1) RETURN LOSS Rt (NOTE 1) 0 0 0 DSX-1 (0 to 133 feet)/0dB CSU 1:2 N.M.

DS26503 T1/E1/J1 BITS Element Register Address: Bit # Register Name: LIC2 Register Description: Line Interface Control 2 31h 7 6 5 4 3 2 1 0 Name J

DS26503 T1/E1/J1 BITS Element Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 32h Bit # 7 6 5 4 3 2 1 0 Name C

DS26503 T1/E1/J1 BITS Element Bit # Register Name: LIC4 Register Description: Line Interface Control 4 Register Address: 33h 7 6 5 4 3 2 1 0 Name M

DS26503 T1/E1/J1 BITS Element INFO1 Register Name: Register Description: Information Register 1 Register Address: 11h Bit # 7 6 5 4 3 2 1 0 Name —

DS26503 T1/E1/J1 BITS Element 88 of 122 Register Name: SR1 Register Description: Status Register 1 Register Address: 14h Bit # 7 6 5 4 3 2 1 0 Na

DS26503 T1/E1/J1 BITS Element Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 15h Bit # 7 6 5 4 3 2 1 0 Name

DS26503 T1/E1/J1 BITS Element 9 of 122 2. SPECIFICATIONS COMPLIANCE The DS26503 meets all applicable sections of the latest telecommunications speci

DS26503 T1/E1/J1 BITS Element 90 of 122 13.8 Recommended Circuits Figure 13-4. Software-Selected Termination, Metallic Protection

DS26503 T1/E1/J1 BITS Element 91 of 122 Figure 13-5. Software-Selected Termination, Longitudinal Protection Table 13-2.

DS26503 T1/E1/J1 BITS Element Figure 13-6. E1 Transmit Pulse Template 0-0.1-0.20.10.20.30.40.50.60.70.80.91.01.11.20TIME (ns)SCAL

DS26503 T1/E1/J1 BITS Element Figure 13-8. Jitter Tolerance (T1 Mode) UNIT INTERVALS (UIpp) FREQUENCY (Hz)1K 100 10 1 0.1 10 100

DS26503 T1/E1/J1 BITS Element Figure 13-10. Jitter Attenuation (T1 Mode) Figure 13-11. Jitter Attenuation (E1 Mode) FREQUE

DS26503 T1/E1/J1 BITS Element 14. LOOPBACK CONFIGURATION Register Name: LBCR Register Description: Loopback Control Register Register Address: 20h

DS26503 T1/E1/J1 BITS Element 96 of 122 15. 6312kHz SYNCHRONIZATION INTERFACE The DS26503 has a 6312kHz Synchronization Interface mode of operation

DS26503 T1/E1/J1 BITS Element Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and

DS26503 T1/E1/J1 BITS Element Figure 16-2TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level a

DS26503 T1/E1/J1 BITS Element Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during th