Motorola ColdFire MCF5281 Manuel d'utilisateur

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This document identifies implementation differences between the MCF5281/82 processors and the description
contained in the MCF5282 ColdFire
®
Reference Manual. Refer to http://www.freescale.com/coldfire for the latest
updates.
All current MCF5281/82 devices are marked as L95M mask set. The date code on the marking can be used to
determine which errata have been corrected on a particular device as shown in Table 1. The datecode format is
XXXYYWW, where YY represents the year and WW represents the work week. The three leading digits can be
ignored.
Table 1. Summary of MCF5281/82 Errata
Errata Module Affected Date Errata
Added
Date Code Affected?
<XXX0324 XXX0324 to
XXX0326
>XXX0326
SECF035 PLL 3/18/03 Yes No No
SECF003 BDM 3/28/03 Yes Yes Yes
SECF002 EMAC 3/28/03 Yes Yes No
SECF021 Cache 3/31/03 Yes Yes No
SECF004 Flash 4/09/03 Yes Yes No
SECF005 Cache 7/21/03 Yes Yes Yes
SECF001 Cache 7/21/03 Yes Yes Yes
SECF029 FlexCAN 7/23/03 Yes Yes Yes
SECF009 FEC 4/22/04 Yes Yes Yes
SECF007 FEC 4/22/04 Yes Yes Yes
SECF036 PLL 8/23/04 Yes Yes Yes
SECF010 FEC 9/14/04 Yes Yes Yes
Table continues on the next page...
Freescale Semiconductor
MCF5282DE
Chip Errata
Rev 8, 02/2015
MCF5282 Chip Errata
Silicon Revision: All
© 2015 Freescale Semiconductor, Inc.
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Résumé du contenu

Page 1 - MCF5282 Chip Errata

This document identifies implementation differences between the MCF5281/82 processors and the descriptioncontained in the MCF5282 ColdFire® Reference

Page 2

Workaround:Do not write to the control/status word after initializing a receive MB. If a write (deactivation) isrequired to the control/status field o

Page 3 - SECF035: Leakage Current on V

Affects:PLLDescription:During a power on reset, if the CLKMOD[1:0] equals 11 (normal PLL mode with crystalreference), the PLL does not lock and the de

Page 4 - SECF021: Incorrect Cache Size

Workaround Step 2b (Select one of the step 2 options to use): Separate the contents ofthe SRAM and the flash memory into exclusive categories and use

Page 5

Document Number: MCF5282DERev. 8, 02/2015Information in this document is provided solely to enable system and software implementers to use Freescale p

Page 6

Table 1. Summary of MCF5281/82 Errata (continued)Errata Module Affected Date ErrataAddedDate Code Affected?<XXX0324 XXX0324 toXXX0326>XXX0326SEC

Page 7

SECF035: Leakage Current on VDDPLL pinErrata type:SiliconAffects:PLLDescription:The device exhibits a 65mA leakage current on the VDDPLL supply, regar

Page 8

should not experience any stall because that accumulator is not being updated. In the currentV2 + EMAC implementation, it incorrectly stalls for two c

Page 9

If a write to the CACR is performed to clear the cache (CACR[CINV] = 1) and only a partialclear is done (CACR[INVI] or CACR[INVD] set), then cache cor

Page 10

up to four lines after the end of the valid data can also be written. In most cases, this is not aproblem because the extra lines of data continue fal

Page 11

When TCP is used as a transport mechanism, this errata manifests itself as lost packets andreduced throughput. Data continues to be received correctly

Page 12

Description:A CCW table location may be corrupted by writing any other CCW or results table locationwhile any queue is active. If a CCW table or resul

Page 13 - How to Reach Us:

Workaround:Use bypass mode, by setting CLKMOD[1:0] to 00. The CLKOUT to CLKIN phase relationshipis maintained.Fix plan:Currently, there are no plans t

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