Motorola MSC8101 ADS Manuel d'utilisateur

Networking and Computing Systems Group (NCSG) Colvilles Road, Kelvin Industrial Estate, East Kilbride, Glasgow G75 OTG. 44 (0) 1355 355000. Fa

5 PFC_DDD_v1.3.doc o The JTAG file “PFCjtag21.cfg” is selected. The file listing and core JTAG numbering is detailed in Appendix C. Table 2. M

6 PFC_DDD_v1.3.doc SW3.4 ON Boot=0, Host Port disabled, Boot from external memory SW3.8 OFF RSTCONF=1, Reset Configuration Slave 4.2.2 MSC

7 PFC_DDD_v1.3.doc SW2.8 OFF JP1 Pos 1-2 Full Chain (21 cores) SW2.8 ON The JTAG configuration file for 21 cores is listed in Appendix C. 4.3

8 PFC_DDD_v1.3.doc 5 Hardware Description This section describes the Packet Telephony Farm Card Hardware. The Hardware architecture has been pa

9 PFC_DDD_v1.3.doc Table 9. MSC8101 Memory Controller Resources Chip Select Peripheral CS0 Flash (Boot) CS2 SDRAM CS3 DSI Asynchronous (Individ

10 PFC_DDD_v1.3.doc OP = 000 Normal Operation SDAM = 010 A[9:19] multiplexed to A[19:29] BSMA = 100 A17-A18 are used as Bank Selects Signals

11 PFC_DDD_v1.3.doc Step 3. Issue Precharge All command (PALL) to all banks of the device. Program PSDMR[OP] bits to [101] and then perform an ac

12 PFC_DDD_v1.3.doc A_BADDR[31] A-1 On the flash the BYTE signal is pulled down for byte mode which enables DQ[0:7] but tri-states DQ[8:14], wi

13 PFC_DDD_v1.3.doc Figure 6. PFC to DSI Interface 5.2.3.2 MSC8101 60x to DSI Interface: Asynchronous mode The DSI can be asynchronously cont

14 PFC_DDD_v1.3.doc Figure 7. Aggregator MSC8102 Interrupt Connectivity Options Figure 8. Standard Interrupt Routing MSC 8101 A_IRQ[1:7] DSP_

i PFC_DDD_v1.3.doc Revision History Revision By Date Description of Change 1.0 CM 24/1/3 First Issue 1.1 CM 7/3/3 Updated to reflect

15 PFC_DDD_v1.3.doc 5.2.5 MSC8101 FCC Interface The MSC8101 incorporates two FCC interfaces for packet transfers. The packet interfaces are con

16 PFC_DDD_v1.3.doc PD16 FCC1 Utopia II TXPRTY Pn4-31 PD17 FCC1 Utopia II RXPRTY Pn4-36 PD18 FCC1 Utopia II RXADDR4 Pn4-4 PD19 FCC1 Ut

17 PFC_DDD_v1.3.doc Table 17. HDI6 Configuration 60x signal HDI16 Signal Description Dh57 HDSP=0 Single data strobe mode Dh58 HDDS=0 Negat

18 PFC_DDD_v1.3.doc Table 18. MSC8102 PSDMR settings Register Setting Description PBI = 1 Paged Based Interleaving RFEN = 1 Refresh services

19 PFC_DDD_v1.3.doc 5.3.1.1 SDRAM Initialization Command Sequence Step 1. Apply power and start clock. Maintain No Operation (NOP) condition at

20 PFC_DDD_v1.3.doc TDM. With the P3TMC specification implemented the number of CT lines is further restricted to 20 streams. Each MSC8102 has fo

21 PFC_DDD_v1.3.doc TDM2 TDM2TDAT TDM2RDAT CT_D12 CT_D13 TDM3 TDM3TDAT TDM3RDAT CT_D18 CT_D19 MSC8102 #4 TDM0 TDM0TDAT TDM0RDAT CT_D14 CT_D15

22 PFC_DDD_v1.3.doc MR Reset In R12 R10 3V3 1V6 RESET VCC A_PORESET PORESET_M1 PORESET_FPGA MSC8101 GPIO[PA7] FLASH FPGA MSC8102 MSC8102 MSC8

23 PFC_DDD_v1.3.doc The frequency of operation will depend on the revision of silicon used and the required application. Consult Motorola Ltd for

24 PFC_DDD_v1.3.doc 5.4.3 Power The PICMG 2.15 standard currently stipulates that 5V, 3.3V and GND are provided through the PTMC connectors. The

ii PFC_DDD_v1.3.doc CONTENTS 1 OVERVIEW...

25 PFC_DDD_v1.3.doc Color MeaningNot ConnectedGroundVoltageCT (TDM) BusHost Interface SignalsGeneral Data I/O PIN SIGNAL SIGNAL PIN1NC NC23 GND N

26 PFC_DDD_v1.3.doc PIN SIGNAL SIGNAL PIN1NC NC23NC NC45NC GND67 GND NC 89HD0 HA11011 HD1 +3.3V 1213 PTMC_RESET HA2 1415 +3.3V HA3 1617 HD2 GND 1

27 PFC_DDD_v1.3.doc PIN SIGNAL SIGNAL PIN1 MII_MDIO GND 23 GND NC 45 MII_MDC NC 67RMII_RX_ER0 GND 89NCRMII_TXD01011 NC RMII_TXD1 1213 REF_CLK GND

28 PFC_DDD_v1.3.doc PIN SIGNAL SIGNAL PIN1TxSOC GND 23GNDRXADR445 TxCLAV TXADR4 67 RXADR3 GND 89I2C_SCL GND 1011 GND 5V 1213 5V GND 1415 GND RXEN

29 PFC_DDD_v1.3.doc PIN SIGNAL SIGNAL PIN1NC 1V623NC NC45NC NC67NC NC891V6 NC1011 1V6 GND 1213 NC NC 1415 NC NC 1617 NC NC 1819 GND MII2_TCLK 202

30 PFC_DDD_v1.3.doc • TDI: The input signal is pulled high to save power in low power stop mode. All JTAG ports have a weak internal TDI pull u

31 PFC_DDD_v1.3.doc SW2.4 Select DSI bus width (DSI64) ON = 32-bit OFF = 64-bit SW2.5 Select DSI Mode of Operation (DSISYNC) ON = Asynchrono

32 PFC_DDD_v1.3.doc 6 Firmware Implementation This section describes the firmware implementation on the PFC board, which includes detailed memor

33 PFC_DDD_v1.3.doc SRAM 0x0200_0000 0x0207_FFFF FLASH 0xFE00_0000 0xFE3F_FFFF IMMR 0xF000_0000 0xF001_FFFF Peripherals 0x01F0_0000 0x01F0_7FFF

34 PFC_DDD_v1.3.doc DSP Peripherals [64KB] 0x021E_0000 0x021E_FFFF IMMR 0xF000_0000 0xF000_FFFF SDRAM 0x2000_0000 0x20FF_FFFF IP Peripherals [25

iii PFC_DDD_v1.3.doc APPENDIX B PFC BASE CARD PARTS...

35 PFC_DDD_v1.3.doc 6.4 PFC Reset Configuration Word (MSC8102) The slave MSC8102s are configured to receive their reset configuration word throug

36 PFC_DDD_v1.3.doc Figure 20. PFC Bootstrap Method Yes MSC8101 reads RCW From flash IMMR=0xF000_0000 EARB=0,EBM=1 HReset =

37 PFC_DDD_v1.3.doc 7 PFC Base Card To facilitate debug and customer demonstrations the PFC base card is designed to break out a number of inter

38 PFC_DDD_v1.3.doc UTOPIA_TXD6 Pn4 37 ATMTXD6 P2 B13 UTOPIA_TXD7 Pn4 35 ATMTXD7 P2 B14 UTOPIA_RXD0 Pn4 60 ATMRXD0 P2 B15 UTOPIA_RXD1 P

39 PFC_DDD_v1.3.doc HD3 Pn2 19 HD3 P2 C18 HD4 Pn2 23 HD4 P2 C19 HD5 Pn2 25 HD5 P2 C20 HD6 Pn2 29 HD6 P2 C21 HD7 Pn2 31 HD7 P2 C22

40 PFC_DDD_v1.3.doc Table 38. Ethernet Interface PFC MSC8101 ADS Signal Connector Signal P2/J2 Connector UTOPIA_MTXADDR1 (MII_MDC) Pn3 1 F

41 PFC_DDD_v1.3.doc Appendix A PFC Parts. Board Ref. Description Manufacturer Part Number D1,D2,D3,D4,D5,D6,D10 0603 SM YELLOW LED LiteO

42 PFC_DDD_v1.3.doc U36 EEPROM FLASH 2MX16/4MX8 TSSOP 48PIN AMD AM29LV320DB120EI U37 IC DSP 332PIN BGA MOTOROLA MSC8101 U39 IC FPGA 1.8V Spa

43 PFC_DDD_v1.3.doc Appendix B PFC Base Card Parts. Board Ref. Description Manufacturer Part Number D1,D2,D3 1A Silicon Rectifier GENERAL

44 PFC_DDD_v1.3.doc Appendix C JTAG configuration file (21 cores) MSC8102SyncMSC8102 # DSP5 Core 0 1 MSC8102 # DSP5 Cor

iv PFC_DDD_v1.3.doc TABLE 36. CT BUS ...

45 PFC_DDD_v1.3.doc Appendix D PFC Layout Figure 22. PFC Layout - Top Figure 23. PFC Layout - Bottom

46 PFC_DDD_v1.3.doc MSC8102PFCUG/D Rev. 1.3

1 PFC_DDD_v1.3.doc 1 Overview 1.1 Scope This document provides user guide information and a detailed design description of the MSC8102 Packet Te

2 PFC_DDD_v1.3.doc 2 PFC Overview The Packet Telephony Farm Card is a PCI Telephony Mezzanine Card (PTMC) designed primarily as an MSC8102 upgra

3 PFC_DDD_v1.3.doc 3 PFC Feature List  PFC Platform  Digital Support for up to 672 channels  PTMC Type 3 form card for interfacing to stan

4 PFC_DDD_v1.3.doc 4 User Guide 4.1 Quick Start 1. Start the Start the Codewarrior tools and ensure that the command converter is running 2.