Motorola MSC8101 ADS Manuel d'utilisateur

AN2191/DRev. 0, 10/2001Porting the CORTEX RTOSto the MSC8101Application Note by Mihai Fecioru, Cristian Zamfirescu and Emilian Medve

6 Porting the CORTEX RTOS to the MSC8101 CORTEX Overview• EXECUTIVE—CORTEX is implemented as a runtime library to be linked with an application and d

Platform-Independent Layer CORTEX Overview 73.1.1.2 Software Interrupt ManagerThe software interrupt manager simulates an interrupt controller. The s

8 Porting the CORTEX RTOS to the MSC8101 CORTEX OverviewTwo tasks are always created on kernel startup—the Idle task (thrd_IdleThread()) and the Main

HAL—Platform-Dependent Layer CORTEX Overview 9Each segment has a memory manager assigned to it. A memory manager consists of a collection of function

10 Porting the CORTEX RTOS to the MSC8101 CORTEX Overviewcrtx_Void_t hrdi_UnregisterDispatcher(hrdi_ISRCB_t * pLisr_a);/* Initialize HISR stack frame

HAL—Platform-Dependent Layer CORTEX Overview 11crtx_Void_t * malloc(size_t Size_a);crtx_Void_t free(crtx_Void_t * Addr_a);crtx_Void_t * calloc(size_t

12 Porting the CORTEX RTOS to the MSC8101 CORTEX Overview/* Set LISR interrupt mask. This service is only alowed from hrdi_Shell() to allow proper ne

Platform Initialization Porting Details 134 Porting DetailsThis section details the porting of CORTEX-based code to the MSC8101 platform, including p

14 Porting the CORTEX RTOS to the MSC8101 Porting DetailsFigure 2. MSC8101 Interrupt TableEach entry in the interrupt table is 64 bytes wide. The t

Interrupt Management Porting Details 15• Decrementing the hrdi_NestedPtr_g variable, restoring the context of the interrupted task and returning to t

Star*Core is a trademark of Motorola, Inc.Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no

16 Porting the CORTEX RTOS to the MSC8101 Porting Details4.2.3 The LISR and HISR StacksAn extra amount of space must be allocated on the stack for ea

Interrupt Management Porting Details 17CORTEX assumes that stacks are aligned on 4-byte boundaries, and all kernel functions that allocate stack spac

18 Porting the CORTEX RTOS to the MSC8101 Porting DetailsCode Example 9. Pattern for Atomic FunctionsDI readmodifyEI write4.3 Task ManagementThe en

Task Management Porting Details 19• Saves the R6, R7, D6, D7 registers (ABI conventions) and the hrdi_Environ_g.Nested value of the current task on i

20 Porting the CORTEX RTOS to the MSC8101 Porting Details4.3.2 Stack Frame TracingSuppose that function 1 calls function 2 which calls function 3 … w

Memory Management Porting Details 214.4.2 Clock LISRThe LISR performs the following set of operations required by CORTEX:• Adjust the system time• Ru

22 Porting the CORTEX RTOS to the MSC8101 Porting DetailsThe main configuration files provided by CORTEX include:• gmake/template.cf—The template con

Building the System Porting Details 23• linking object files• linking object files with debugging support• creating libraries from object filesFor ex

24 Porting the CORTEX RTOS to the MSC8101 TestingFigure 5. CodeWarrior Project for the ‘Producer-Consumer Problem’ Test Application5 TestingCORTEX

Building the System Conclusions 257 ConclusionsThe MSC8101 is a very powerful device with several peripherals and a high-performance DSP core capable

 iii Abstract and ContentsApplication software targeted for today’s digital signal processors is becoming more complex. DSPs are now incorporated wit

26 Porting the CORTEX RTOS to the MSC8101 References• StarCore’s dual stack pointers (NSP and ESP) could not be used because CORTEX does not comply w

iv Porting the CORTEX RTOS to the MSC8101 4.3 Task Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 Introduction 11 Introduction1.1 RTOS Requirements for DSPsThe design of a StarCore SC140 real time operating system (RTOS) will support features nee

2 Porting the CORTEX RTOS to the MSC8101 MSC8101 Hardware Platform2 MSC8101 Hardware Platform2.1 General DescriptionThe Motorola MSC8101 is a versati

Features Used by the RTOS MSC8101 Hardware Platform 32.2.1.2 Address Generation UnitThe AGU is one of the execution units in the StarCore SC140 core.

4 Porting the CORTEX RTOS to the MSC8101 MSC8101 Hardware Platform• Bits[5:0]—always zero, allowing 64 bytes for each entry in the interrupt vectorTh

Features Used by the RTOS CORTEX Overview 5• Interrupt Pending Registers (IPRA, IPRB): two 16-bit read/write registers used for monitoring pending in