Motorola MSC8101 ADS Guide de l'utilisateur

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Page 1 - MSC8101 USER’S GUIDE

MSC8101 USER’S GUIDE16-Bit Digital Signal ProcessorMSC8101UG/DRevision 1, June 2001

Page 2 - 1-800-441-2447

Contentsx MSC8101 User’s Guide10.3.1 Set Up the Global MCC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1010.3.2 Se

Page 3

5-4 MSC8101 User’s GuideBalancing Between the PowerPC System and Local BusesAccess from the SC140 core to the QBus goes through a QBus switch. Since t

Page 4

Bus InteractionBalancing Between the PowerPC System and Local Buses 5-55.3 Bus InteractionThe PowerPC buses reside in the SIU portion of the MSC8101

Page 5

5-6 MSC8101 User’s GuideBalancing Between the PowerPC System and Local Busesallocated to the PowerPC system bus. User-Programmable Machine C (UPMC) co

Page 6

Bus InteractionBalancing Between the PowerPC System and Local Buses 5-7Figure 5-7. Memory Controller Machine SelectionAddresses are decoded by compar

Page 7 - Chapter 5

5-8 MSC8101 User’s GuideBalancing Between the PowerPC System and Local Buses5.3.1 DMA ControllerThe multi-channel DMA controller connects to both th

Page 8

Bus InteractionBalancing Between the PowerPC System and Local Buses 5-95.3.1.4 Bus ErrorsA non-maskable interrupt is generated and the DMA TEA Statu

Page 9

5-10 MSC8101 User’s GuideBalancing Between the PowerPC System and Local BusesFigure 5-8. SDMA Data PathsOn a path 1 access, the SDMA channel must acq

Page 10 - EOnCE/JTAG

Related ReadingBalancing Between the PowerPC System and Local Buses 5-11Registers, PDTEM and LDTEM. If an SDMA bus error occurs on a CP-related transa

Page 11 - MSC8101 User’s Guide xi

5-12 MSC8101 User’s GuideBalancing Between the PowerPC System and Local Buses

Page 12

MSC8101 User’s Guide 6-1Chapter 6DMA ChannelsThe on-device direct memory access (DMA) controller channels transport data between the various modules o

Page 13 - MSC8101 User’s Guide xiii

ContentsMSC8101 User’s Guide xiAPPENDIXES:Appendix AProgramming ReferenceA.1 Interrupt Sources and Priorities . . . . . . . . . . . . . . . . . . . .

Page 14

6-2 MSC8101 User’s GuideDMA ChannelsFigure 6-1. DMA Engine Interfaces6.1.1 Operating ModesThe DMA controller operates in two modes: Normal (dual-ac

Page 15 - MSC8101 User’s Guide xv

DMA Programming BasicsDMA Channels 6-3Figure 6-2. Normal Mode Example6.1.1.2 Flyby Mode (Single Access)Flyby mode does not require two DMA channels

Page 16

6-4 MSC8101 User’s GuideDMA Channels6.1.2.1 Memory to DMA FIFOA memory transfer to the DMA FIFO can occur from either external or internal memory. F

Page 17 - MSC8101 User’s Guide xvii

DMA Programming BasicsDMA Channels 6-56.1.2.3 Peripheral to DMA FIFOThe DMA controller transfers data from the internal peripherals HDI16 and EFCOP,

Page 18

6-6 MSC8101 User’s GuideDMA ChannelsFigure 6-6. DMA FIFO to Peripheral Transfers6.1.2.5 Memory to Peripheral, Flyby ModeFlyby transactions can be e

Page 19 - About This Book

Initializing the DMADMA Channels 6-7Figure 6-8. Peripheral to Memory, Flyby Mode Data Transfer6.2 Initializing the DMAThe DMA controller uses regis

Page 20 - Audience and Helpful Hints

6-8 MSC8101 User’s GuideDMA Channels6.2.1 DMA Channel Configuration Registers (DCHRx)Each DMA channel has a DCHCR that defines whether the channel i

Page 21 - Organization

Initializing the DMADMA Channels 6-9will not be serviced further. On the other hand, if the peripheral requires the DMA channel to terminate before th

Page 22

6-10 MSC8101 User’s GuideDMA ChannelsEach DMA channel uses buffer descriptors in the DCPRAM to point to a buffer and characterize it. The buffer descr

Page 23 - Further Reading

Initializing the DMADMA Channels 6-11The BD_ATTR bits are as follows.Some of the bit functions are straightforward: INTRPT defines whether the DMA is

Page 24

Contentsxii MSC8101 User’s Guide

Page 25 - MSC8101 Overview

6-12 MSC8101 User’s GuideDMA ChannelsAnother grouping of bits that relate to each other are the BP, TC, and GBL bits. These bits all regulate bus acti

Page 26 - 1.2 Features

Initializing the DMADMA Channels 6-136.2.8 Buffering and BurstingThe MSC8101 DMA module supports five types of buffering: simple, cyclic, chained, i

Page 27 - 1.2.5 System Interface Unit

6-14 MSC8101 User’s GuideDMA ChannelsFigure 6-9. DMA Buffer Types6.3 Using DMA Signals to Initiate and Control DMA TransfersDMA has four signal typ

Page 28 - 1.2.7 DMA Engine

DMA Programming ExamplesDMA Channels 6-15DREQ[3–4] and DACK[3–4] are multiplexed with IRQ lines on the MSC8101 pins, as shown in the external signals

Page 29

6-16 MSC8101 User’s GuideDMA Channels1. Channel 0 reads data from internal memory to the DMA FIFO. The DMA control registers for channel 0 are program

Page 30 - 1.3 Architecture

DMA Programming ExamplesDMA Channels 6-17Example 6-1. Internal Memory to External Memory, Simple Buffer;DMA0 init to input DATA to DMA Buffermove.l

Page 31 - 1.3.2 SRAM

6-18 MSC8101 User’s GuideDMA Channelsc. The buffer is a continuous cyclic buffer. The buffer size to be reloaded, BSIZE0, is written to the DMA buffer

Page 32 - Extended Core

DMA Programming ExamplesDMA Channels 6-19move.l #SIZE1,d0 ;Init transfer sizemove.l d0,M_BDSIZE1move.l #ATTR1,d0 ;Init channel 1 attribmove.l d0,M_B

Page 33 - 1.3.4 DMA Controller

6-20 MSC8101 User’s GuideDMA Channelsc. To configure channel 0 to perform 16-bit read transactions with no increment of the address and a flush of the

Page 34

DMA Programming ExamplesDMA Channels 6-21;DMA1 init to output DATA from DMA Buffermove.l #BUFF_START,d0 ;Init destination addressmove.l d0,M_BDADDR1m

Page 35

FiguresMSC8101 User’s Guide xiiiFigure 1-1. MSC8101 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8F

Page 36

6-22 MSC8101 User’s GuideDMA Channelsinitialized for any of the transfers because the code is not implementing cyclic buffers.a. The DMA buffer descri

Page 37 - 0x6 Low-Order Buffer Pointer

DMA Programming ExamplesDMA Channels 6-23 ; initialize interrupts bmclr #$00e0,sr.h ; allow all interrupt levels move.l #M_ELIRE,r7

Page 38 - MSC8101 Reference Manual

6-24 MSC8101 User’s GuideDMA Channelscore using IRQ18. Once this interrupt is triggered, the processor jumps to the appropriate interrupt vector addre

Page 39 - MSC8101 Overview 1-15

Avoiding DMA and SC140 Core ContentionsDMA Channels 6-256.5 Avoiding DMA and SC140 Core ContentionsThe DMA and the SC140 core can access internal me

Page 40 - Table 1-6. SCC Parameter RAM

6-26 MSC8101 User’s GuideDMA Channelschannel is active. The DMA can also change the BDPTR and ACTV fields. To prevent the SC140 core from conflicting

Page 41 - MSC8101 Overview 1-17

MSC8101 User’s Guide 7-1Chapter 7Interrupts and Interrupt PrioritiesThis chapter describes a step-by-step procedure for handling MSC8101 interrupts. T

Page 42 - 1-18 MSC8101 User’s Guide

7-2 MSC8101 User’s GuideInterrupts and Interrupt PrioritiesFigure 7-1. MSC8101 Interrupt Structure7.2 Programmable Interrupt Controller (PIC)The MS

Page 43 - MSC8101 Overview 1-19

Programmable Interrupt Controller (PIC)Interrupts and Interrupt Priorities 7-3 Support for software acknowledgment of all edge-triggered IRQ and NMI.

Page 44 - 1-20 MSC8101 User’s Guide

7-4 MSC8101 User’s GuideInterrupts and Interrupt Priorities7.3 Programming MSC8101 InterruptsWhen the PIC detects an IRQ on one or more of its input

Page 45

Programming MSC8101 InterruptsInterrupts and Interrupt Priorities 7-5Each register defines the interrupt trigger mode and IPL for four inputs. For eac

Page 46

Figuresxiv MSC8101 User’s GuideFigure 4-14. HDI16 UPM Write, Single Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18Figure

Page 47

7-6 MSC8101 User’s GuideInterrupts and Interrupt PrioritiesWhen the corresponding IR is configured as edge-triggered, its IP bit is set for every new

Page 48 - Centralized DSP Architecture

Programming MSC8101 InterruptsInterrupts and Interrupt Priorities 7-7Table 7-4 summarizes the routing of MSC8101 interrupts. Unless stated otherwise,

Page 49 - Serial Backplane

7-8 MSC8101 User’s GuideInterrupts and Interrupt Priorities7.4 Interrupt Programming ExamplesThis section describes how to use the PIC programming m

Page 50 - 1.5 Software Development

Interrupt Programming ExamplesInterrupts and Interrupt Priorities 7-9...;Programming the VBA register to address 0x5000move.l #$5000,vba;Initializing

Page 51 - MSC8101 Overview 1-27

7-10 MSC8101 User’s GuideInterrupts and Interrupt Prioritiesservice routines to accommodate unlimited code size. The following example illustrates a t

Page 52 - 1-28 MSC8101 User’s Guide

Interrupt Programming ExamplesInterrupts and Interrupt Priorities 7-11 rte ;;;; ---

Page 53 - Reset Configuration and Boot

7-12 MSC8101 User’s GuideInterrupts and Interrupt Priorities;; ---------------------------------------------------------------- ;;; interrupt

Page 54 - 2.1.2 Clocks

Interrupt Programming ExamplesInterrupts and Interrupt Priorities 7-13loop1 ;

Page 55

7-14 MSC8101 User’s GuideInterrupts and Interrupt Priorities ;; irq num from 0-23 nop if irq_num<16 move.l

Page 56

Interrupt Programming ExamplesInterrupts and Interrupt Priorities 7-15void SPI_InitInterrupt(){//create entry in SIC branch table:SIC_BranchTable[SIC_

Page 57

FiguresMSC8101 User’s Guide xvFigure 11-3. SPI as a Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 58

7-16 MSC8101 User’s GuideInterrupts and Interrupt PrioritiesSIC_RESV05, SIC_RESV06, SIC_RESV07, SIC_RESV08, SIC_FCC1, SIC_FCC2, SIC_FCC3, SI

Page 59 - Connected

Interrupt Programming ExamplesInterrupts and Interrupt Priorities 7-17 memcpy((void*)(VBA + 0x0c00), &PIC_Code,0x50); //clear whole SIC branch

Page 60 - Data Bus

7-18 MSC8101 User’s GuideInterrupts and Interrupt Priorities asm("nop"); asm("adda r1,r0"); //SIVEC address asm(&quo

Page 61

MSC8101 User’s Guide 8-1Chapter 8Host Interface (HDI16)The HDI16 host port is a Motorola MSC8101 DSP peripheral featuring a 16-bit-wide parallel port

Page 62

8-2 MSC8101 User’s GuideHost Interface (HDI16)As Figure 8-1 shows, the HDI16 peripheral has two register banks: Host-side register bank. Accessible o

Page 63 - BTM[0–1]/EE[4–5]

Operating in Different Data Transfer ModesHost Interface (HDI16) 8-38.1.2 DSP-Side ModelTo the SC140 core, the DSP-side registers appear as six regi

Page 64 - Host Port

8-4 MSC8101 User’s GuideHost Interface (HDI16)The Host DMA Mode Enable bit in the Host Port Control Register, HPCR[14]:DMA, defines the mode of operat

Page 65

Operating in Different Data Transfer ModesHost Interface (HDI16) 8-5 Polarity of the read/write strobes. Signals can be programmed as active high or a

Page 66

8-6 MSC8101 User’s GuideHost Interface (HDI16)Conversely, if the DSP defines the data size of the Normal mode transfer (HCR[4]:HICR=0), the DSP-side H

Page 67

Operating in Different Data Transfer ModesHost Interface (HDI16) 8-7The minimum hardware set-up necessary for using the HDI16 port in Normal mode is a

Page 68 - 2-16 MSC8101 User’s Guide

Figuresxvi MSC8101 User’s Guide

Page 69 - 2.5 Related Reading

8-8 MSC8101 User’s GuideHost Interface (HDI16)active low, read (HRD) and write (HWR) strobes by setting HPCR[3]:HDDS and clearing HPCR[6]:HDSP. Active

Page 70 - 2-18 MSC8101 User’s Guide

Operating in Different Data Transfer ModesHost Interface (HDI16) 8-9If the host (external DMA controller) defines the DMA (HCR[4]:HICR=1), the host-si

Page 71 - Chapter 3

8-10 MSC8101 User’s GuideHost Interface (HDI16)There are two ways to set up the hardware connection for DMA transfers, depending on the method of ackn

Page 72 - 3.3 Allocating Memory

Operating in Different Data Transfer ModesHost Interface (HDI16) 8-11The assembly language equate listed in Example 8-3 defines the initial register v

Page 73

8-12 MSC8101 User’s GuideHost Interface (HDI16)Example 8-4. Initializing the HDI16 Portmove.w #HPCR_ADDR,r1 ; r1 = HPCR addressmove.l #HCR_ADDR,r2 ;

Page 74

Managing Data Transfers Via Handshaking ProtocolsHost Interface (HDI16) 8-13A similar situation occurs when the host performs multiple reads from the

Page 75 - 3.5 Related Reading

8-14 MSC8101 User’s GuideHost Interface (HDI16) If HTFE is clear, the HOTX FIFO is not empty (it is either partially empty or full). If HTFE is set,

Page 76 - 3-6 MSC8101 User’s Guide

Managing Data Transfers Via Handshaking ProtocolsHost Interface (HDI16) 8-158.3.1.2 Host PollingA polling mechanism similar to that for the DSP is a

Page 77 - Memory-Mapped Devices

8-16 MSC8101 User’s GuideHost Interface (HDI16)Figure 8-4 depicts how the interrupt source status bits and the masking bits operate to generate an int

Page 78 - 4.2 External Bus Basics

Managing Data Transfers Via Handshaking ProtocolsHost Interface (HDI16) 8-17Figure 8-4. HDI16 DSP-Side Interrupt OperationExample 8-7 shows the set-u

Page 79

TablesMSC8101 User’s Guide xviiTable 1-1. MSC8101 Serial Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Page 80 - 2MB Flash

8-18 MSC8101 User’s GuideHost Interface (HDI16)Example 8-7. Receive Interrupt Set-up Code; setup HI16 registersmove.l #M_HPCR,r1 ; r1 = HPCR addre

Page 81 - 01234 0567 9EHTR8

Managing Data Transfers Via Handshaking ProtocolsHost Interface (HDI16) 8-19The host enables host requests using the Interface Control Register (ICR)

Page 82 - 01234 05678910

8-20 MSC8101 User’s GuideHost Interface (HDI16)The request signal lines from the DSP normally connect to the host’s interrupt request pins (IRQx), whi

Page 83 - Table 4-1. GPCM ORx Settings

Managing Data Transfers Via Handshaking ProtocolsHost Interface (HDI16) 8-21The details of the MSC8101 internal DMA are beyond the scope of this chapt

Page 84

8-22 MSC8101 User’s GuideHost Interface (HDI16)Example 8-9 shows the code necessary to set up a dual DMA to receive BUFF_SIZE 16-bit data elements fro

Page 85 - ACTIVATE command

Issuing Host Commands and Non-Maskable InterruptsHost Interface (HDI16) 8-23move.l #M_DCHCR1,r0 ; set DCHCR1moveu.l #INIT_DCHCR1,d0move.l d0,(r0)

Page 86 - CAS latency = 2, Last Data

8-24 MSC8101 User’s GuideHost Interface (HDI16)determine when the PIC accepts this command. The ISR must also clear the interrupt request in the PIC I

Page 87

MSC8101 User’s Guide 9-1Chapter 9Enhanced Filter Coprocessor (EFCOP)The MSC8101 EFCOP module is a general-purpose, fully programmable filter with 32-b

Page 88 - 4-12 MSC8101 User’s Guide

9-2 MSC8101 User’s GuideEnhanced Filter Coprocessor (EFCOP):The EFCOP operates in many different modes based on the settings of these control register

Page 89 - Multiplex

Specifying the Operating Modes for the FIR Filter TypeEnhanced Filter Coprocessor (EFCOP) 9-39.2 Specifying the Operating Modes for the FIR Filter T

Page 90 - 4-14 MSC8101 User’s Guide

Tablesxviii MSC8101 User’s GuideTable 8-7. Transfer Control in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5T

Page 91 - GPL2 is programmed high in a

9-4 MSC8101 User’s GuideEnhanced Filter Coprocessor (EFCOP)9.2.1 Real ModeReal mode performs FIR type filtering with real data and is selected by cl

Page 92

Specifying the Operating Modes for the FIR Filter TypeEnhanced Filter Coprocessor (EFCOP) 9-5to be from 1 to 64. For each time period, the EFCOP expec

Page 93

9-6 MSC8101 User’s GuideEnhanced Filter Coprocessor (EFCOP)9.2.3 Alternating Complex ModeAlternating Complex mode performs FIR type filtering with c

Page 94 - CSx = HCS

Specifying the Operating Modes for the FIR Filter TypeEnhanced Filter Coprocessor (EFCOP) 9-7The Data Initialization mode is selected via the FCTL[8]:

Page 95 - 4.6 Related Reading

9-8 MSC8101 User’s GuideEnhanced Filter Coprocessor (EFCOP)mode, two times the decimation ratio number of samples must be written to the FDIR (one for

Page 96 - 4-20 MSC8101 User’s Guide

Specifying the ALU ModesEnhanced Filter Coprocessor (EFCOP) 9-9Figure 9-2. IIR Filter Block DiagramMultichannel mode for the IIR filter type works ex

Page 97 - System and Local Buses

9-10 MSC8101 User’s GuideEnhanced Filter Coprocessor (EFCOP)9.4.2 Input ScalingThe Input Scaling mode affects only IIR filtering and the coefficient

Page 98 - 5.1 PowerPC System Bus

Transferring Data In and Out of the EFCOPEnhanced Filter Coprocessor (EFCOP) 9-119.5 Transferring Data In and Out of the EFCOPWhen the EFCOP is prog

Page 99 - QBus Switch

9-12 MSC8101 User’s GuideEnhanced Filter Coprocessor (EFCOP) FSTR[10]:FDOBF is set when the FDOR is full (that is, all eight of the locations are ful

Page 100 - 5.2 PowerPC Local Bus

Transferring Data In and Out of the EFCOPEnhanced Filter Coprocessor (EFCOP) 9-13d. Clear the Interrupt Trigger Mode (PEDxx) bits of the ELIRx registe

Page 101 - 5.3 Bus Interaction

About This BookMSC8101 User’s Guide xixThe MSC8101 device is the first Motorola product based on the SC140 DSP core introduced by the StarCoreTM Allia

Page 102 - Figure 5-6. Bus Architecture

9-14 MSC8101 User’s GuideEnhanced Filter Coprocessor (EFCOP)this mode when the DMA is programmed to transfer single 32-bit long samples from the FDOR

Page 103

Programming ExamplesEnhanced Filter Coprocessor (EFCOP) 9-15resolution and that memory is addressed in one byte resolution. Therefore, the FDM and FCM

Page 104 - 5.3.1 DMA Controller

9-16 MSC8101 User’s GuideEnhanced Filter Coprocessor (EFCOP)dosetup0 empty doen0 #NSAMPloopstart0empty move.w M_FSTR,d4bmtstc #$0040,d4.ljt empty ;Wai

Page 105 - 5.3.2 SDMA Channels

Programming ExamplesEnhanced Filter Coprocessor (EFCOP) 9-17uses Adaptive mode and the data output not empty interrupt (IRQ3) to update the coefficien

Page 106 - Figure 5-8. SDMA Data Paths

9-18 MSC8101 User’s GuideEnhanced Filter Coprocessor (EFCOP)Example 9-3. Adaptive Filter Codemove.w #INPUT,r0 move.w #OUTPUT,r1 ;Init data pointersm

Page 107 - 5.4 Related Reading

Programming ExamplesEnhanced Filter Coprocessor (EFCOP) 9-19The interrupt service routine code, shown in Example 9-5, completes the processing as foll

Page 108 - 5-12 MSC8101 User’s Guide

9-20 MSC8101 User’s GuideEnhanced Filter Coprocessor (EFCOP)through the UPMC and to access the EFCOP registers through the GPCM, respectively. The mem

Page 109 - DMA Channels

Programming ExamplesEnhanced Filter Coprocessor (EFCOP) 9-21c. To configure channel 1 for 32-bit write transactions without incrementing the buffer ad

Page 110 - 6.1.1 Operating Modes

9-22 MSC8101 User’s GuideEnhanced Filter Coprocessor (EFCOP)Example 9-6. FIR Filter Sessionmove.w #FIR_FDBA,d0 ;Init FDBAmove.w d0,M_FDBAmove.w #FIR

Page 111 - 6.1.2 Transfer Types

Programming ExamplesEnhanced Filter Coprocessor (EFCOP) 9-23empty and channel 1 transfers eight 32-bit samples from the FDOR whenever the FDOR is full

Page 112 - External

© 2001, Motorola Inc. All rights reserved.EOnCE is a registered trademark of Motorola, Inc.StarCore, PowerQUICC II, Motorola, and the Motorola logo ar

Page 113

Before Using This Manual—Important Notexx MSC8101 User’s GuideBefore Using This Manual—Important NoteThis manual explains how to program the MSC8101.

Page 114

9-24 MSC8101 User’s GuideEnhanced Filter Coprocessor (EFCOP)d. The value 0x80014204 is written to the DMA Channel Configuration Register (DCHCR1). Thi

Page 115 - 6.2 Initializing the DMA

Related ReadingEnhanced Filter Coprocessor (EFCOP) 9-259.7 Related ReadingMSC8101 User’s Guide (This manual)Chapter 1, MSC8101 Overview Section 1.3.

Page 116 - Table 6-2. DCHCRx Bits

9-26 MSC8101 User’s GuideEnhanced Filter Coprocessor (EFCOP)

Page 117 - Table 6-3. DCPRAM Addressing

MSC8101 User’s Guide 10-1Chapter 10Multi-Channel Controllers (MCCs)This chapter describes a step-by-step procedure for setting up a 32-channel T1/E1 l

Page 118 - 6-10 MSC8101 User’s Guide

10-2 MSC8101 User’s GuideMulti-Channel Controllers (MCCs)The main MCC configuration is through MCC-specific parameters in the on-device Dual Port RAM

Page 119

MCC Configuration BasicsMulti-Channel Controllers (MCCs) 10-33. Configure the external interface:a. Set up the parallel I/O pins.b. Enable the TDM.T

Page 120 - 6.2.6 FIFO Requests

10-4 MSC8101 User’s GuideMulti-Channel Controllers (MCCs)10.1.2 Driver Memory MapAll values in the driver memory map are set up as offsets to the In

Page 121 - 6.2.9 Interrupts

MCC Configuration BasicsMulti-Channel Controllers (MCCs) 10-5Figure 10-4. Internal and External Memory Usage10.1.3 Memory UsageMemory resources ca

Page 122 - (DMA acknowledge)

10-6 MSC8101 User’s GuideMulti-Channel Controllers (MCCs)To simplify the relocation, all BDs for each MCC start from a fixed base in external memory,

Page 123

Connect the TDM Interface to T1/E1Multi-Channel Controllers (MCCs) 10-7Figure 10-5. T1/E1 Transceiver Interface ExampleThe TDM interface connection

Page 124 - 6-16 MSC8101 User’s Guide

OrganizationMSC8101 User’s Guide xxiOn the MSC8101, the SC140 core is a 16-bit DSP processor and the CPM contains a 32-bit RISC processor. The followi

Page 125

10-8 MSC8101 User’s GuideMulti-Channel Controllers (MCCs)Figure 10-6. T1/E1 Data Frame10.2.1 Provide Appropriate Signal Polarity and TimingTable 1

Page 126

Connect the TDM Interface to T1/E1Multi-Channel Controllers (MCCs) 10-9 External PHY loopback. The full external Transmit-to-Receive path tests the p

Page 127

10-10 MSC8101 User’s GuideMulti-Channel Controllers (MCCs)Line Clock (TLCLK) sourcing L1TCLK and the Ingress Clock (ICLK) connected to L1RCLK (see Fig

Page 128

Configure the ChannelsMulti-Channel Controllers (MCCs) 10-11 GRFTHR and GRFCNT. Two parameters relating to the reception of frames. GRFTHR is a thres

Page 129

10-12 MSC8101 User’s GuideMulti-Channel Controllers (MCCs) MCCM. The Interrupt Mask Register filters interrupt event requests to the core. In this ex

Page 130

Select the TSA Channel Route to a TDM TimeslotMulti-Channel Controllers (MCCs) 10-1310.3.4 Set Up the Channel Extra ParametersEach MCC channel has a

Page 131

10-14 MSC8101 User’s GuideMulti-Channel Controllers (MCCs)10.4.1 Define the Serial Interface Entries in SIRAMFigure 10-8. Serial InterfaceThe SIRA

Page 132 - from the vector base

Select the TSA Channel Route to a TDM TimeslotMulti-Channel Controllers (MCCs) 10-15Figure 10-9. Serial Interface Entry Definitions for Driver Examp

Page 133

10-16 MSC8101 User’s GuideMulti-Channel Controllers (MCCs)3. Timer Reference Register (TRR). Finally, the TRR1 register is set to contain the timeout

Page 134 - 6.6 Related Reading

MSC8101 User’s Guide 11-1Chapter 11Serial Peripheral Interface (SPI)The serial peripheral interface (SPI) is a synchronous serial data protocol that i

Page 135 - Chapter 7

Organizationxxii MSC8101 User’s Guide Chapter 4, Connecting External Memories and Memory-Mapped Devices. Memory interconnection options for the bus a

Page 136

11-2 MSC8101 User’s GuideSerial Peripheral Interface (SPI)The SPI signals are multiplexed with the port D pins, PD[16–19]. These pins can be configure

Page 137 - PERIPH_IR

Setting the ClockSerial Peripheral Interface (SPI) 11-311.2 Setting the ClockIn the master mode, the baud rate is determined by the divide by 16 opt

Page 138

11-4 MSC8101 User’s GuideSerial Peripheral Interface (SPI)changed only when the SPI is disabled. The remaining parameters are for communications proce

Page 139

Operating the SPI as a MasterSerial Peripheral Interface (SPI) 11-5then the SPI parameter table would begin at IMM + 0x3800. The RxBDs reside in the d

Page 140 - 7.3.4 Routing Interrupts

11-6 MSC8101 User’s GuideSerial Peripheral Interface (SPI)shifts transmit data out on SPIMOSI and receive data in on SPIMISO. Received data is written

Page 141 - 0x0 TRAP

Operating the SPI as a MasterSerial Peripheral Interface (SPI) 11-7The following example shows the steps required to initialize the SPI as a master. T

Page 142

11-8 MSC8101 User’s GuideSerial Peripheral Interface (SPI)a. Configure the RxBD and TxBD.Since there is only one RxBD, it is the last BD in the table.

Page 143 - 7.4.1 PIC Programming

Operating the SPI as a SlaveSerial Peripheral Interface (SPI) 11-911.5 Operating the SPI as a SlaveThe state diagram in Figure 11-4 shows how the SP

Page 144

11-10 MSC8101 User’s GuideSerial Peripheral Interface (SPI)The following example shows the steps required to initialize the SPI as a slave. The assump

Page 145

Operating the SPI as a SlaveSerial Peripheral Interface (SPI) 11-115. Configure MRBLR.Assume the maximum bytes per receive buffer is 16 bytes.SPIRAM-&

Page 146

Other MSC8101 DocumentationMSC8101 User’s Guide xxiiiOther MSC8101 Documentation MSC8101 Programmer’s Quick Reference. A hands-on reference to the pi

Page 147 - 7.4.4 PIC Macros

11-12 MSC8101 User’s GuideSerial Peripheral Interface (SPI)11.6 Responding to a Multi-master ErrorA multi-master error occurs when the SPISEL pin is

Page 148

Related ReadingSerial Peripheral Interface (SPI) 11-1311.7 Related ReadingMSC8101 User’s Guide (This manual)Chapter 1, MSC8101 Overview Section 1.3.

Page 149

11-14 MSC8101 User’s GuideSerial Peripheral Interface (SPI)

Page 150

MSC8101 User’s Guide 12-1Chapter 12EOnCE/JTAGThis chapter presents examples of how the EOnCE port can be used for system-level debugging of real-time

Page 151

12-2 MSC8101 User’s GuideEOnCE/JTAGbe issued to transition through the appropriate states. The first action that occurs when either block is entered i

Page 152

EOnCE/JTAG BasicsEOnCE/JTAG 12-312.1.1 InstructionsThe host sends JTAG instructions to the MSC8101 least significant bit first. As Figure 12-2 shows

Page 153 - Host Interface (HDI16)

12-4 MSC8101 User’s GuideEOnCE/JTAG12.1.2 Executing a JTAG InstructionThis section presents an example of how the host takes the instruction registe

Page 154 - 8.1.1 Host-Side Model

EOnCE/JTAG BasicsEOnCE/JTAG 12-5instructions are sent least significant bit first on TDI. If the TAP controller is in the Run-Test/Idle state, DEBUG_R

Page 155 - 8.1.2 DSP-Side Model

12-6 MSC8101 User’s GuideEOnCE/JTAGAll the EOnCE registers are accessible from the core and are memory-mapped. Therefore, each register has its own ad

Page 156

EOnCE/JTAG BasicsEOnCE/JTAG 12-70A PC_DETECT PC Breakpoint Detection Register 32... Reserved10 EDCA0_CTRL EDCA 0 Control Register 1611 EDCA1_CTRL EDCA

Page 157 - 8.2.1 Normal Mode

Further Readingxxiv MSC8101 User’s Guide

Page 158 - 8-6 MSC8101 User’s Guide

12-8 MSC8101 User’s GuideEOnCE/JTAGThe external host writes the instruction to be executed by the SC140 core into the CORE_CMD register. The SC140 cor

Page 159

EOnCE/JTAG BasicsEOnCE/JTAG 12-9 Opcode (bits 19–4). Derive from the instruction opcode. These bits are reversed in order from the instruction opcode

Page 160 - 8.2.2 Host DMA Mode

12-10 MSC8101 User’s GuideEOnCE/JTAG12.1.3.1 CORE_CMD Example 1Instruction: move.l #0xdead,d0Opcode:0x30C0 3EAD 8000CORE_CMD:0x0002 D5F0 30C312.1.3.

Page 161 - HDM0 is

Writing EOnCE Registers Through JTAGEOnCE/JTAG 12-1112.1.3.4 CORE_CMD Example 4Instruction: move.l #$c0ffee,d8Opcode:0x3820 A000 30E0 3FEE 80C0CORE_

Page 162 - 0 HACK pin is asserted

12-12 MSC8101 User’s GuideEOnCE/JTAGFigure 12-5. Writing EOnCE Registers12.3 Reading EOnCE Registers Through JTAGThis section presents an example o

Page 163 - Figure 8-3

Executing a Single Instruction Through JTAGEOnCE/JTAG 12-13Figure 12-6. Reading EOnCE Registers12.4 Executing a Single Instruction Through JTAGThis

Page 164 - 8-12 MSC8101 User’s Guide

12-14 MSC8101 User’s GuideEOnCE/JTAGFigure 12-7. Executing a Single Instruction Through JTAG12.5 Writing to the EOnCE Receive Register (ERCV)This s

Page 165 - 8.3.1 Software Polling

Reading From the EOnCE Transmit Register (ETRSMT)EOnCE/JTAG 12-15Figure 12-8. Writing to ERCV12.6 Reading From the EOnCE Transmit Register (ETRSMT)

Page 166

12-16 MSC8101 User’s GuideEOnCE/JTAGFigure 12-9. Reading From ETRSMT12.7 Downloading SoftwareThis section presents an example showing how software

Page 167 - 8.3.2 DSP Interrupts

Downloading SoftwareEOnCE/JTAG 12-17ECR[R/W] = 0 to perform a write access.ECR[GO] = 1 to execute the instruction.ECR[REGSEL] = 1111110 to select the

Page 168 - Table 8-16. PIC Interrupts

MSC8101 User’s Guide 1-1Chapter 1MSC8101 OverviewThe Motorola MSC8101 is a versatile, one-chip integration of a high-performance StarCore SC140 core,

Page 169 - Host Interface (HDI16) 8-17

12-18 MSC8101 User’s GuideEOnCE/JTAG Figure 12-10. Software DownloadingCHOOSE_EONCEShift in ‘1’ on TDIDEBUG_REQUESTWrite into ECR:Write, no Go, ERCV

Page 170 - 8.3.3 Host Requests

Writing and Reading the Trace BufferEOnCE/JTAG 12-1912.8 Writing and Reading the Trace BufferThis section presents an example that shows how the tra

Page 171 - Host Interface (HDI16) 8-19

12-20 MSC8101 User’s GuideEOnCE/JTAGBecause of the pre-fetch mechanism, a three-cycle delay must occur from the time the trace buffer is disabled unti

Page 172

Counting Core CyclesEOnCE/JTAG 12-213. Enable the event counter. The event counter is disabled but hardware enables it when EDCA #0 detects an event b

Page 173 - Host Interface (HDI16) 8-21

12-22 MSC8101 User’s GuideEOnCE/JTAGWhen the event counter counts the core clock, the memory contention and external wait state clocks are not counted

Page 174 - 8-22 MSC8101 User’s Guide

MSC8101 User’s Guide A-1Appendix AProgramming ReferenceThis reference for programmers includes a table summarizing the routing of programmable interru

Page 175 - Host Interface (HDI16) 8-23

Programming ReferenceA-2 MSC8101 User’s GuideA.1 Interrupt Sources and PrioritiesInterrupt SchemePIC Edge/Level-Triggered Interrupt Priority Registe

Page 176 - 8.5 Related Reading

Interrupt Sources and PrioritiesMSC8101 User’s Guide A-30x21 IRQ1 EFCOP (1): Input FIFO empty 0x8400x22 IRQ2EFCOP (2): Output FIFO full 0x8800x23 IRQ3

Page 177 - Chapter 9

Programming ReferenceA-4 MSC8101 User’s GuideTable A-3. SIC and SIC_EXT Interrupt Source PriorityPriority Level(Highest to Lowest)Description Multip

Page 178 - 9-2 MSC8101 User’s Guide

Interrupt Sources and PrioritiesMSC8101 User’s Guide A-537 Parallel I/O–PC12 No38 Reserved No39 Reserved No40 Timer 2 Yes41 Reserved No42 XSIU5 (GSIU

Page 179

1-2 MSC8101 User’s GuideMSC8101 Overview(ATM, Ethernet, IP). The MSC8101 performs digital signal processing tasks such as speech compression, echo can

Page 180 - 9-4 MSC8101 User’s Guide

Programming ReferenceA-6 MSC8101 User’s GuidePending unmasked interrupts are presented to the core in order of priority. The core reads SIVEC to get t

Page 181 - 9.2.2 Complex Mode

Programming SheetsMSC8101 User’s Guide A-7A.2 Programming SheetsThe programming sheets are presented in the order shown in Table A-1 on page A-1.23

Page 182 - 9.2.4 Magnitude Mode

Programming ReferenceA-8 MSC8101 User’s Guide16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31EPAR0123456789101112131415EBM APD2 LETMAPD1APD0 ETMSYSTEM

Page 183

Programming SheetsMSC8101 User’s Guide A-90123456789101112131415PTF0** = Reserved. Write to 0 for future compatibility0*0000****PS PTEPIESYSTEM INTERF

Page 184 - 9-8 MSC8101 User’s Guide

Programming ReferenceA-10 MSC8101 User’s GuideSIUMCR16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31TCPC0BCTLC00123456789101112131415BBDIRQ7INTDPPC0 DP

Page 185 - 9.4.1 Rounding

Programming SheetsMSC8101 User’s Guide A-11RESRES00SIUMCRMODCK1/BNKSEL0/TC0TC0RESBNKSEL0TCPC[0–1] – Transfer Code Pin Configuration, Bits 10–11MODCK2/

Page 186 - 9-10 MSC8101 User’s Guide

Programming ReferenceA-12 MSC8101 User’s Guide1 Software watchdog timer and bus monitor time-out0 Software watchdog timer and bus monitor time-outLBME

Page 187 - 9.5.1 Polling

Programming SheetsMSC8101 User’s Guide A-130123456789101112131415ALR SIE TCF0** = Reserved. Write to 0 for future compatibility0*0000****SEC TCEALESYS

Page 188 - 9.5.2 Interrupts

Programming ReferenceA-14 MSC8101 User’s Guide1 Accesses are handled by an external memory controller0 Accesses are handled by the memory controllerEM

Page 189 - 9.5.3 DMA

Programming SheetsMSC8101 User’s Guide A-15SCY1 SCY216 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31AM16 CSNT ACS0 ACS1 SCY3SCY0AM9 AM10 AM140123456789

Page 190 - 9.6 Programming Examples

FeaturesMSC8101 Overview 1-31.2.2 On-Device Memories Total of 512 KB (256 K × 16-bit words) unified on-device RAM 2 KB bootstrap ROM1.2.3 100 M

Page 191 - FCNT/2 complex

Programming ReferenceA-16 MSC8101 User’s GuideLSDAM[0–4] – Lower SDRAM Address Mask, Bits 12–16PSDMR[PBI] = 00010 A70100 A80110 A91000 A101010 A111100

Page 192

Programming SheetsMSC8101 User’s Guide A-1716 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31AM16AM9 AM10 AM140123456789101112131415AM0 AM3 AM4 AM5 AM6 A

Page 193

Programming ReferenceA-18 MSC8101 User’s Guide0001 Loop executes 1 timeTLFx[0–3] – Refresh Loop Field, Bits 22–250010 Loop executes 2 times1111 Loop e

Page 194

Programming SheetsMSC8101 User’s Guide A-19PSDMRWRC016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31RFRC2BLBSMA1 BSMA2 RFRC00123456789101112131415PBI O

Page 195

Programming ReferenceA-20 MSC8101 User’s GuidePSCMR/200 Reserved011102113WRC016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31RFRC2BLBSMA1 BSMA2 RFRC001

Page 196 - 9-20 MSC8101 User’s Guide

Programming SheetsMSC8101 User’s Guide A-21ELIRBPIC Edge/Level-Triggered Interrupt Priority Register BAddress: 0x1C08Reset: 0Read/Write012345678910111

Page 197 - NSAMP/4 data samples are

Programming ReferenceA-22 MSC8101 User’s GuideELIRDPIC Edge/Level-Triggered Interrupt Priority Register DAddress: 0x1C18Reset: 0Read/Write012345678910

Page 198

Programming SheetsMSC8101 User’s Guide A-23ELIRFPIC Edge/Level-Triggered Interrupt Priority Register FAddress: 0x1C28Reset: 0000_0000_0000_1000Read/Wr

Page 199 - Programming Examples

Programming ReferenceA-24 MSC8101 User’s Guide* = Reserved. Write to 0 for future compatibility* = Reserved. Write to 0 for future compatibilityINTERR

Page 200

Programming SheetsMSC8101 User’s Guide A-25BD_ATTR16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 310123456789101112131415INTRPTCONTCYCDIRECT MEMORY ACCE

Page 201 - 9.7 Related Reading

1-4 MSC8101 User’s GuideMSC8101 Overview1.2.6 On-Device Peripherals Enhanced 16-bit parallel host interface (HDI16) supports a variety of buses and

Page 202 - 9-26 MSC8101 User’s Guide

Programming ReferenceA-26 MSC8101 User’s GuideBD_ATTR216 17 18 19 20 21 22 23 24 25 26 27 28 29 30 310123456789101112131415INTRPTCONTCYCDIRECT MEMORY

Page 203 - Chapter 10

Programming SheetsMSC8101 User’s Guide A-2716 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31DRACKDPL0123456789101112131415ACTV EXP0 EXP1 EXP2 DRSPPCDIRE

Page 204

Programming ReferenceA-28 MSC8101 User’s Guide16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31DRACKDPL0123456789101112131415ACTV EXP0 EXP1 EXP2 DRSPPCD

Page 205

Programming SheetsMSC8101 User’s Guide A-29FACR0123456789101112131415ENHANCED FILTERFACREFCOP ALU Control RegisterAddress: 0x0CA0Reset: 0Read/WriteCOP

Page 206 - 10.1.2 Driver Memory Map

Programming ReferenceA-30 MSC8101 User’s Guide0123456789101112131415FDOMFONEIEFDIMENHANCED FILTERFCTLEFCOP Control Register (page 1 of 2)Address: 0x0C

Page 207 - 10.1.3 Memory Usage

Programming SheetsMSC8101 User’s Guide A-31FCTL0123456789101112131415FDOM FONEIEFDIMENHANCED FILTERFCTLEFCOP Control Register (page 2 of 2)Address: 0x

Page 208 - × 64 Kbps slots

Programming ReferenceA-32 MSC8101 User’s Guide0123456789101112131415HF4 HF6HF5HCR (HICR=0)Host Control RegisterAddress: 0x0000Hardware Reset: 0,Read/W

Page 209

Programming SheetsMSC8101 User’s Guide A-330123456789101112131415HF4 HF6HF5HCR (HICR=1)Host Control RegisterAddress: 0x0000Hardware Reset: 0,Read/Writ

Page 210 - 10-8 MSC8101 User’s Guide

Programming ReferenceA-34 MSC8101 User’s Guide0123456789101112131415HAP HRPHPCRHost Port Control RegisterAddress: 0x0020Hardware Reset: 0,Read/WriteHO

Page 211 - × 8), thus creating a

Programming SheetsMSC8101 User’s Guide A-350123456789101112131415HDM0HF0 HF1 HDM1 HF2 HF30** = Reserved. Write to 0 for future compatibility0*0000****

Page 212 - 10.3 Configure the Channels

FeaturesMSC8101 Overview 1-5 Four full-duplex serial communication controllers (SCCs) supporting IEEE 802.3/Ethernet, high-level synchronous data lin

Page 213 - 0x3800 is used

Programming ReferenceA-36 MSC8101 User’s Guide• RREQ and TREQ should not be set at the same time0123456789101112131415ICR (DMA=0, DMA=1, HICR=1)Interf

Page 214

MSC8101 User’s Guide Appendix B-1Appendix BGlossaryThis glossary presents an alphabetical list of terms, phrases, and abbreviations that are used in t

Page 215

Appendix B-2 MSC8101 User’s GuideGlossaryAGUAddress generation unit. One of the execution units in the MSC8101. The AGU performs effective address cal

Page 216 - 10-14 MSC8101 User’s Guide

Glossary Appendix B-3basebandThe original band of frequencies of a signal before it is modulated for transmission at a higher frequency. The signal is

Page 217 - BRG50 pin must be

Appendix B-4 MSC8101 User’s GuideGlossarybroadbandAlso called wideband. A type of data transmission in which a single medium (wire) can carry several

Page 218 - 10.6 Related Reading

Glossary Appendix B-5CPMCommunications processor module. One of three internal modules in the MSC8101: CPM, SIU, and SC140 extended core. The CPM cons

Page 219

Appendix B-6 MSC8101 User’s GuideGlossaryDMADirect memory access. A fast method of moving data from a storage device to RAM, which speeds up processin

Page 220

Glossary Appendix B-7E1The European equivalent of the North American T1, except that E1 carries information at the rate of 2.048 Mbps. This is a telep

Page 221 - 11.2 Setting the Clock

Appendix B-8 MSC8101 User’s GuideGlossaryFCCFast communications controllers. A type of serial communications controller (SCC) optimized for synchronou

Page 222 - 11-4 MSC8101 User’s Guide

Glossary Appendix B-9FIRFinite impulse response. A type of filter. FIR filters are characterized by transfer functions that are polynomials, where the

Page 223 - Operating the SPI as a Master

1ABIND23456789101112MSC8101 OverviewReset Configuration and BootOptimizing Memory on the SC140 CoreConnecting External Memories and Memory-Mapped Devi

Page 224 - Figure 11-3. SPI as a Master

1-6 MSC8101 User’s GuideMSC8101 Overview1.2.11 Packaging 332-pin 0.8 mm pitch 17 × 17 mm flip chip plastic ball grid array (FCPBGA)1.2.12 Softwa

Page 225

Appendix B-10 MSC8101 User’s GuideGlossaryGPCMGeneral-purpose chip-select machine. Part of the MSC8101 memory controller. The GPCM provides interfacin

Page 226 - 11-8 MSC8101 User’s Guide

Glossary Appendix B-11MACMultiply and accumulate. On the SC140 core, the MAC unit is the main arithmetic processing unit. It performs all the calculat

Page 227 - Figure 11-4. SPI as Slave

Appendix B-12 MSC8101 User’s GuideGlossaryMIIMedia independent interface. Part of the Fast Ethernet specification, the MII replaces 10BaseT AUI (Attac

Page 228

Glossary Appendix B-13PICProgram interrupt controller. A peripheral module to serve all the interrupt requests (IRs) and non-maskable interrupts (NMIs

Page 229 - Operating the SPI as a Slave

Appendix B-14 MSC8101 User’s GuideGlossarySCCSerial communications controller. The MSC8101 has four SCCs, which can be configured independently to imp

Page 230

Glossary Appendix B-15SIUSystem interface unit. Controls system start-up and initialization, as well as operation, protection, and the external system

Page 231 - 11.7 Related Reading

Appendix B-16 MSC8101 User’s GuideGlossarySRAMStatic random access memory. Contrast with dynamic random access memory (DRAM). The dynamic nature of th

Page 232 - 11-14 MSC8101 User’s Guide

Glossary Appendix B-17.transactionA complete exchange between two bus devices. A typical transaction is composed of an address tenure and a data tenur

Page 233

Appendix B-18 MSC8101 User’s GuideGlossary

Page 234 - 12-2 MSC8101 User’s Guide

MSC8101 User’s Guide C-1Appendix CBootloader ProgramThis appendix lists the boot program for the MSC8101.;;/******************************************

Page 235 - 12.1.1 Instructions

ArchitectureMSC8101 Overview 1-7contains two address arithmetic units (AAUs), one bit mask unit (BMU), and one branch unit. Overall, the SC140 can iss

Page 236 - 12-4 MSC8101 User’s Guide

C-2 MSC8101 User’s GuideBootloader Program;; HOST registers addresses definitions;; dsp side HCR equ BASE0_D+$0000HPCR equ BASE0_D+$002

Page 237 - 12.1.3 Registers

Bootloader Program C-3 endsec;---------- auto ir exception offset 0x1c0 ---------- section auto_ir_exception org p:$

Page 238 - 12-6 MSC8101 User’s Guide

C-4 MSC8101 User’s GuideBootloader Program;; calculating the checksum; during the loading process the check sum is calculated for the whole; long an

Page 239 - EOnCE/JTAG 12-7

Bootloader Program C-5 ; d3 xor 3’b100 to recover original isb eor #$4,d3.l ;r3 <- d3 move.l d3,r3 nop

Page 240 - 12-8 MSC8101 User’s Guide

C-6 MSC8101 User’s GuideBootloader Program;write checksum , ~checksum at the and of the block move.l d5,(r3);calculate the checksum of these wo

Page 241 - EOnCE/JTAG 12-9

Bootloader Program C-7 ;move the size into d6 move.l d4,d6 ;move the address into r3 move.l d5,r3 ;; check if the f

Page 242 - 12.1.3.3 CORE_CMD Example 3

C-8 MSC8101 User’s GuideBootloader Programload_8bit ;d7 = 0 , checksm =0 clr d7 ;load the size into d6 jsr load_from_fi

Page 243 - EOnCE/JTAG 12-11

Bootloader Program C-9 and #$0000ffff,d7,d7 ;d7 = d7 ^ d2 eor d2,d7 ;d2 = (~d7 & 0x0000ffff) = ~checksum not d7

Page 244 - 12-12 MSC8101 User’s Guide

C-10 MSC8101 User’s GuideBootloader Program and #$0000ffff,d4,d4 ;if ( checksum_loaded |= Checksum_calculated ) goto set sticky bit

Page 245 - EOnCE/JTAG 12-13

Bootloader Program C-11 ;d7 = d7 ^ d2 eor d2,d7 ;d2 = (~d7 & 0x0000ffff) = ~checksum not d7,d2 and #$0000ffff,d

Page 246 - 12-14 MSC8101 User’s Guide

1-8 MSC8101 User’s GuideMSC8101 OverviewFigure 1-1. MSC8101 Block Diagram1.3.3 System Interface Unit (SIU)The SIU consists of the following: A Powe

Page 247 - Figure 12-8. Writing to ERCV

C-12 MSC8101 User’s GuideBootloader Program move.2l (r0),d4:d5 rtsset_sticky_bit ;set the hf6 bit in HCR move.w HCR,d6

Page 248 - 12.7 Downloading Software

Bootloader Program C-13 move.l d1,r6 move.l #$02000000,d1 ; base address for sram is 0x0200_0000 move.l d1,r5 ;

Page 249 - EOnCE/JTAG 12-17

C-14 MSC8101 User’s GuideBootloader Program move.w #$0,(r5) ; move.l #$00030044,d7 move.l d7,(r6+$188) ;

Page 250 - 12-18 MSC8101 User’s Guide

Bootloader Program C-15 move.w #$0,(r5) ; move.l #$00000045,d7 move.l d7,(r6+$188) ; move.w #$0,(r5)

Page 251 - EOnCE/JTAG 12-19

C-16 MSC8101 User’s GuideBootloader Program

Page 252 - 12.10 Counting Core Cycles

MSC8101 User’s Guide D-1AA address bus signal (A[0–31])AACK address acknowledge signalAAL ATM adaptation layerAAU address arithmetic unitABB address b

Page 253 - EOnCE/JTAG 12-21

D-2 MSC8101 User’s GuideCHAMR Channel Mode RegisterC/I command/indication (channel)CI congestion indicationCLP cell loss priorityCLSN collision signal

Page 254 - 12.11 Related Reading

MSC8101 User’s Guide D-3ENQ enquiry characterEOB end-of-burst (data)EOnCE Enhanced On-Chip EmulationEPD early packet discardEPROM erasable programmabl

Page 255 - Programming Reference

D-4 MSC8101 User’s Guide(core-side)HD host data bus signalHDDS host dual data strobe signalHDI16 host interface (enhanced 16-bit parallel host interfa

Page 256 - A-2 MSC8101 User’s Guide

MSC8101 User’s Guide D-5LDMTEA Local PowerPC Bus DMA Transfer Error Address RegisterLDMTER Local PowerPC Bus DMA Transfer Error Requestor Number Regis

Page 257 - MSC8101 User’s Guide A-3

ArchitectureMSC8101 Overview 1-9 A memory controller supporting eight external memory banks. The memory controller, which is based on the MPC8260 mem

Page 258 - A-4 MSC8101 User’s Guide

D-6 MSC8101 User’s GuidePCM pulse-code modulationPCMCIA Personal Computer Memory Card International AssociationPCR peak cell ratePCU program control u

Page 259 - MSC8101 User’s Guide A-5

MSC8101 User’s Guide D-7RQNUM requestor numberRSCFG Reset Configuration Registers (host-side)RSR Reset Status RegisterRSTATE receiver stateRSTCONF res

Page 260 - A-6 MSC8101 User’s Guide

D-8 MSC8101 User’s GuideSPIM SPI Mask RegisterSPLL system PLLSPLL MF SPLL multiplication factorSPLL PDF SPLL pre-division factorSPMODE SPI Mode regist

Page 261 - A.2 Programming Sheets

MSC8101 User’s Guide D-9UNI user-network interfaceUPM user-programmable machineUPM user-programmable machineUSART universal synchronous/asynchronous r

Page 262 - SYSTEM INTERFACE UNIT

D-10 MSC8101 User’s Guide

Page 263 - Read/Write

IndexMSC8101 User’s Guide Index-1Numerics300 MHz clock at 1.5 V core voltage 1-23G infrastructure cellular BTS configuration 1-2360x SDRAM Protocol-Sp

Page 264

Index-2 MSC8101 User’s Guidereceive buffer descriptor (RxBD) table 1-13RxBD buffer pointer 1-14RxBD data length 1-14RxBD processing example 1-18status

Page 265

MSC8101 User’s Guide Index-3DMA FIFO peripheral data transfers 6-5DMA FIFO to memory data transfers 6-4DMA Internal Mask Register (DIMR) 6-7DMA Pin Co

Page 266

Index-4 MSC8101 User’s Guideeliminate clock skews 2-2enhanced filter coprocessor (EFCOP) 1-4Adaptive and Multichannel modes 9-4Adaptive mode 9-4Adapti

Page 267 - Address: 0x10220

MSC8101 User’s Guide Index-5downloading software 12-1entering Debug mode 12-20EOnCE Control Register (ECR) 12-5EOnCE registers 12-5event counter, even

Page 268 - BR[0–7, 10, 11]

1-10 MSC8101 User’s GuideMSC8101 Overview1.3.6 Enhanced Filter Coprocessor (EFCOP)The EFCOP performs filtering operations vital to such DSP tasks as

Page 269 - OR[0–7, 10, 11]

Index-6 MSC8101 User’s Guideactivate the DMA 8-21as asynchronous interface 4-14broadcast bootstrap code to all devices 4-15clearing an interrupt 8-16d

Page 270

MSC8101 User’s Guide Index-7Host Transmit Not Full bit in the Host Status Register 8-14host-side Receive Data Registers (RX) 8-6host-side Transmit Dat

Page 271

Index-8 MSC8101 User’s Guideassign priority 5 to the SIC interrupt 7-9clear an edge-triggered interrupt request 7-13clear pending requests 7-9disable

Page 272 - MAMR, MBMR, MCMR

MSC8101 User’s Guide Index-9define a base for the Transmit (Tx) and Receive (Rx) buffer descriptor (BD) rings 10-10define interrupt queue addresses 10

Page 273

Index-10 MSC8101 User’s GuidePpackaging 1-6page-based interleaved configuration (PSDMR PBI bit = 1) 4-8page-based interleaving 4-8, 4-13parallel arith

Page 274

MSC8101 User’s Guide Index-11RSTCONF 2-5, 2-9, 2-10, 2-14RxBD buffer pointer 1-14SSC100 DSP cores 1-1SC140 application development methodology 3-1SC14

Page 275 - INTERRUPT SCHEME

Index-12 MSC8101 User’s Guidesystem-level debugging of real-time systems 12-1TT1, CEPT, T1/E1,T3/E3, pulse code modulation highway, ISDN basic rate 1-

Page 276

ArchitectureMSC8101 Overview 1-11The MCC also supports super channels of rates higher than 64 Kbps and subchanneling of the 64 Kbps channels. Four fu

Page 277

1-12 MSC8101 User’s GuideMSC8101 Overview1.3.7.2 CPM ConfigurationsThe CPM comprises many different functional blocks and offers flexibility in conf

Page 278 - SIEXR/SIEXR_EXT

ArchitectureMSC8101 Overview 1-131.3.7.3 Buffer DescriptorsIf you are programming the CPM serial controllers, you need to know how the serial contro

Page 279 - DIRECT MEMORY ACCESS

1-14 MSC8101 User’s GuideMSC8101 OverviewBD.bd_cstat.bitThe structural elements of a buffer descriptor are defined as follows: Status and control. Th

Page 280

ArchitectureMSC8101 Overview 1-15these channels. The exact definition of the parameter RAM, which differs for each protocol, is provided in the MSC810

Page 281 - DCHCR[0–15]

1ABIND23456789101112MSC8101 OverviewReset Configuration and BootOptimizing Memory on the SC140 CoreConnecting External Memories and Memory-Mapped Devi

Page 282

1-16 MSC8101 User’s GuideMSC8101 OverviewTable 1-6 shows the parameter RAM for all SCC protocols. You must initialize entries with boldfaced names bef

Page 283 - COPROCESSOR

ArchitectureMSC8101 Overview 1-171.3.7.5 BD and Buffer Memory StructureThe BDs of all protocols can point to data buffers that are located in the in

Page 284 - Address: 0x0C80

1-18 MSC8101 User’s GuideMSC8101 OverviewFigure 1-3. Example SCC2 BD and Buffer Memory Structure1.3.7.6 RxBD Processing ExampleFigure 1-5 shows how

Page 285

ArchitectureMSC8101 Overview 1-19Figure 1-4. Example SPI BD and Buffer Memory StructureIf RxBD.bd_cstat.E is cleared, the current buffer is not empty

Page 286 - Hardware Reset: 0

1-20 MSC8101 User’s GuideMSC8101 OverviewFigure 1-5. Example SCC UART RxBD Processing1.3.7.7 TxBD Processing ExampleFigure 1-6 shows how the TxBD i

Page 287 - HOST INTERFACE

MSC8101 Application ExamplesMSC8101 Overview 1-21Figure 1-6. Example SCC UART TxBD Processing1.4 MSC8101 Application Examples The MSC8101 can be co

Page 288 - Address: 0x0020

1-22 MSC8101 User’s GuideMSC8101 Overview1.4.1 Media (Voice/Fax/Data) Over Packet Gateway (ATM/FR/IP)Figure 1-7 shows the media (voice/fax/data) ove

Page 289 - ICR (DMA=0, DMA=1, HICR=0)

MSC8101 Application ExamplesMSC8101 Overview 1-23supports many types of memories, including EDO DRAM and page-mode as well as pipeline SDRAM for effic

Page 290 - ICR (DMA=0, DMA=1, HICR=1)

1-24 MSC8101 User’s GuideMSC8101 OverviewFigure 1-9. Centralized DSP Architecture1.4.4 Distributed DSP ArchitectureFigure 1-10 shows a distributed

Page 291 - Glossary

MSC8101 Application ExamplesMSC8101 Overview 1-25Figure 1-10. Distributed DSP Architecture Connected Through the HDI16 PortIn the configuration depic

Page 292

ContentsMSC8101 User’s Guide vPrefaceBefore Using This Manual—Important Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxAudienc

Page 293 - Glossary Appendix B-3

1-26 MSC8101 User’s GuideMSC8101 Overview1.5 Software DevelopmentFigure 1-12 shows the typical software development flow for the MSC8101.Figure 1-12

Page 294

Software DevelopmentMSC8101 Overview 1-27window-based and provides multiple views of the code. You can use it to debug C source code, assembly code, o

Page 295 - Debug mode

1-28 MSC8101 User’s GuideMSC8101 Overview

Page 296 - DSP MIPs

MSC8101 User’s Guide 2-1Chapter 2Reset Configuration and Boot This chapter describes the MSC8101 reset and boot process illustrated with examples of d

Page 297 - Glossary Appendix B-7

2-2 MSC8101 User’s GuideReset Configuration and Boot2.1.1 Bootloader ProgramThe MSC8101 bootloader program resides in the on-device ROM, starting at

Page 298 - FC-PBGA

Reset Configuration and Boot BasicsReset Configuration and Boot 2-3multiplication factor is determined by the values of the SPLL pre-division factor a

Page 299 - Glossary Appendix B-9

2-4 MSC8101 User’s GuideReset Configuration and BootSix bits map the MSC8101 clocks to one of 64 configuration mode options. Each option determines th

Page 300

Configuring a Single MSC8101Reset Configuration and Boot 2-52.2.2 Slave Mode With No EPROMFor a system with no boot EPROM, you can configure the MSC

Page 301 - Glossary Appendix B-11

2-6 MSC8101 User’s GuideReset Configuration and Boot2.2.3 Default Configuration With No EPROMThe default MSC8101 reset configuration is the simplest

Page 302

Configuring a Multi-MSC8101 System, PowerPC Bus ConnectedReset Configuration and Boot 2-72.3 Configuring a Multi-MSC8101 System, PowerPC Bus Connect

Page 303 - TXD, RXD, and SMSYN

Contentsvi MSC8101 User’s Guide1.3.7.6 RxBD Processing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-181.3.

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2-8 MSC8101 User’s GuideReset Configuration and BootFigure 2-4. Multi-MSC8101 PowerPC Bus SystemPORESETPORESETPORESETPORESETA1A6HRESETHRESETHRESETHRE

Page 305 - Glossary Appendix B-15

Configuring a Multi-MSC8101 System, PowerPC Bus ConnectedReset Configuration and Boot 2-92.3.1 Reset Configuration SequenceThe reset configuration s

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2-10 MSC8101 User’s GuideReset Configuration and BootThe configuration master first reads a value from address 0x00 and then reads a value from addres

Page 307 - Glossary Appendix B-17

Configuring a Multi-MSC8101 System, PowerPC Bus ConnectedReset Configuration and Boot 2-112.3.3 Boot in a Multi-MSC8101 PowerPC Bus SystemThe MSC810

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2-12 MSC8101 User’s GuideReset Configuration and Boot2.4 Configuring a Multi-MSC8101 System Connected Via the Host PortThis section presents an exam

Page 309 - Bootloader Program

Configuring a Multi-MSC8101 System Connected Via the Host PortReset Configuration and Boot 2-13Figure 2-5. Multiple MSC8101s Connected Via the Host P

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2-14 MSC8101 User’s GuideReset Configuration and Boot2.4.1 Host Reset Configuration SequenceThis section describes how the reset configuration word

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Configuring a Multi-MSC8101 System Connected Via the Host PortReset Configuration and Boot 2-152.4.2 Boot Through Host PortThe MSC8101 host interfac

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2-16 MSC8101 User’s GuideReset Configuration and BootThe bootloader routine expects at least one code block. When more than one block is included in t

Page 313 - long instead of bytes

Related ReadingReset Configuration and Boot 2-17checksum. The checksum is calculated by XORing the current word bit by bit with the result of XORing p

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ContentsMSC8101 User’s Guide vii4.3.1 GPCM Hardware Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44.3.2

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2-18 MSC8101 User’s GuideReset Configuration and Boot

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MSC8101 User’s Guide 3-1Chapter 3Optimizing Memory on the SC140 CoreThis chapter describes the memory mechanism of the SC140 core and explains how to

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3-2 MSC8101 User’s GuideOptimizing Memory on the SC140 Core The SC140 core does not support accesses to a non-existent memory location. If required,

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Allocating MemoryOptimizing Memory on the SC140 Core 3-3Figure 3-1. Memory Organization0 1 2...3031MODULE 032 33 34 62 63MODULE 1GROUP 0255254...2262

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3-4 MSC8101 User’s GuideOptimizing Memory on the SC140 Core3.4 Avoiding Memory ContentionsContentions occur when there are multiple requests for acc

Page 320

Related ReadingOptimizing Memory on the SC140 Core 3-5use the addresses 0..0x7FFF (group0) for data storage and addresses 0x8000..0xFFF for program me

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3-6 MSC8101 User’s GuideOptimizing Memory on the SC140 Core

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MSC8101 User’s Guide 4-1Chapter 4Connecting External Memories and Memory-Mapped DevicesThis chapter illustrates several memory interconnection options

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4-2 MSC8101 User’s GuideConnecting External Memories and Memory-Mapped Devicesgranularity. Developers commonly use this flexibility for user-defined i

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External Bus BasicsConnecting External Memories and Memory-Mapped Devices 4-3Figure 4-1. Memory Controller OverviewThe Single-Master MSC8101 Bus mode

Page 325 - Acronyms and Abbreviations

Contentsviii MSC8101 User’s Guide6.2.4 DMA Internal/External Mask Registers (DIMR/DEMR) . . . . . . . . . . . . . . . . . . . 6-96.2.5 DMA Channel Par

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4-4 MSC8101 User’s GuideConnecting External Memories and Memory-Mapped Devices4.3 Connecting the Bus to the Flash Memory InterfaceIn most embedded s

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Connecting the Bus to the Flash Memory InterfaceConnecting External Memories and Memory-Mapped Devices 4-54.3.2 Single-Bus Mode GPCM-Based TimingsTh

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4-6 MSC8101 User’s GuideConnecting External Memories and Memory-Mapped DevicesFigure 4-4. Flash Memory Write, Single MasterFor the AMD AM29LV160D-70n

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Connecting the Bus to the SDRAM Memory InterfaceConnecting External Memories and Memory-Mapped Devices 4-7more time at the beginning and end of cycles

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4-8 MSC8101 User’s GuideConnecting External Memories and Memory-Mapped Devices4.4.1 Single-Bus Mode SDRAM Hardware InterconnectWhen the MSC8101 oper

Page 331 - MSC8101 User’s Guide D-7

Connecting the Bus to the SDRAM Memory InterfaceConnecting External Memories and Memory-Mapped Devices 4-9two least significant addresses from the MSC

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4-10 MSC8101 User’s GuideConnecting External Memories and Memory-Mapped DevicesTable 4-2 summarizes the control settings of the MSC8101 SDRAM controll

Page 333 - MSC8101 User’s Guide D-9

Connecting the Bus to the SDRAM Memory InterfaceConnecting External Memories and Memory-Mapped Devices 4-11Figure 4-7. SDRAM Burst Read Page Miss, Si

Page 334 - D-10 MSC8101 User’s Guide

4-12 MSC8101 User’s GuideConnecting External Memories and Memory-Mapped DevicesFor write accesses, the SDRAM controller Activate to R/W = 2 and Write

Page 335 - Numerics

Connecting the Bus to the SDRAM Memory InterfaceConnecting External Memories and Memory-Mapped Devices 4-134.4.5 PowerPC 60x Bus Mode SDRAM Hardware

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ContentsMSC8101 User’s Guide ix8.3.1.3 Host Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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4-14 MSC8101 User’s GuideConnecting External Memories and Memory-Mapped Devices4.5 Connecting the Bus to the HDI16 Memory InterfaceThe HDI16 host po

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Connecting the Bus to the HDI16 Memory InterfaceConnecting External Memories and Memory-Mapped Devices 4-15Note: The standard MSC8101 GPCM can glueles

Page 339 - , 1-4, 1-22, 4-2, 5-3

4-16 MSC8101 User’s GuideConnecting External Memories and Memory-Mapped DevicesFigure 4-11. Single-Master MSC8101 Bus to HDI16 InterfaceSee Figure 4-

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Connecting the Bus to the HDI16 Memory InterfaceConnecting External Memories and Memory-Mapped Devices 4-17Figure 4-12. Multi-Master PowerPC System B

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4-18 MSC8101 User’s GuideConnecting External Memories and Memory-Mapped Deviceseffect. The DLT3 bit must be set in the corresponding UPM word to indic

Page 342 - SET command 4-7

Related ReadingConnecting External Memories and Memory-Mapped Devices 4-194.6 Related ReadingCChCMSC8101 User’s Guide (This manual)Chapter 2, Reset

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4-20 MSC8101 User’s GuideConnecting External Memories and Memory-Mapped Devices

Page 344 - -ALL-BANKS command 4-7

MSC8101 User’s Guide 5-1Chapter 5Balancing Between the PowerPC System and Local BusesThe MSC8101 combines the SC140 core with the PowerPC bus and the

Page 345

5-2 MSC8101 User’s GuideBalancing Between the PowerPC System and Local BusesFigure 5-1. MSC8101 Block Diagram5.1 PowerPC System Bus Because the Pow

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PowerPC System BusBalancing Between the PowerPC System and Local Buses 5-3(UPM) memory controllers. Since the PowerPC local bus does not have access e

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