Motorola MVME172 Manuel d'utilisateur

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Page 1 - User's Manual

172Bug DiagnosticsUser's Manual V172DIAA/UM1

Page 2 - Tempe, Arizona 85282

LC - Loop-Continue 2-8LE - Loop-On-Error 2-9LF - Line Feed Suppression 2-9LN - Loop Non-Verbose 2-9NV - Non-Verbose 2-9SE - Stop-On-Error 2-9Introduc

Page 3

Diagnostic Tests3-623On receipt of an unexpected access exception, the following message appears:Bus Error Information: Address _____

Page 4 - Conventions

CMMU - Cache and Memory Management Unit3-633CCHSCC - Cache Supervisor Code Cache InhibitThe CCHSCC test checks the ability of the MMU to not execute c

Page 5 - Manual Terminology

Diagnostic Tests3-643If the string fails to verify or does not execute, an error message appears. If during the test an unexpected exception occurs, t

Page 6 - Notice of Copyright

CMMU - Cache and Memory Management Unit3-653On receipt of an unexpected access exception, the following message appears:Bus Error Information:

Page 7 - Safety Depends On You

Diagnostic Tests3-663CCHSD - Cache Supervisor DataThis test checks the ability of the MMU to write and read cached data in the Supervisory mode. The t

Page 8

CMMU - Cache and Memory Management Unit3-673Command Input172-Diag> CMMU CCHSD MessagesIf the memory range is less than $32000 bytes, the following

Page 9 - Contents

Diagnostic Tests3-683CCHSDC - Cache Supervisor Data Cache InhibitThis test checks the ability of the MMU to not write and read the data cache in the S

Page 10

CMMU - Cache and Memory Management Unit3-693Command Input172-Diag> CMMU CCHSDCI MessagesIf the memory range specified is less than $32000 bytes, th

Page 11

Diagnostic Tests3-703CCHSDWT - Cache Supervisor Data Write ThroughThis test checks the ability of the MMU to operate in Supervisory mode if write thro

Page 12

CMMU - Cache and Memory Management Unit3-713If pattern 2 (cached) fails to verify or if memory fails to verify, an error message appears. If during th

Page 13

WDTMRB - Watchdog Timer Board Fail 3-42WDTMRC - Watchdog Timer Local Reset 3-43MCECC - ECC Memory Board 3-44ConÞguration Parameters 3-44CBIT - Check-

Page 14 - List of Figures

Diagnostic Tests3-723If an unexpected exception is taken, the following message appears:Unsolicited Exception: Program Counter ________

Page 15 - List of Tables

CMMU - Cache and Memory Management Unit3-733CCHTTM - Translation Table MemoryThis test checks the memory (RAM) that is used for the translation table.

Page 16

Diagnostic Tests3-743If any data verification phase fails, the following message appears: Data Miscompare Error: Address =________, Expected =________

Page 17 - 1General Information

CMMU - Cache and Memory Management Unit3-753CCHUC - Cache User CodeThis test checks the ability of the MMU to execute cached instructions in the User

Page 18 - Memory Requirements

Diagnostic Tests3-76316. The code cache is flushed and invalidated (this should do nothing because this is a code cache, not a data cache). 17. Memory

Page 19

CMMU - Cache and Memory Management Unit3-773If the wrong instruction strings are executed, the following message appears: Code Execution Status Error:

Page 20 - 172Bug Implementation

Diagnostic Tests3-783CCHUCCI - Cache User Code Cache InhibitThis test checks the ability of the MMU to not execute cached instructions in the User mod

Page 21 - Installation

CMMU - Cache and Memory Management Unit3-793The memory range specified by the configuration parameters starting address and ending address must be at

Page 22

Diagnostic Tests3-803On receipt of an unexpected access exception, the following message appears:Bus Error Information: Address _____

Page 23

CMMU - Cache and Memory Management Unit3-813CCHUD - Cache User DataThis test checks the ability of the MMU to write and read cached data in the User m

Page 24 - System Console

SWIA - Software Interrupts (Polled Mode) 3-128SWIB - Software Interrupts (Processor Interrupt Mode) 3-130SWIC - Software Interrupts Priority 3-132TAC

Page 25 - Start-up

Diagnostic Tests3-823A trap always true instruction (vector 7) is executed to return the MPU to the supervisor mode.The memory range specified by the

Page 26 - General Information

CMMU - Cache and Memory Management Unit3-833On receipt of an unexpected access exception, the following message appears:Bus Error Information:

Page 27

Diagnostic Tests3-843CCHUDCI - Cache User Data Cache InhibitThis test checks the ability of the MMU to not write and read the data cache in the User m

Page 28

CMMU - Cache and Memory Management Unit3-853If pattern 2 (not cached) fails to verify, or if memory fails to verify, an error message appears. If duri

Page 29 - 2Using the Diagnostics

Diagnostic Tests3-863If an unexpected exception is taken, the following message appears:Unsolicited Exception: Program Counter ________

Page 30 - Diagnostic Commands

CMMU - Cache and Memory Management Unit3-873CCHUDWT - Cache User Data Write ThroughThis test checks the ability of the MMU to operate in the User mode

Page 31 - CEM - Clear Error Messages

Diagnostic Tests3-883The memory range specified by the configuration parameters starting address and ending address must be at least $32000 bytes.If p

Page 32 - HE - Help

CMMU - Cache and Memory Management Unit3-893If an unexpected exception is taken, the following message appears:Unsolicited Exception: Program C

Page 33

Diagnostic Tests3-903MMUMU - MMU Modified/Used Data/CodeThis test checks the ability of the MMU to set the Used and Modified bits in the Page Descripto

Page 34 - SD - Switch Directories

CMMU - Cache and Memory Management Unit3-913MessagesIf the memory range is less than $32000 bytes, the following message appears:Insufficient Amount o

Page 35 - ZP - Zero Pass Count

ELPBCK - SCC External Loopback 3-194ILPBCK - SCC Internal Loopback 3-195MDMC - SCC Modem Control 3-196SCC Error Messages 3-197FLASH - Flash Memory Te

Page 36 - Test Prefixes

Diagnostic Tests3-923MMUSC - MMU Supervisor CodeThis test checks the ability of the MMU to execute instructions in Supervisor mode. The test runs as f

Page 37 - Test Prefixes

CMMU - Cache and Memory Management Unit3-933The memory range specified by the configuration parameters starting address and ending address must be at

Page 38 - Using the Diagnostics

Diagnostic Tests3-943If an unexpected exception is taken, the following message appears:Translation failed causing exception.Unsolicited Exception:

Page 39 - 3Diagnostic Tests

CMMU - Cache and Memory Management Unit3-953MMUSD - MMU Supervisor DataThis test checks the ability of the MMU to access data in Supervisor mode. The

Page 40 - Running the Tests

Diagnostic Tests3-963The memory range specified by the configuration parameters starting address and ending address must be at least $32000 bytes.If t

Page 41 - SRAM - Static RAM

CMMU - Cache and Memory Management Unit3-973Bus Error Information: Address ________ Data ________ Ac

Page 42

Diagnostic Tests3-983MMUSP - MMU Supervisor Protect Data/CodeThis test checks the ability of the MMU to supervisor protect User area memory during Cod

Page 43 - ADR - Memory Addressing

CMMU - Cache and Memory Management Unit3-993If during the test an unexpected exception occurs, the test will service it and display the exception info

Page 44 - ALTS - Alternating Ones/Zeros

Diagnostic Tests3-1003If an unexpected exception is taken, the following message appears:Unsolicited Exception: Program Counter ________

Page 45 - BTOG - Bit Toggle

CMMU - Cache and Memory Management Unit3-1013MMUSPF - MMU Segment/Page Fault Data/CodeThis test checks the ability of the MMU to deny access to a root

Page 46 - Command Input

List of Figures 172Bug Start-up Flow (Sheet 1 of 3) 1-10

Page 47 - CODE - Code Execution/Copy

Diagnostic Tests3-1023MessagesIf the memory range is less than $32000 bytes, the following message appears:Insufficient Amount of Memory to Perform Te

Page 48 - PATS - Data Patterns

CMMU - Cache and Memory Management Unit3-1033If an unexpected exception is taken, the following message appears:Unsolicited Exception: Program

Page 49

Diagnostic Tests3-1043MMUUC - MMU User CodeThis test checks the ability of the MMU to execute instructions in User mode. The test runs as follows:1. T

Page 50

CMMU - Cache and Memory Management Unit3-105317. Using the logical address, the instruction in test memory is executed. 18. A trap always true instruc

Page 51 - PERM - Permutations

Diagnostic Tests3-1063On receipt of an unexpected access exception, the following message appears:Bus Error Information: Address ____

Page 52 - QUIK - Quick Write/Read

CMMU - Cache and Memory Management Unit3-1073MMUUD - MMU User DataThis test checks the ability of the MMU to access data in User mode. The test runs a

Page 53 - REF - Memory Refresh Testing

Diagnostic Tests3-108317. A trap always true instruction (vector 7) is executed to return the MPU to the supervisor mode. 18. The MMU Fault/Status reg

Page 54

CMMU - Cache and Memory Management Unit3-1093On receipt of an unexpected access exception, the following message appears: Bus Error Information:

Page 55 - RNDM - Random Data

Diagnostic Tests3-1103MMUWP - MMU Write ProtectThis test checks the ability of the MMU to write protect memory using the appropriate bits in the Page

Page 56 - RTC - MK48T58 Real Time Clock

CMMU - Cache and Memory Management Unit3-1113If during the test an unexpected exception occurs, the test will service it and display the exception inf

Page 57 - ADR - NVRAM Addressing

xv List of Tables DRAM and SRAM Base Addresses 1-3General Purpose Software-Readable Header Jumper Settings 1-6Diagnostic Commands 2-2Diagnostic Comma

Page 58

Diagnostic Tests3-1123On receipt of an access exception, the following message appears: Bus Error Information: Address ________

Page 59 - CLK - Check Real Time Clock

CMMU - Cache and Memory Management Unit3-1133TTRSC - TTR Supervisor CodeThis test checks the ability of the code Transparent Translation Register to e

Page 60

Diagnostic Tests3-1143On receipt of an access exception, the following message appears: Bus Error Information: Address ________

Page 61 - RAM - Battery Backed-Up SRAM

CMMU - Cache and Memory Management Unit3-1153TTRSD - TTR Supervisor DataThis test checks the ability of the data Transparent Translation Register to a

Page 62 - MCC - Memory Controller Chip

Diagnostic Tests3-1163On receipt of an access exception, the following message appears:Bus Error Information: Address ________

Page 63

CMMU - Cache and Memory Management Unit3-1173TTRUC - TTR User CodeThis test checks the ability of the code Transparent Translation Register to execute

Page 64 - ACCESSA - Device Access

Diagnostic Tests3-1183MessagesIf the memory range is less than $32000 bytes, the following message appears:Insufficient Amount of Memory to Perform Te

Page 65 - ACCESSB - Register Access

CMMU - Cache and Memory Management Unit3-1193TTRUD - TTR User DataThis test checks the ability of the data Transparent Translation Register to access

Page 66 - ADJ - Prescaler Clock Adjust

Diagnostic Tests3-1203MessagesIf the memory range is less than $32000 bytes, the following message appears: Insufficient Amount of Memory to Perform T

Page 67 - FAST - FAST Bit

CMMU - Cache and Memory Management Unit3-1213TTRWP - TTR Write Protect - TTRThis test checks the ability to write protect memory using the appropriate

Page 69 - PCLK - Prescaler Clock

Diagnostic Tests3-1223MessagesIf test pattern is written to memory but no data fault exception occurs, the following message appears:Access Fault Exce

Page 70 - DRAM - DRAM Refresh Timing

3VME2 - VME Interface ASICs3-1233Diagnostic TestsVME2 - VME Interface ASICsThe VME2 tests check the VMEchip2 interface ASICs. The tests are listed in

Page 71 - A - Timer Counter

Diagnostic Tests3-1243Configuration ParametersYou may set the following parameters with the CF command (the default values are given):Prescaler Clock A

Page 72

VME2 - VME Interface ASICs3-1253REGA - Register AccessThis test verifies that the registers at offsets 0 through 84 can be read accessed. The read acc

Page 73 - B - Timer Free-Run

Diagnostic Tests3-1263REGB - Register Walking BitThis test verifies that certain bits in the VMEchip2 ASIC user registers can be set independently of

Page 74 - C - Timer Clear on Compare

VME2 - VME Interface ASICs3-1273If a bit in the LCSR fails to respond properly to the walking bit algorithm, the following message appears:regvrf: bit

Page 75 - D - Timer Overflow Counter

Diagnostic Tests3-1283SWIA - Software Interrupts (Polled Mode)This test verifies that all software interrupts (1 through 7) can be generated and that

Page 76 - E - Timer Interrupts

VME2 - VME Interface ASICs3-1293If the interrupt status bit does not clear, the following message appears:Interrupt Status Bit did not clear Status: E

Page 77

Diagnostic Tests3-1303SWIB - Software Interrupts (Processor Interrupt Mode)This test verifies that all software interrupts (levels 1 through 7) can be

Page 78 - VBR - Vector Base Register

VME2 - VME Interface ASICs3-1313If the programmed interrupt does not occur, the following message appears:Software Interrupt did not occur:Status: Exp

Page 79

1 1-1 1General Information Description of 172Bug 172Bug is a member of the M68000 firmware family. It is implemented on the MVME172 series of MC68060

Page 80

Diagnostic Tests3-1323SWIC - Software Interrupts PriorityThis test verifies that all software interrupts (1 through 7) occur in the priority set by th

Page 81

VME2 - VME Interface ASICs3-1333If, after receiving an interrupt, the interrupt status cannot be negated by writing the interrupt clear register, the

Page 82 - MCECC - ECC Memory Board

Diagnostic Tests3-1343TACU - Timer Accuracy TestThis test performs a four-point verification of the VMEChip2 ASIC timer and prescaler circuitry using

Page 83

VME2 - VME Interface ASICs3-1353If the prescaler calibration register does not contain one of four legal MPU clock calibration values, the following m

Page 84 - CBIT - Check-Bit DRAM

Diagnostic Tests3-1363TMRA, TMRB - Tick Timer IncrementThese tests verify that the Tick Timer 1 (or Timer 2) Counter Register can be set to 0, and, th

Page 85

VME2 - VME Interface ASICs3-1373TMRC - Prescaler Clock AdjustThis test proves that the Prescaler Clock Adjust register can vary the period of the tick

Page 86 - EXCPTN - Exceptions

Diagnostic Tests3-1383TMRD, TMRE - Tick Timer No Clear On CompareThese tests verify the Tick Timer 1 (or Timer 2) No Clear On Compare mode. Use TMRD t

Page 87 - MBE - Multi-Bit-Error

VME2 - VME Interface ASICs3-1393MessagesIf the test fails, one of the following messages appears: Tick Timer ___: Counter did not clear. Timer Counter

Page 88 - SBE - Single-Bit-Error

Diagnostic Tests3-1403TMRF, TMRG - Tick Timer Clear On CompareThese tests verify the Tick Timer 1 (or Timer 2) Clear On Compare mode. Use TMRF to test

Page 89 - SCRUB - Scrubbing

VME2 - VME Interface ASICs3-1413MessagesIf the test fails, one of the following messages appears: Tick Timer ____: Counter did not clear.Timer Counter

Page 90

General Information1-21 you have access to the debugger commands only. Switch to the diagnostics by entering the debugger SD (Switch directories) c

Page 91

Diagnostic Tests3-1423TMRH, TMRI - Overflow CounterThese tests verify that the Tick Timer 1 (or Timer 2) Overflow Counter accumulates a count of timer

Page 92

VME2 - VME Interface ASICs3-1433TMRJ - Watchdog Timer CounterThis test verifies the watchdog timer to ensure functionality at all programmable timing

Page 93 - 172-Diag> CMMU CCHCODE

Diagnostic Tests3-1443TMRK - Watchdog Timer Board FailThis test verifies the watchdog timer in board fail mode by setting up a watchdog timeout and ve

Page 94

3LANC - LAN Coprocessor3-1453Diagnostic TestsLANC - LAN CoprocessorThe LANC tests check the Local Area Network Coprocessor (Intel 82596). The tests ar

Page 95 - CCHCPYB - Cache Copyback

Diagnostic Tests3-1463checking, short frame detection, and automatic length-field handling. The 82596 supports serial data rates up to 20MB per second

Page 96

LANC - LAN Coprocessor3-1473CST - Chip Self TestThis test verifies that the 82596 self-test mode (command) can be executed, and also verifies that the

Page 97

Diagnostic Tests3-1483DIAG - Diagnose Internal HardwareThis test verifies that the Diagnose command of the 82596 can be executed, and that an error-fr

Page 98 - CCHSC - Cache Supervisor Code

LANC - LAN Coprocessor3-1493switches from 01111111111 to 10000000000, and the collision counter (4 bits) wraps from all ones to all zeros. 6. Phase 1

Page 99

Diagnostic Tests3-1503DUMP - Dump Configuration/RegistersThis test verifies that the Dump command of the 82596 can be executed, and that an error free

Page 100 - Diagnostic Tests

LANC - LAN Coprocessor3-1513ELBC - External Loopback CableThis test verifies that the 82596 can be operated with the External Loopback and with the LP

Page 101

Memory Requirements1-31 172Bug requires 2.25KB of NVRAM for storage of board configuration, communication, and booting parameters. This storage area

Page 102

Diagnostic Tests3-1523The STATUS-Bits (the hex value represents a bit sting, big endian) indicate the type of error: If the data receive timeout (four

Page 103

LANC - LAN Coprocessor3-1533The STATUS-Bits (the hex value represents a bit sting, big endian) indicate the type of error:If the receive data count an

Page 104 - CCHSD - Cache Supervisor Data

Diagnostic Tests3-1543ELBT - External Loopback TransceiverThis test verifies that the 82596 can be operated with the External Loopback and with the LP

Page 105

LANC - LAN Coprocessor3-1553The STATUS-Bits (the hex value represents a bit sting, big endian) indicate the type of error: If the data receive timeout

Page 106

Diagnostic Tests3-1563The STATUS-Bits (the hex value represents a bit sting, big endian) indicate the type of error:If the receive data count and the

Page 107

LANC - LAN Coprocessor3-1573ILB - Internal LoopbackThis test verifies that the 82596 can be operated in the Internal Loopback mode. The test sets up a

Page 108

Diagnostic Tests3-1583The STATUS-Bits (the hex value represents a bit sting, big endian) indicate the type of error: If the data receive timeout (four

Page 109

LANC - LAN Coprocessor3-1593The STATUS-Bits (the hex value represents a bit sting, big endian) indicate the type of error:If the receive data count an

Page 110

Diagnostic Tests3-1603IRQ - Interrupt RequestThis test verifies that the 82596 can assert an interrupt request to the MPU. The 82596 has only one line

Page 111 - 172-Diag> CMMU CCHTTM

LANC - LAN Coprocessor3-1613MON - Monitor (Incoming Frames) ModeThis utility monitors activities on the LAN. It instructs the 82596 to monitor all inc

Page 112

Notice While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissi

Page 113 - CCHUC - Cache User Code

General Information1-41 172Bug Implementation Language The C programming language is used for most 172Bug modules. The CPU-specific low-level hardwar

Page 114

Diagnostic Tests3-1623TDF -Time Domain ReflectometryThis test verifies that Time Domain Reflectometry (TDR) can be executed, and that an error free com

Page 115

LANC - LAN Coprocessor3-1633expires. This is the normal case and indicates that there is no problem on the link. The distance to the cable failure can

Page 116

Diagnostic Tests3-1643LANC Test Group Error MessagesThe following error messages may apply to any of the LANC tests:Table 3-9. LANC Error MessagesMes

Page 117

LANC - LAN Coprocessor3-1653LANC Initialization Error:LANC Command Unit Interrupt Acknowledge Command Completion Time-Out The command timed out.During

Page 118

Diagnostic Tests3-1663LANC Command Unit Interrupt(s) Pending The command unit has pending interrupt requests.Prior to issuing a command to the Command

Page 119 - CCHUD - Cache User Data

LANC - LAN Coprocessor3-1673LANC Command Unit Interrupt Acknowledge Command Completion Time-Out The interrupt acknowledge timeout expired.Once the app

Page 120

Diagnostic Tests3-1683Configure Command Completion Status Error:OK-Bit =0, ABORT-Bit =0 An error occurred in completing the command.Upon completion of

Page 121

3NCR - NCR 53C710 SCSI I/O Processor3-1693Diagnostic TestsNCR - NCR 53C710 SCSI I/O ProcessorThe NCR tests check the NCR 53C710 SCSI I/O Processor. Th

Page 122

Diagnostic Tests3-1703ACC1 - Device AccessThis test verifies the basic ability to access the NCR 53C710 device. 1. All device registers are accessed (

Page 123

NCR - NCR 53C710 SCSI I/O Processor3-1713Note All data is hexadecimal. The Access Fault Information is only displayed if the exception was an Access F

Page 124

Installation1-51400/500-Series ModulesAs delivered, 172Bug is installed in and executes out of the lower 512KB of a 28F016SA Flash memory device. This

Page 125

Diagnostic Tests3-1723ACC2 - Register AccessThis test verifies the basic ability to access the NCR 53C710 registers by checking the state of the regis

Page 126

NCR - NCR 53C710 SCSI I/O Processor3-1733DMA Next Address Error: Address =________, Expected =________, Actual =________ Register Access Error: Bus Er

Page 127

Diagnostic Tests3-1743DFIFO - DMA FIFOThis tests verifies the ability to write data into the DMA FIFO and retrieve it in the same order as written. Th

Page 128

NCR - NCR 53C710 SCSI I/O Processor3-1753IRQ - InterruptsThis test verifies that level 0 interrupts will not generate an interrupt, but will set the a

Page 129

Diagnostic Tests3-1763Interrupt Status bit did not set Status: Expected =__, Actual =__ Vector: Expected =__, Actual =__ State : IRQ Level =_, VBR =__

Page 130 - MMUSC - MMU Supervisor Code

NCR - NCR 53C710 SCSI I/O Processor3-1773Bus Error Information: Address ________ Data ________ Access S

Page 131

Diagnostic Tests3-1783LPBK - LoopbackThis test checks the Input and Output Data Latches and performs a selection. The 53C710 executes initiator instru

Page 132

NCR - NCR 53C710 SCSI I/O Processor3-1793SCRIPTS - SCRIPTS ProcessorThis test initializes the test structures and makes use of the diagnostic register

Page 133 - MMUSD - MMU Supervisor Data

Diagnostic Tests3-1803validity is the ÒByte CountÓ during test structures initialization. 7. The ÒMemory MoveÓ SCRIPT copies the specified number of b

Page 134

NCR - NCR 53C710 SCSI I/O Processor3-1813SCSI Status Zero Reg. set during single step Address =________, Expected =__, Actual =__ Test Timeout during:

Page 135

General Information1-61J21 pins 7 and 8, the address spaces of the EPROM and Flash are swapped. You can optionally load the 172Bug firmware to Flash m

Page 136

Diagnostic Tests3-1823SFIFO - SCSI FIFOThis procedure tests the basic ability to write data into the SCSI FIFO and retrieve it in the same order as wr

Page 137

3IPIC - IndustryPack Interface Controller3-1833Diagnostic TestsIPIC - IndustryPack Interface ControllerThe IPIC tests check the IndustryPack Interface

Page 138

Diagnostic Tests3-1843ACCESSA - Read Internal RegistersThis test verifies that all of the IP2 chip ASICs internal registers can be read. It does so by

Page 139 - 172-Diag> CMMU MMUSPF

IPIC - IndustryPack Interface Controller3-1853ACCESSB - Write to Internal RegistersThis test verifies that internal registers of the IP2 chip ASIC can

Page 140

Diagnostic Tests3-1863INRPT - Interrupt Control RegistersThis test verifies that the bits in the IP2 chip Interrupt Control Registers are functioning

Page 141

IPIC - IndustryPack Interface Controller3-1873IPIC Error MessagesThe following table lists the IPIC test group error messages:Table 3-12. IPIC Error

Page 142 - MMUUC - MMU User Code

Diagnostic Tests3-1883Status: Expected =e, Actual =rThe expected and actual contents of the Interrupt Control Register under test after certain failur

Page 143 - 172-Diag> CMMU MMUUC

3SCC - Z85230 Serial Communication Controller3-1893Diagnostic TestsSCC - Z85230 Serial Communication ControllerThe SCC tests check the Z85230 Serial C

Page 144

Diagnostic Tests3-1903used for the BAUDS and ILPBCK test suites. The External-Loopback/Modem-Control Port Mask is only used for the ELPBCK and MDMC te

Page 145 - MMUUD - MMU User Data

SCC - Z85230 Serial Communication Controller3-1913ACCESS - SCC Device/Register AccessThis test performs a write/read test on two registers in the Z85C

Page 146

Installation1-71172-Bug> PFLASH FF80000:800000 FFA00000Then reinstall the jumper on header J21 pins 7 and 8 Refer to the PFLASH command in the 172B

Page 147

Diagnostic Tests3-1923IRQ - SCC Interrupt RequestThis test verifies that the Z85C230 can generate interrupts to the local processor. This is done usin

Page 148 - MMUWP - MMU Write Protect

SCC - Z85230 Serial Communication Controller3-1933BAUDS - SCC Baud RatesThis test transmits 256 characters at various baud rates. The data is received

Page 149

Diagnostic Tests3-1943ELPBCK - SCC External LoopbackThis test transmits 256 characters at 38,400 baud. The data is received and compared. If any proto

Page 150

SCC - Z85230 Serial Communication Controller3-1953ILPBCK - SCC Internal LoopbackThis test transmits 256 characters at 38,400 baud. The data is receive

Page 151 - TTRSC - TTR Supervisor Code

Diagnostic Tests3-1963MDMC - SCC Modem ControlThis test verifies that the Z85C230 can negate and assert selected modem control lines and that the appr

Page 152

SCC - Z85230 Serial Communication Controller3-1973SCC Error MessagesThe following table lists the SCC test group error messages:Table 3-14. SCC Error

Page 153 - TTRSD - TTR Supervisor Data

Diagnostic Tests3-1983Receiver Ready (Character Available) Time-OutSCC Base Address =________, Channel =__Baud Rate =____The receiver has not received

Page 154

3FLASH - Flash Memory Tests3-1993Diagnostic TestsFLASH - Flash Memory TestsThe FLASH tests check the Intel 28F016SA FLASHFILETM Flash memory devices.

Page 155 - TTRUC - TTR User Code

Diagnostic Tests3-2003Configuration ParametersYou may set the following parameters with the CF command (the default values are shown):Flash Device Test

Page 156

FLASH - Flash Memory Tests3-2013ERASE - Erase Flash MemoryThe ERASE test erases Flash memory. This test operates on a single block at a time within a

Page 157 - TTRUD - TTR User Data

General Information1-81EPROM/Flash Header Jumper SettingsAs received from the factory, the 200/300-Series module has jumpers installed on EPROM/Flash

Page 158

Diagnostic Tests3-2023FILL - Fill Flash MemoryThe FILL test fills Flash memory. This test operates on each individual block at a time, within each dev

Page 159 - 172-Diag> CMMU TTRWP

FLASH - Flash Memory Tests3-2033PATS - Flash PatternsThe PATS test writes and reads various data patterns in Flash memory. This test operates on each

Page 160

Diagnostic Tests3-2043FLASH Test Group Error MessagesThe following error messages apply to the FLASH tests:Table 3-16. FLASH Error MessagesMessage Ca

Page 161 - VME2 - VME Interface ASICs

FLASH - Flash Memory Tests3-2053Data Miscompare Error:Address =________ Expected =__ Actual = __The data read from a Flash memory device failed to mat

Page 163 - REGA - Register Access

44-14172Bug EnvironmentIntroductionThe parameters that affect board and 172Bug operation are stored in the NVRAM. The board information block operatin

Page 164 - REGB - Register Walking Bit

172Bug Environment4-24IndustryPack A Board Identifier = " " IndustryPack A (PWA) Serial Number = " " In

Page 165

ENV - Set Environment4-34ENV - Set EnvironmentThe ENV command allows you to interactively view and configure all 172Bug operational parameters. Refer

Page 166

172Bug Environment4-44Probe System for Supported I/O Controllers [Y/N] = Y?Negate VMEbus SYSFAIL* Always [Y/N] = N?Local SCSI Bus Reset on Debugger Se

Page 167

ENV - Set Environment4-54Auto Boot Enable [Y/N] = N? Auto Boot at power-up only [Y/N] = Y? Auto Boot Controller LUN = 00? The boot controller Logic

Page 168

Start-up1-91Start-upWhen 172Bug is brought up at either power up or RESET, the following is displayed on the system console: Copyright Motorola Inc. 1

Page 169

172Bug Environment4-64ROM Boot at power-up only [Y/N] = Y? ROM Boot Enable search of VMEbus [Y/N] = N?ROM Boot Abort Delay = 0? The time in secon

Page 170

ENV - Set Environment4-74Network Auto Boot Controller LUN = 00? The boot controller Logical Unit Number. Refer to Appendix G in the Debugging Package

Page 171

172Bug Environment4-84Memory Search Increment Size = 00010000? The offset to the location of the Bug work page for multi-CPU use. This must be a m

Page 172 - TACU - Timer Accuracy Test

ENV - Set Environment4-94Memory Size Ending Address = 08000000? The Ending Address for memory sizing. This is the calculated size of local memor

Page 173

172Bug Environment4-104Size of ECC Memory Board #1 = 00000000? The size of the second ECC type memory mezzanine. The default is the calculated size

Page 174

ENV - Set Environment4-114Slave Address Translation Address #1 = 00000000? The base address of local resource that is associated with the starting and

Page 175 - TMRC - Prescaler Clock Adjust

172Bug Environment4-124Master Enable #1 [Y/N] = Y? Master Starting Address #1 = 01000000 The base address of the VMEbus resource that is accessible fr

Page 176

ENV - Set Environment4-134Master Enable #3 [Y/N] = Y? Master Starting Address #3 = 00800000? The base address of the VMEbus resource that is accessib

Page 177 - Messages

172Bug Environment4-144Master Address Translation Select #4 = 00000000? A mask that deÞnes which bits of the address are signiÞcant. A 1 indicates a s

Page 178

ENV - Set Environment4-154VMEC2 GCSR Board Base Address = 00? The base address ($FFFFCCx0) in Short I/O for the board.VMEbus Global Time Out Code =

Page 179

General Information1-101Figure 1-1. 172Bug Start-up Flow (Sheet 1 of 3)CONFIGURE HARDWARE PERROM DEFAULT PARAMETERSCLEAR DEBUGGER WORK PAGESET POWER-

Page 180 - TMRH, TMRI - Overflow Counter

172Bug Environment4-164IP D/C/B/A General Control = 00000000? This deÞnes the general control requirements for the IP modules: IP D/C/B/A Interrup

Page 181 - TMRJ - Watchdog Timer Counter

ENV - Set Environment4-174Saving ENV Parameter SettingsBefore ENV parameters are saved in the NVRAM, a warning message will appear if the any of envir

Page 182

172Bug Environment4-184

Page 183 - LANC - LAN Coprocessor

AA-1ARelated DocumentationRelated DocumentationThe following publications are applicable to 172Bug and may provide additional helpful information. Tho

Page 184

Related DocumentationA-2Aof a manual). A supplement bears the same number as a manual but has a suffix such as Ò2A1Ó (the first supplement to the seco

Page 185 - CST - Chip Self Test

IN-3IndexNumerics172-Bug> prompt 1-1172-Diag> prompt 1-128F016SA Flash memory 3-19948T58 RTC 3-1853C710 SCSI 3-16982596 LANC chip 3-14585230 SCC

Page 186

IndexIN-4INDEXCache User Code Cache Inhibit -CCHUCCI 3-78Cache User Data - CCHUD 3-81Cache User Data Cache Inhibit -CCHUDCI 3-84Cache User Data Write

Page 187 - OK-Bit =0, F(ail)-Bit =1

IN-5INDEXDEM 2-4description 1-1Device Access - ACC1 3-170DFIFO test (NCR) 3-174DIAG 3-148DIAG test (LANC) 3-148Diagnose Internal Hardware (DIAG)3-148d

Page 188

IndexIN-6INDEXGeneral Purpose Software-ReadableHeader 1-5, 1-6GPI3200/300-series modules 1-5400/500-series modules 1-7GPI3 to GPI0 1-5group address (G

Page 189

IN-7INDEXliterature, related A-1LN 2-9Local Parity Memory Error Detection -PED 3-11location of 172Bug 1-4200/300-series 1-4400/500-series 1-5longword

Page 190 - RECEIVE Status Error:

Start-up1-111Figure 1-1. 172Bug Start-up Flow (Sheet 2 of 3) PROBE SYSTEM FOR SUPPORTEDDISK/TAPE CONTROLLERSDISPLAY WARNING MESSAGE OF LOCALMEMORY CO

Page 191 - Expected =05EA, Actual =003C

IndexIN-8INDEXmulti-bit-error 3-49Multi-Bit-Error - MBE 3-49NNCR 53C710 SCSI I/O Processor (NCR)tests 3-169NCR testsACC1 3-170ACC2 3-172DFIFO 3-174IRQ

Page 192

IN-9INDEXSSBE 3-50SBE test (MCECC) 3-50SCC Baud Rates - BAUDS 3-193SCC Device/Register Access - ACCESS3-191SCC Error Messages 3-197SCC External Loopba

Page 193

IndexIN-10INDEXTimer Counters test (MCC) - TMRnA3-33Timer Free-Run test (MCC) - TMRnB3-35Timer Interrupts tests (MCC) - TMRnE3-38Timer Overflow Counte

Page 194

IN-11INDEXwrite to IPIC registers - ACCESSB 3-185write/read 3-14XXON/XOFF 1-8ZZ85230 tests 3-189ZE 2-7Zero Pass Count - Command ZP 2-7ZP 2-7

Page 195 - ILB - Internal Loopback

General Information1-121Figure 1-1. 172Bug Start-up Flow (Sheet 3 of 3) 5NOYESNEGATE SYSFAILATTEMPT BOOTSYSTEMNOSYSFAIL NEGATE FLAG TRUE?BOOT LOADNOY

Page 196

22-12Using the DiagnosticsIntroductionThis chapter contains information about entering the 172Bug diagnostic commands and tests. The diagnostic comman

Page 197

Preface The 172Bug Diagnostics UserÕs Manual provides information on using the 172Bug diagnostics. This edition (172DIAA/UM1) applies to all versio

Page 198 - IRQ - Interrupt Request

Using the Diagnostics2-22For instance, to invoke the command RTC CLK after the command RAM ADR, you may enter RAM ADR ; RTC CLK on the command line. T

Page 199 - 172-Diag>LANC MON

Diagnostic Commands2-32AEM - Append Error Messages ModeThe AEM command allows you to accumulate error messages in the internal error message buffer of

Page 200 - TDF -Time Domain Reflectometry

Using the Diagnostics2-42DE - Display Error CountersThe DE command displays all errors in the test error counters. Each test or command in the diagnos

Page 201

Diagnostic Commands2-52To view a description of an individual test, enter the full test name. For example, to view information on the RAM Code Executi

Page 202 - LANC test group conÞguration

Using the Diagnostics2-62HEX - Interactive HelpThe HEX command enters a continuous interactive mode of the HE command. When you execute HEX, the quest

Page 203 - LANC while

Diagnostic Commands2-72ST - Self TestThe ST command runs the system self tests that the bug runs at system start-up. The command HE ST lists the test

Page 204

Using the Diagnostics2-82Test PrefixesThe tests execution can be modified with the prefixes, which are listed in Table 2-2 and are described on the fol

Page 205

Test Prefixes2-92LE - Loop-On-ErrorThe LE prefix causes a test to be re-executed if the previous execution returns a failure status. To break a loop,

Page 206

Using the Diagnostics2-102

Page 207

33-13Diagnostic TestsIntroductionThis chapter contains detailed descriptions of the 172Bug diagnostic tests. The test sets are shown in Table 3-1.Tabl

Page 208 - ACC1 - Device Access

Conventions The following conventions are used in this document: bold is used for user input that you type just as it appears. Bold is also used for

Page 209

Diagnostic Tests3-23Running the TestsThe diagnostic test commands consist of a test group name and a test name. To run a test, enter the test group na

Page 210 - ACC2 - Register Access

3RAM - Local RAM, SRAM - Static RAM3-33Diagnostic TestsRAM - Local RAM, SRAM - Static RAMThe RAM tests check the local RAM and the SRAM tests check th

Page 211

Diagnostic Tests3-43Starting/Ending Address Enable [Y/N] =N ?Starting Address =00000000 ? (FFE00000 for SRAM)Ending Address =01000000 ? (FFE1FFFC fo

Page 212 - DFIFO - DMA FIFO

RAM - Local RAM, SRAM - Static RAM3-53ADR - Memory AddressingThe ADR test verifies addressing of memory in the range specified by the configuration pa

Page 213 - IRQ - Interrupts

Diagnostic Tests3-63ALTS - Alternating Ones/ZerosThis test verifies addressing of memory in the range specified by the configuration parameters for th

Page 214

RAM - Local RAM, SRAM - Static RAM3-73BTOG - Bit ToggleThis test toggles the bits in the memory range specified by the configuration parameters for th

Page 215

Diagnostic Tests3-83Command Input172-Diag>RAM BTOG or 172-Diag>SRAM BTOG MessagesIf the test fails, the following message appears:Data Miscompa

Page 216 - LPBK - Loopback

RAM - Local RAM, SRAM - Static RAM3-93CODE - Code Execution/CopyThis test copies test code to a memory location and executes the code. The test code c

Page 217 - SCRIPTS - SCRIPTS Processor

Diagnostic Tests3-103PATS - Data PatternsThis test writes and reads a series of test patterns to the test memory range. Each location is filled with a

Page 218

RAM - Local RAM, SRAM - Static RAM3-113PED - Local Parity Memory Error DetectionThis test checks memory parity for memory range and address increment

Page 219

Manual Terminology Throughout this manual, a convention has been maintained whereby data and address parameters are preceded by a character which spe

Page 220 - SFIFO - SCSI FIFO

Diagnostic Tests3-123If no exception occurred when data with bad parity was read, the following message appears:RAM/PED Test Failure Data: Parity Erro

Page 221

RAM - Local RAM, SRAM - Static RAM3-133PERM - PermutationsThis test verifies that the memory in the test range can accommodate 8-, 16-, and 32-bit wri

Page 222

Diagnostic Tests3-143QUIK - Quick Write/ReadThis test writes and reads a pair of test patterns, 0 and $FFFFFFFF, to the test memory range. Each pass o

Page 223 - 172-Diag>IPIC ACCESSB

RAM - Local RAM, SRAM - Static RAM3-153REF - Memory Refresh TestingThis test verifies memory locations after a refresh wait cycle. The memory range an

Page 224

Diagnostic Tests3-163 or RAM/REF Test Failure Data: RTC is in write mode, invoke SET command. or RAM/REF Test Failure Data: RTC is in read mode, invok

Page 225 - IPIC Error Messages

RAM - Local RAM, SRAM - Static RAM3-173RNDM - Random DataThis test writes and verifies a random test patterns and the complement of the test pattern.

Page 226 - Message Cause

3Diagnostic Tests3-183Diagnostic TestsRTC - MK48T58 Real Time ClockThe RTC tests check the NVRAM, SRAM, and clock portions of the MK48T58 ÒZeropowerÓ

Page 227

RTC - MK48T58 Real Time Clock3-193ADR - NVRAM AddressingThis test checks the proper addressing of the MK48T58 NVRAM. The test runs as follows:1. The N

Page 228

Diagnostic Tests3-203If a pattern ÒbÓ write affects any NVRAM location other than the resultant address, the following message appears:Data Verify Err

Page 229 - 172-Diag>SCC ACCESS

RTC - MK48T58 Real Time Clock3-213CLK - Check Real Time ClockThis test verifies that the RTC is operating. It does not check clock accuracy. This test

Page 230 - IRQ - SCC Interrupt Request

Notice of Copyright The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., 1995, and may

Page 231 - BAUDS - SCC Baud Rates

Diagnostic Tests3-223If the seconds register changes before the full count of MPU loops is executed, the following message appears: RTC did not freeze

Page 232

RTC - MK48T58 Real Time Clock3-233RAM - Battery Backed-Up SRAMThis test performs a data test on each SRAM location of the MK48T58 RAM. RAM contents ar

Page 233 - 172-Diag>SCC ILPBCK

3Diagnostic Tests3-243Diagnostic TestsMCC - Memory Controller ChipThe MCC tests check the Memory Controller chip, the MC2 chip, which is one of the AS

Page 234 - MDMC - SCC Modem Control

MCC - Memory Controller Chip3-253Configuration ParametersThere are no configuration parameters for the MCC test group.Bus Error and Unsolicited Excepti

Page 235 - SCC Error Messages

Diagnostic Tests3-263ACCESSA - Device AccessThis test verifies that the MCC register set can be accessed (read) on byte, word, and long word boundarie

Page 236

MCC - Memory Controller Chip3-273ACCESSB - Register AccessThis test checks the device data lines by successive writes and reads to all tick timers com

Page 237 - FLASH - Flash Memory Tests

Diagnostic Tests3-283ADJ - Prescaler Clock AdjustThis test verifies that the Prescaler Clock Adjust Register can vary the period of the Tick Timer inp

Page 238

MCC - Memory Controller Chip3-293FAST - FAST BitThis test verifies the FAST/SLOW access time to the BBRAM. This is accomplished by using Tick Timer #1

Page 239 - ERASE - Erase Flash Memory

Diagnostic Tests3-303MPUCS - MPU Clock SpeedThis test verifies that the calculated MPU clock speed matches both the version register of the MCC and th

Page 240 - FILL - Fill Flash Memory

MCC - Memory Controller Chip3-313PCLK - Prescaler ClockThis test verifies the accuracy of the Prescaler Clock. This is accomplished by using a constan

Page 241 - PATS - Flash Patterns

Safety SummarySafety Depends On You The following general safety precautions must be observed during all phases of operation, service, andrepair of t

Page 242

Diagnostic Tests3-323DRAM - DRAM Refresh TimingThis test verifies that when the refresh rate is changed via the Bus Clock Register, the total time of

Page 243

MCC - Memory Controller Chip3-333TMRnA - Timer CounterThese tests verify that the Tick Timer Counters are operational. Each test runs as follows:1. Th

Page 244

Diagnostic Tests3-343Counter did not incrementAddress =________, Expected =________, Actual =________ Timeout waiting for Counter to incrementAddress

Page 245 - 4172Bug Environment

MCC - Memory Controller Chip3-353TMRnB - Timer Free-RunThese test verify that the Tick Timer Compare Registers are operational. Each test runs as foll

Page 246 - 172Bug Environment

Diagnostic Tests3-363TMRnC - Timer Clear on CompareThese tests verify the Tick TimersÕ Clear on Compare functions. Each test runs as follows:1. The co

Page 247 - ENV - Set Environment

MCC - Memory Controller Chip3-373TMRnD - Timer Overflow CounterThese tests verify the Tick Timers Overflow Counters. Each test runs as follows:1. The t

Page 248 - 172Bug

Diagnostic Tests3-383TMRnE - Timer InterruptsThese tests verify that the Tick Timers can generate interrupts and that the MPU takes the correct vector

Page 249

MCC - Memory Controller Chip3-393Unexpected Vector taken Status: Expected =__, Actual =__ Vector: Expected =__, Actual =__ State : IRQ Level =_, VBR =

Page 250

Diagnostic Tests3-403VBR - Vector Base RegisterThis test verifies that the MCC's Vector Base Register is operational. The register is tested for

Page 251

MCC - Memory Controller Chip3-413WDTMRA - Watchdog Timer CounterThis test verifies that the Watchdog Timer Counter will count and set the correct stat

Page 252

!WARNING This equipment generates, uses, and can radiate electro-magnetic energy. It may cause or be susceptible to electro-magnetic interference (EMI

Page 253

Diagnostic Tests3-423WDTMRB - Watchdog Timer Board FailThis test verifies that the Watchdog Timer will set the Board Fail indicator (FAIL LED and VMEb

Page 254 - VMEbus Interface Parameters

MCC - Memory Controller Chip3-433WDTMRC - Watchdog Timer Local ResetThis test verifies that the Watchdog Timer will generate a local reset upon timing

Page 255

3Diagnostic Tests3-443Diagnostic TestsMCECC - ECC Memory BoardThe MCECC tests check ECC memory devices on the 200/300-Series MVME172. The tests are li

Page 256

MCECC - ECC Memory Board3-453Override default starting/ending addresses (y/n) =n ? This overrides the default address ranges for testing, on a per boa

Page 257

Diagnostic Tests3-463CBIT - Check-Bit DRAMThis test verifies the operation of the check-bit RAM. The test uses the address as the data in the first wo

Page 258

MCECC - ECC Memory Board3-473If there is a check bit memory failure, the following message appears:At: ______, read: ______, should be: ______, (lo

Page 259 - Configuring IndustryPacks

Diagnostic Tests3-483EXCPTN - ExceptionsThis test verifies the ECC boardÕs ability to generate interrupts or bus errors on detecting a memory error. T

Page 260

MCECC - ECC Memory Board3-493MBE - Multi-Bit-ErrorThis test verifies the ECC board's ability to detect multi-bit-errors. It fills a memory area w

Page 261 - Saving ENV Parameter Settings

Diagnostic Tests3-503SBE - Single-Bit-ErrorThis test verifies the ECC board's ability to correct single-bit-errors. It fills a memory area with r

Page 262

MCECC - ECC Memory Board3-513SCRUB - ScrubbingThis test verifies refresh ÒscrubbingÓ of errors from DRAM. It checks the ECC memory board's capabi

Page 263 - ARelated Documentation

Contents Lithium Battery Caution 8Description of 172Bug 1-1Debug and Diagnostic Commands 1-1Memory Requirements 1-2172Bug Implementation 1-4Language

Page 264

Diagnostic Tests3-523If there is a first pass scrubbing failure, the following message appears:Timed out waiting for scrubber to start, bd #_ (status

Page 265 - Numerics

3CMMU - Cache and Memory Management Unit3-533Diagnostic TestsCMMU - Cache and Memory Management UnitThe CMMU tests check the Cache and the Memory Mana

Page 266

Diagnostic Tests3-543Configuration ParametersYou may set the following parameters with the CF command (the default values are shown):Starting/Ending Ad

Page 267

CMMU - Cache and Memory Management Unit3-553CCHCODE - Cache Code Copy/ExecutionThe CCHCODE test checks the ability of the MMU to copy or move instruct

Page 268

Diagnostic Tests3-563MessagesOn receipt of an unexpected access exception, the following message appears:Bus Error Information: Addre

Page 269

CMMU - Cache and Memory Management Unit3-573CCHCPYB - Cache CopybackThe CCHCPYB test checks the ability of the MMU to operate in the Supervisory mode

Page 270

Diagnostic Tests3-583If during the test an unexpected exception occurs, the test will service it and display one or more exception messages.Command In

Page 271

CMMU - Cache and Memory Management Unit3-593If an unexpected exception is taken, the following message appears:Unsolicited Exception: Program C

Page 272

Diagnostic Tests3-603CCHSC - Cache Supervisor CodeThe CCHSC test checks the ability of the MMU to execute cached instructions in the Supervisory mode.

Page 273

CMMU - Cache and Memory Management Unit3-613If a string fails to verify, an error message appears. If a string does not execute or the wrong string ex

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