Motorola CPU32 manuels

Manuels d'utilisation et guides de l'utilisateur pour Processeurs Motorola CPU32.
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Motorola CPU32 Manuel d'utilisateur (646 pages)

marque: Motorola | Catégorie: Processeurs | Taille: 2.28 MB |

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Table des matières

MOTOROLA

2

M68000 FAMILY

2

TABLE OF CONTENTS

3

LIST OF FIGURES

8

LIST OF FIGURES (Concluded)

9

LIST OF TABLES

10

LIST OF TABLES (Continued)

11

SECTION 1

12

INTRODUCTION

12

1.1.3 Program Counter

14

1.3.2 Status Register

21

31 24 23 16

23

ADDRESS BASE ADDRESS MASK

23

1514131211109876 432 0

23

1.4 INTEGER DATA FORMATS

25

1.6.1 Normalized Numbers

29

1.6.2 Denormalized Numbers

29

1.6.3 Zeros

30

1.6.4 Infinities

30

1.6.5 Not-A-Numbers

30

Introduction

31

SECTION 2

42

ADDRESSING CAPABILITIES

42

POINTS TO

46

2.2.18 Immediate Data

60

Addressing Capabilities

63

BR Xn bd Addressing Mode

65

2.5.2 Memory Indirect Modes

66

2.6 OTHER DATA STRUCTURES

69

2.6.1 System Stack

69

2.6.2 Queues

70

SECTION 3

72

INSTRUCTION SET SUMMARY

72

Bit field selection

74

3.1.3 Logical Instructions

79

3.1.6 Bit Field Instructions

81

→ (SSP);

84

Table 3-19. Conditional Tests

90

3.3 INSTRUCTION EXAMPLES

91

3.3.4 Bit Field Instructions

91

3.5.1 Intermediate Result

95

3.5.2 Rounding the Result

96

3.6.2 Conditional Testing

99

Instruction Set Summary

100

Data Type N Z I NAN

100

3.7 INSTRUCTION DESCRIPTIONS

103

SECTION 4

105

INTEGER INSTRUCTIONS

105

Add Decimal with Extend

106

EFFECTIVE ADDRESS

108

MODE REGISTER

108

1514131211109876543210

108

1101 REGISTER OPMODE

108

Add Address

111

(M68000 Family)

112

Add Immediate

113

ADDI Add Immediate ADDI

114

ADDQ Add Quick ADDQ

115

ADDX Add Extended ADDX

117

AND AND Logical AND

119

ANDI AND Immediate ANDI

122

ANDI ANDI

124

Arithmetic Shift ASL, ASR

125

Branch Conditionally Bcc

129

Bcc Branch Conditionally Bcc

130

Test a Bit and Change BCHG

131

Test a Bit and Clear BCLR

134

Integer Instructions

137

BFINS Insert Bit Field BFINS

150

Test Bit Field and Set BFSET

153

BFTST Test Bit Field BFTST

155

BKPT Breakpoint BKPT

157

BRA Branch Always BRA

159

BSET Test a Bit and Set BSET

160

BSR Branch to Subroutine BSR

163

BTST Test a Bit BTST

165

CALLM Call Module CALLM

168

CAS CAS

170

CLR Clear an Operand CLR

177

CMP Compare CMP

179

CMPA Compare Address CMPA

181

CMPI Compare Immediate CMPI

183

CMPM Compare Memory CMPM

185

Signed Divide DIVS, DIVSL

196

Unsigned Divide DIVU, DIVUL

200

EOR Exclusive-OR Logical EOR

204

Exclusive-OR Immediate EORI

206

EORI EORI

208

EXG Exchange Registers EXG

209

Sign-Extend EXT, EXTB

210

JMP Jump JMP

212

JSR Jump to Subroutine JSR

213

Load Effective Address LEA

214

LINK Link and Allocate LINK

215

Logical Shift LSL, LSR

217

MOVEA Move Address MOVEA

223

MOVE MOVE

225

Move 16-Byte Block MOVE16

230

Move Peripheral Data MOVEP

235

MOVEQ Move Quick MOVEQ

238

MULS Signed Multiply MULS

239

MULU Unsigned Multiply MULU

242

Instruction Format:

246

Instruction Fields:

246

NEG Negate NEG

247

NEGX Negate with Extend NEGX

249

NOP No Operation NOP

251

NOT Logical Complement NOT

252

OR Inclusive-OR Logical OR

254

ORI Inclusive-OR ORI

257

ORI ORI

259

PACK Pack PACK

260

Push Effective Address PEA

263

REGISTER ROTATE

265

MEMORY ROTATE

266

Return and Deallocate RTD

270

RTM Return from Module RTM

271

Return from Subroutine RTS

273

SUB Subtract SUB

278

SUBA Subtract Address SUBA

281

SUBI Subtract Immediate SUBI

283

SUBQ Subtract Quick SUBQ

285

Subtract with Extend SUBX

287

Swap Register Halves SWAP

289

Test and Set an Operand TAS

290

TRAP Trap TRAP

292

Trap on Condition TRAPcc

293

TRAPV Trap on Overflow TRAPV

295

TST Test an Operand TST

296

UNLK Unlink UNLK

298

UNPK Unpack BCD UNPK

299

SECTION 5

303

FLOATING POINT INSTRUCTIONS

303

Floating-Point Absolute Value

306

Arc Cosine

310

Floating-Point Add

313

FADD Floating-Point Add FADD

314

FASIN Arc Sine FASIN

316

FATAN Arc Tangent FATAN

319

Floating Point Instructions

323

Floating-Point Compare FCMP

327

FCOS Cosine FCOS

330

FCOSH Hyperbolic Cosine FCOSH

333

Hyperbolic Cosine FCOSH

334

Hyperbolic Cosine FCOSH

335

Decrement, and Branch

336

Floating-Point Divide FDIV

338

DESTINATION

342

FETOXM1 e

345

FETOXM1

345

FGETEXP Get Exponent FGETEXP

348

FGETMAN Get Mantissa FGETMAN

351

FINT Integer Part FINT

354

FLOG10 Log

360

FLOG2 Log

363

FLOGN Log

366

FLOGNP1 Log

369

FLOGNP1

370

FMOD Modulo Remainder FMOD

372

⋅), but all

375

< EA > TO REGISTER

377

REGISTER—TO-MEMORY

380

Move Floating-Point FMOVE

382

System Control Register

382

Move Constant ROM FMOVECR

385

Data Registers

387

Control Registers

393

Floating-Point Multiply FMUL

396

Floating-Point Negate FNEG

400

FNOP No Operation FNOP

404

Arithmetic

406

FREM IEEE Remainder FREM

407

FSCALE Scale Exponent FSCALE

409

FSIN Sine FSIN

420

FSINH Hyperbolic Sine FSINH

427

Floating-Point Subtract FSUB

434

FTAN Tangent FTAN

438

Hyperbolic Tangent FTANH

441

FTENTOX 10

444

FTENTOX

444

FTWOTOX 2

452

FTWOTOX

452

SECTION 6

455

Invalidate Cache Lines

457

Coprocessor

459

Restore Functions

459

Coprocessor Save Function

461

Restore Internal FRESTORE

465

Floating-Point State

465

Move Control Register MOVEC

476

Move Address Space MOVES

478

1111000001001COUNT REGISTER

485

0000000000 MC68851 CONDITION

485

16-BIT DISPLACEMENT

485

1111000000

487

0 0 1 MODE 0 0 MASK FC

487

Flush ATC Entries PFLUSH

489

PFLUSH PFLUSH

492

PFLUSHA PFLUSHA

492

1010000000000000

495

001000R/ W0000 FC

498

SRP, CRP, and TC Registers

502

MMU Status Register

503

TT Registers

504

011000R/W000000000

505

ACx Registers

506

Move PMMU Register PMOVE

507

1111000101

512

PMMU Save Function PSAVE

513

Set on PMMU Condition PScc

516

Test a Logical Address PTEST

517

(MC68030 only)

519

1111000001111 OPMODE

533

Validate a Pointer PVALID

534

Reset External Devices RESET

537

Return from Exception RTE

538

0100111001110010

539

IMMEDIATE DATA

539

SECTION 7

541

CPU32 INSTRUCTIONS

541

Enter Background Mode

544

(CPU32)

544

Low-Power Stop

545

TBLS TBLS

546

TBLU TBLU

551

CPU32 Instructions

556

SECTION 8

557

INSTRUCTION FORMAT SUMMARY

557

Instruction Format Summary

577

X AND BACX REGISTERS

581

TBLU, TBLUN

584

TBLS, TBLSN

584

DATA REGISTER INTERPOLATE

585

FRESTORE

594

FTRAPcc

594

APPENDIX A

597

PROCESSOR INSTRUCTION SUMMARY

597

Processor Instruction Summary

608

Mnemonic Description

608

(Continued)

609

Data Addressing Modes

612

A.2 MC68020 PROCESSORS

613

(Concluded)

615

Addressing Modes Syntax

616

A.3 MC68030 PROCESSORS

617

A.4 MC68040 PROCESSORS

621

A.6 MC68851 COPROCESSORS

627

APPENDIX B

628

Assignment

629

B.2 EXCEPTION STACK FRAMES

630

Frame, Format $4

632

Format $9

633

15 031 24 23 16

639

VERSION $41

639

(RESERVED)

639

APPENDIX C

641

S-RECORD OUTPUT FORMAT

641

C.2 S-RECORD TYPES

642

C.3 S-RECORD CREATION

643

Table C-2. ASCII Code

645

Motorola CPU32 Guide de l'utilisateur (205 pages)

marque: Motorola | Catégorie: Processeurs | Taille: 1.85 MB |

Anglais

Table des matières

Emulation for

2

Motorola CPU32

2

In This Book

5

Registers)

9

Contents

10

Together

11

Updating Firmware

12

Troubleshooting the Emulator

12

Setup Flowchart

18

Emulation Probe

19

CPU32 Emulation 19

20

Chapter 1: Overview

20

Minimum equipment required

21

CPU32 Emulation 21

22

To power on the system

23

To power off the system

23

Connection Sequence

23

Emulation Migration

26

CPU32 Emulation 27

28

28 CPU32 Emulation

29

Serial connection

31

Recommended connection

31

Workstation

32

To obtain an IP address

33

CPU32 Emulation 33

34

34 CPU32 Emulation

35

36 CPU32 Emulation

37

CPU32 Emulation 39

40

See Also

40

To verify LAN communications

42

CPU32 Emulation 43

44

To connect a serial cable

45

HP 16701A expansion frame

50

50 CPU32 Emulation

51

CPU32 Emulation 51

52

6 Reinstall the cover

53

Installing and loading

55

What needs to be installed

56

(HP 16600A/700A)

57

58 CPU32 Emulation

59

Emulator

60

60 CPU32 Emulation

61

1 Open the Workspace window

64

64 CPU32 Emulation

65

Debug port connections

66

8-pin BDM port

68

10-pin BDM port

68

Target V

68

CONFIG2 pin

69

Enabling BDM

69

To test the emulator

69

70 CPU32 Emulation

71

CPU32 Emulation 73

74

1 Turn on the target system

75

Configuring the Emulator

76

Interface

77

To configure using a debugger

79

command will restore

80

80 CPU32 Emulation

81

82 CPU32 Emulation

83

Emulation probe

84

84 CPU32 Emulation

85

To test memory accesses

88

88 CPU32 Emulation

89

EMSIM Registers)

90

The purpose of SIM Registers

91

Configuring the SIM Registers

92

92 CPU32 Emulation

93

CPU32 Emulation 93

94

94 CPU32 Emulation

95

Load Configuration

96

To manually define SIM values

97

SIM registers” on page 95

99

In Commands

100

Registers

102

102 CPU32 Emulation

103

Benefits of using a debugger

105

CPU32 Emulation 105

106

Minimum requirements

107

LAN connection

107

Setting up Debugger Software

108

Port numbers for emulators

109

CPU32 Emulation 109

110

110 CPU32 Emulation

111

1 Telnet to the IP address

112

2 At the prompt, type:

112

at the prompt

112

IP_address

113

CPU32 Emulation 113

114

Compatibility

115

Overview

115

Getting started

115

Start the debugger

117

7 Download the code:

118

To reinitialize the system

122

Error conditions

122

Hills Software, Inc

123

Startup behavior

124

To send commands

131

Download performance

132

Using the Analysis Probe and

134

Emulation Module Together

134

Analyzer

137

CPU32 Emulation 137

138

To minimize the “skid” effect

139

Emulation Module

142

Group Run

143

Debuggers can cause triggers

144

144 CPU32 Emulation

145

CPU32 Emulation 145

146

146 CPU32 Emulation

147

Emulation Probe Firmware

150

Emulation Module Firmware

151

CPU32 Emulation 151

152

Chapter 9: Updating Firmware

152

See also

152

152 CPU32 Emulation

153

Processor compatibility

155

BNC, labeled TRIGGER OUT

156

BNC, labeled BREAK IN

156

Communications

156

Accessory Power Out

156

Power Supply

156

Electrical Characteristics

157

158 CPU32 Emulation

159

Troubleshooting Guide

162

Status Lights

163

Emulation Probe Status Lights

164

Emulator Built-in Commands

166

To use the built-in commands

168

Problems with Configuration

171

If boot area accesses fail

172

Module Only)

173

Probe Only)

178

To run the power up self test

183

184 CPU32 Emulation

185

CPU32 Emulation 185

186

5 Enter the pv 1 command

187

CPU32 Emulation 187

188

188 CPU32 Emulation

189

TEST 7: I2C Test

190

TEST 8: Data Line Test

190

To obtain replacement parts

192

To clean the instrument

193

Glossary

194

196 CPU32 Emulation

197

CPU32 Emulation 197

198

198 CPU32 Emulation

199

CPU32 Emulation 199

200

200 CPU32 Emulation

201

DECLARATION OF CONFORMITY

202

Product Regulations

203

Hewlett-Packard

204

P.O. Box 2197

204

1900 Garden of the Gods Road

204

Motorola CPU32 Guide de l'utilisateur (107 pages)

marque: Motorola | Catégorie: Processeurs | Taille: 2.65 MB |

Anglais

Table des matières

HP E2480A Motorola CPU32

2

Preprocessor Interface

2

At a Glance

3

Introduction

4

In This Book

5

Contents

6

Overview

10

Logic Analyzers Supported

12

Equipment supplied

13

Minimum equipment required

14

Chapter 1: Overview

17

Power-ON/Power-OFF Sequence

18

Connection Sequence

19

Hooking up Your System

20

Hooking up your System

21

Analyzer

29

Logic Analyzer

31

To set the ID switches

50

To interpret the LEDs

51

Downloading a configuration

53

Connecting Optional Equipment

57

Analyzing the Target System

60

Modes of Operation

62

Format Menu

63

Format Menu (Timing)

64

Using the Inverse Assembler

67

• Press the Align softkey

68

General output format

69

Clock qualifiers

71

Reference

72

Operating Characteristics

74

Repair Strategy

90

Circuit Board Dimensions

91

If You Have a Problem

92

Analyzer Problems

94

No trace list display

95

Analyzer won’t power up

95

Preprocessor Problems

96

Erratic trace measurements

97

Capacitive loading

97

Inverse Assembler Problems

98

Messages

101

“Slow or Missing Clock”

103

“Waiting for Trigger”

104

Cleaning the Instrument

105

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