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MOTOROLA

SEMICONDUCTOR PRODUCT INFORMATION

DSP56303

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DSP56303P/D

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Advance Information

24-BIT DIGITAL SIGNAL PROCESSOR

The DSP56303 is a member of the DSP56300 core family of programmable CMOS Digital

Signal Processors (DSPs). This family uses a high performance, single clock cycle per

instruction engine providing a twofold performance increase over Motorola's popular

DSP56000 core family while retaining code compatibility. Significant architectural

enhancements to the DSP56300 core family include a barrel shifter, 24 bit addressing,

instruction cache, and DMA. The DSP56303 offers 66/80 MIPS using an internal 66/80 MHz

clock at 3.0–3.6 volts. The DSP56300 core family offers a new level of performance in speed

and power provided by its rich instruction set and low power dissipation, enabling a new

generation of wireless, telecommunications, and multimedia products.

Figure 1

DSP56303 Block Diagram

PLL

OnCE™

Clock

Generator

Internal

Data

Bus

Switch

Program RAM

4096 × 24

(3072 × 24 and

Instruction

Cache

1024 × 24)

YAB

XAB

PAB

YDB

XDB

PDB

GDB

MODC/IRQC

MODB/IRQB

External

Data Bus

Switch

MODA/IRQA

DSP56300

616

24-Bit

X Data

RAM

2048 × 24

Y Data

RAM

2048 × 24

DDB

DAB

Memory Expansion Area

Peripheral

Core

YM_EB

XM_EB

PM_EB

PIO_EB

Expansion Area

SCI

Interface

JTAG

RESET

MODD/IRQD

PINIT/NMI

Boot-

strap

ROM

EXTAL

XTAL

ADDRESS

CONTROL

DATA

Triple

Timer

Host

Interface

HI08

ESSI

Interface

AA0456

Address

Generation

Unit

Six Channel

DMA Unit

Program

Interrupt

Controller

Program

Decode

Controller

Program

Address

Generator

Data ALU

24 × 24

→

56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

Power

Mngmnt

External

Bus

Interface

I - Cache

Control

External

Address

Bus

Switch

1 2 3 4

Résumé du contenu

Page 1 - DSP56303

Page 2 - DSP56303 FEATURES

DSP56303DSP56303 Features 2 DSP56303P/D MOTOROLA DSP56303 FEATURES • High performance DSP56300 core– 66/80 Million Instructions Per Second (MIPS) wi

Page 3 - TARGET APPLICATIONS

DSP56303Target Applications MOTOROLA DSP56303P/D 3 • Off-chip memory expansion– Data memory expansion to two 256 K x 24-bit word memory spaces– Prog

Page 4 - PRODUCT DOCUMENTATION

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes nowarranty, representation or guarantee reg

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