Motorola DSP56305 Manuel d'utilisateur télécharger pdf (Page 12)

Introduction

Enhancements over the DSP56000

MOTOROLA Optimizing DSP56300/DSP56600 Applications 1-5

1.3.2 Architectural Enhancements

The programmer’s model of the new DSP cores were also enhanced

by the following:

• An instruction cache controller was added to the DSP56300.

A Burst mode can be used to lower the off-chip traffic if

external DRAMs are used.

• A six-channel DMA controller was added to the DSP56300.

• A true barrel shifter (56-bit in DSP56300 and 40-bit in

DSP56600) was added to support multibit operations.

• The address and offset registers of the DSP56300 (R0–R7,

N0–N7) were extended to 24-bit wide to support larger

memory sizes.

• The DSP56300 has a 16-bit Arithmetic operating mode such

that 16-bit exact algorithms can be implemented without any

overhead.

• The DSP56300 and the DSP56600 have an on-chip Hardware

Stack Extension mechanism that makes the Stack depth

practically unlimited.

• Rounding and Saturation modes were added to the

Arithmetic Unit of the DSP56300 and DSP56600.

• New addressing modes were added to the DSP56300 and

DSP56600:

– Short/Long address displacement

– PC-Relative for Position Independent Code

– Short/Long Immediate operands to Arithmetic and

Logical operations

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Motorola DSP56305 Manuel d'utilisateur Page 12