Motorola DSP56305 Manuel d'utilisateur Page 26
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Data Operations
Double precision arithmetic
MOTOROLA Optimizing DSP56300/DSP56600 Applications 2-11
is specified by its width (in bits) and its starting position (in bits,
relative to the LSB of the accumulator). The width and position
values could be prepared using the MERGE instruction, which
merges data from two data registers in the appropriate positions for
future use as a control operand for EXTRACT and INSERT.
The EXTRACT instruction extracts the specified field, right-aligns it,
and sign-extends it in the destination accumulator. The EXTRACTU
instruction does the same, but does not sign-extend the result. The
INSERT instruction takes a right-aligned field of the specified width
from the source register and places it in the specified position in the
destination accumulator.
Detailed examples of the use of these instructions for parsing and
creating a data stream, and parsing Hoffman code data stream can
be found in Appendix C of the
DSP56300
and
DSP56600 Family
Manuals
.
2.6 DOUBLE PRECISION ARITHMETIC
The DSP56300/DSP56600 has instructions to help the programmer
implement arithmetic operations if the operands are longer than
standard accumulator size. Using these instructions can help
achieve enhanced precision with minimum software overhead. The
examples below relate to the DSP56300 core register size (24 bits for
data registers, 56 bits for an accumulator), but can be adapted for
the DSP56600 core by changing the register size accordingly.
The normal ADD and SUB instructions can add a 48-bit operand
(X1:X0, for example) to an accumulator, and, of course, can add a
56-bit accumulator to another. Furthermore, the user may use ADC
(Add long with Carry) or SBC (Subtract long with Carry), which
adds (subtracts) a 48-bit operand to (from) an accumulator with a
carry (borrow) bit from a previous calculation.
The normal MPY (multiply) or MAC (multiply-accumulate)
instructions multiply two 24-bit operands to give a 48-bit result.
Implementing 32 × 32-bit or 48 × 48-bit multiplication requires four
24 × 24 multiplications, and some shifting and addition operations.
The DSP56300 and DSP56600 specialized instructions can help
reducing these extra operations to a minimum. Consider for
example 48 × 48 multiplication, where only the forty-eight Most
Significant Bits are needed, and the forty-eight Least Significant Bits
discarded. Figure 2-2 on page 2-12 illustrates the required
operations.
- DSP56300/DSP56600 1
- Digital Signal 1
- Processors 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 6
- LIST OF TABLES 7
- INTRODUCTION 8
- 1.2 DSP56600 CORE FAMILY 9
- Table 1-1 11
- Introduction 12
- Description and Use 13
- Application Note Structure 14
- 1.4.3 Appendixes 15
- DATA OPERATIONS 16
- DSP56300 Family Manual 21
- 2.3 THE MAX INSTRUCTION 22
- 2.4 USING THE BARREL SHIFTER 23
- Data Operations 24
- Using the barrel shifter 24
- DSP56300 26
- DSP56600 Family 26
- Double precision arithmetic 27
- INSTRUCTIONS 28
- PROGRAM CONTROL 30
- Program Control 31
- Hardware Loops 31
- 3.2 THE HARDWARE STACK 32
- DSP56600 Family Manuals 35
- 3.3 USING THE STACK EXTENSION 36
- Using the Stack Extension 37
- EXTENSION 39
- Conditional DALU Instructions 40
- 3.6 PC RELATIVE INSTRUCTIONS 42
- DSP56600 Family Manual 43
- 3.7 USING FAST INTERRUPTS 46
- Using Fast Interrupts 48
- USING THE DMA 50
- Using the DMA 51
- Using Slow, Low-Cost Memories 54
- 4.4 SERVICING A PERIPHERAL 55
- Servicing a Peripheral 56
- Section 5 62
- 5.1 THE INSTRUCTION CACHE 62
- 5.1.1 Cache Sectors 64
- The Instruction Cache 65
- 5.1.3 Cache Burst Mode 67
- 5.2 MEMORY SWITCH 70
- Memory Switch 71
- 5.3 USING THE BOOTSTRAP ROM 72
- Using the Bootstrap ROM 73
- PIPELINE INTERLOCKS 74
- Pipeline Interlocks 75
- Data ALU Pipeline Interlocks 75
- DSP56000 Family Manual 76
- INTERLOCKS 80
- Interlocks 80
- 6.3 STACK EXTENSION DELAYS 81
- Interlocks? 83
- COMPACT OPCODE USE 86
- Instructions 87
- Compact Opcode Use 89
- Cycle Count of an Instruction 89
- 7.2 ADDRESSING MODES 90
- 7.2.2 Short Addressing Mode 91
- 7.2.3 Short Immediate Mode 91
- 7.2.5 Register Addressing 92
- 7.2.6 Word Count 92
- 7.3 PERIPHERAL ADDRESSING 92
- 7.4 SPECIAL INSTRUCTIONS 93
- 7.4.1 Dual Data Spaces 93
- 7.4.3 Clearing Registers 94
- Special Instructions 95
- SAVING POWER 96
- A.1.2 Stop Standby Mode 97
- A.1.3 Low-Power Clock Divider 97
- Saving Power 98
- Disabling Functional Blocks 98
- DEBUG AND TEST SUPPORT 100
- B.2 JTAG PORT FEATURES 101
- B.3 ADDRESS TRACING 102
- Debug and Test Support 103
- Address Tracing 103
- USING THE PROFILER 104
- C.3 THE PROFILING REPORT 105
- C.3.1 Basic Report 105
- C.3.2 Symbol Report 106
- Using the Profiler 107
- C.3.4 Code Coverage Report 108
- C.3.5 Basic Subroutine Report 109
- C.3.8 Subroutine Call Report 111
- C.4 USING THE PROFILE REPORT 111
- How to reach us: 112
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