Motorola DSP56305 Manuel d'utilisateur Page 46

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Program Control
Using Fast Interrupts
MOTOROLA Optimizing DSP56300/DSP56600 Applications 3-17
instructs the assembler to try and compact the argument into a
1-word opcode. Without it, the assembler may use the 2-word
version.
Note: If a 2-word opcode is used, the value of _CONT1 is 3 (and not
2). This is because the extra word pushes the RTS instruction
address one position forward.
3.7 USING FAST INTERRUPTS
Once the PIC (Program Interrupt Controller) decides to pass an
interrupt request and interrupt the core, two instruction words are
fetched from the interrupt vector space and enter the pipeline for
execution. As explained in Section 7 of the
DSP56300
and
DSP56600 Family Manuals
, interrupt execution is of two types:
Fast interrupts—None of the two interrupt words is a
“change of flow” instruction (JSR, JSCLR, etc.). The program
controller automatically continues to fetch instructions from
the address at which it was interrupted and execution
resumes with no software overhead. There is no pipeline
flush or stall— the pipeline behaves as if the two interrupt
words were originally part of the program sequence.
Long interrupts—If one of the instructions is of a
change-of-flow type, execution cost is much higher.
Normally, the minimum activity includes a jump to a
subroutine, which is relatively a long instruction since it
pushes data to the stack. Normally at the subroutine end
there is a corresponding “RTI” instruction that pops data
from the stack and reconstructs the PC and the SR.
The pipeline is optimized for very high performance (minimum
stall) for fast interrupts, so the user is advised to try using them
whenever possible. Some specialized instructions were added to the
instruction set in order to help the user perform many operations
using fast interrupts. Also for this reason, many instructions have
1-opcode versions, generally at the expense of argument.
A frequently encountered interrupt activity is driving data to and
from a peripheral device triggered by an interrupt at the
peripheral's request. For example, a serial peripheral interrupts the
core when data is received, and expects it to be moved (generally to
a memory location), or the interrupt occurs when the serial device is
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