Motorola DSP56305 Manuel d'utilisateur Page 54
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Noté. / 5. Basé sur avis des utilisateurs
Using the DMA
Using Slow, Low-Cost Memories
MOTOROLA Optimizing DSP56300/DSP56600 Applications 4-5
memory locations. In a read access, the 3 bytes are concatenated to
one 24-bit word that is written to the destination by the DMA. In a
write access, the 24-bit word is unpacked to 3 single-byte write
accesses. After initialization, all this activity is done automatically
without software overhead.
In the following example, the DMA is programmed to read data
from an 8-bit wide external memory and store it as 24-bit words in
the internal memory, using the Packing mode. After reading a
predefined number of 24-bits words, the core is interrupted. The
external 8-bit data module is mapped to 65 K addresses in the Y
data space in addresses: $80XXXX and the data is transferred to
internal Y memory space.
;================= general definitions
MSP_8_BITequ $80 ;MSP of address of
;the 8-bit memory (8 bits)
INT_ADDRequ $200 ;internal address of transfer
;destination
NUM_24_Wequ $512 ;number of 24-bit words to read.
;================= initialize BIU
AAR_WORDequ (MSP_8_BIT<<16)+$8a1
;AAR0 value (only relevant non-zero values
;listed)
;BAC MSP_8_BIT 8 bits for address compare bits
;BNC 1000 number of address bits to compare (8)
;BPAC 1 packing mode enabled
;BYEN 1 Y data space enabled
;BAT 01 external access type - Synchronous RAM
movep #AAR_WORD,x:M_AAR0
movep #5,x:M_BCR ;program aar0 accesses
;for 5 wait states.
;================= initialize DMA
movep #(MSP_8_BIT<<16),x:M_DSR0;first address of
;8-bit data as
;source address
movep #INT_ADDR,x:M_DDR0 ;base address of
;memory data buffer
;is tran. destination.
movep #((NUM_24_W-1)<<12),x:M_DCO0;number of transfers
;before core is
;interrupted
;(2D counter)
movep #3,x:M_DOR0 ;offset of 3 added
;after every 24-bit
;word access.
;DMA control word: % 0 1 011 00 0 00000 0 101 000 01 01
;DE 0 channel not armed (yet)
;DIE 1 DMA interrupts enabled
;DTM 011 word transfer triggered by SW.
;DPR 00 lowest channel priority
;DCON 0 continuous mode disabled
;DRS 00000 DMA request source - don't care (SW trig)
;D3D 0 3 dimensional mode disabled
- DSP56300/DSP56600 1
- Digital Signal 1
- Processors 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 6
- LIST OF TABLES 7
- INTRODUCTION 8
- 1.2 DSP56600 CORE FAMILY 9
- Table 1-1 11
- Introduction 12
- Description and Use 13
- Application Note Structure 14
- 1.4.3 Appendixes 15
- DATA OPERATIONS 16
- DSP56300 Family Manual 21
- 2.3 THE MAX INSTRUCTION 22
- 2.4 USING THE BARREL SHIFTER 23
- Data Operations 24
- Using the barrel shifter 24
- DSP56300 26
- DSP56600 Family 26
- Double precision arithmetic 27
- INSTRUCTIONS 28
- PROGRAM CONTROL 30
- Program Control 31
- Hardware Loops 31
- 3.2 THE HARDWARE STACK 32
- DSP56600 Family Manuals 35
- 3.3 USING THE STACK EXTENSION 36
- Using the Stack Extension 37
- EXTENSION 39
- Conditional DALU Instructions 40
- 3.6 PC RELATIVE INSTRUCTIONS 42
- DSP56600 Family Manual 43
- 3.7 USING FAST INTERRUPTS 46
- Using Fast Interrupts 48
- USING THE DMA 50
- Using the DMA 51
- Using Slow, Low-Cost Memories 54
- 4.4 SERVICING A PERIPHERAL 55
- Servicing a Peripheral 56
- Section 5 62
- 5.1 THE INSTRUCTION CACHE 62
- 5.1.1 Cache Sectors 64
- The Instruction Cache 65
- 5.1.3 Cache Burst Mode 67
- 5.2 MEMORY SWITCH 70
- Memory Switch 71
- 5.3 USING THE BOOTSTRAP ROM 72
- Using the Bootstrap ROM 73
- PIPELINE INTERLOCKS 74
- Pipeline Interlocks 75
- Data ALU Pipeline Interlocks 75
- DSP56000 Family Manual 76
- INTERLOCKS 80
- Interlocks 80
- 6.3 STACK EXTENSION DELAYS 81
- Interlocks? 83
- COMPACT OPCODE USE 86
- Instructions 87
- Compact Opcode Use 89
- Cycle Count of an Instruction 89
- 7.2 ADDRESSING MODES 90
- 7.2.2 Short Addressing Mode 91
- 7.2.3 Short Immediate Mode 91
- 7.2.5 Register Addressing 92
- 7.2.6 Word Count 92
- 7.3 PERIPHERAL ADDRESSING 92
- 7.4 SPECIAL INSTRUCTIONS 93
- 7.4.1 Dual Data Spaces 93
- 7.4.3 Clearing Registers 94
- Special Instructions 95
- SAVING POWER 96
- A.1.2 Stop Standby Mode 97
- A.1.3 Low-Power Clock Divider 97
- Saving Power 98
- Disabling Functional Blocks 98
- DEBUG AND TEST SUPPORT 100
- B.2 JTAG PORT FEATURES 101
- B.3 ADDRESS TRACING 102
- Debug and Test Support 103
- Address Tracing 103
- USING THE PROFILER 104
- C.3 THE PROFILING REPORT 105
- C.3.1 Basic Report 105
- C.3.2 Symbol Report 106
- Using the Profiler 107
- C.3.4 Code Coverage Report 108
- C.3.5 Basic Subroutine Report 109
- C.3.8 Subroutine Call Report 111
- C.4 USING THE PROFILE REPORT 111
- How to reach us: 112
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