Motorola DSP56305 Manuel d'utilisateur Page 65
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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
5-4 Optimizing DSP56300/DSP56600 Applications MOTOROLA
Instruction Cache and Memory Features
The Instruction Cache
independent addresses. The instruction addresses must have one of
the allocated tag fields, and only eight different tag fields can be
allocated at any given time.
An application that depends on the cache for efficient execution
should be designed taking into account the sector allocation. If
possible, important code segments that are planned to be cached
should be written to fit the smallest possible number of 128 (256)
word units, so that they occupy the minimum number of cache
sectors. Also, care should be taken to place segments that are
planned to be cached in addresses that are inside a sector and not
cross sector borders needlessly.
For example, a routine that is 100 words long should start at an
address whose seven (eight) LSBs are between 0 and $1b ($9b),
otherwise it will “spill over” and use two cache sectors instead of
the one into which it could fit. Small code segments could be packed
together to fit into a smaller number of sectors, keeping fragments
of unused sector space at a minimum.
5.1.2 Control of Sector Allocation
Allocation of sectors is done automatically—they are allocated as
instructions are fetched. If an instruction does not have a sector with
a fitting tag, it is a “sector miss”. If a sector is available, it's tag
register is written with the tag field of the instruction's address, and
the instruction from that address is written to the cache. There is no
wait penalty for a sector miss.
When all eight sectors are used, and a sector miss occurs, the cache
controller chooses a sector that will be written over. The controller
keeps track of the sector use, and uses the Least-Recently-Used
(LRU) sector for replacement.
The data that was in that sector is lost for hit detection even if that
sector will be allocated again later with the same tag. A newly
allocated sector should be filled with data fetched from the external
memory, with the resulting wait states.
The user has at his disposal a set of specialized cache control
instructions, for better management of sector allocation. The
following operations can be performed:
1. Lock a sector (PLOCK,PLOCKR)—A sector that is locked will
not be a part of the LRU arbitration for sectors to be replaced
- DSP56300/DSP56600 1
- Digital Signal 1
- Processors 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 6
- LIST OF TABLES 7
- INTRODUCTION 8
- 1.2 DSP56600 CORE FAMILY 9
- Table 1-1 11
- Introduction 12
- Description and Use 13
- Application Note Structure 14
- 1.4.3 Appendixes 15
- DATA OPERATIONS 16
- DSP56300 Family Manual 21
- 2.3 THE MAX INSTRUCTION 22
- 2.4 USING THE BARREL SHIFTER 23
- Data Operations 24
- Using the barrel shifter 24
- DSP56300 26
- DSP56600 Family 26
- Double precision arithmetic 27
- INSTRUCTIONS 28
- PROGRAM CONTROL 30
- Program Control 31
- Hardware Loops 31
- 3.2 THE HARDWARE STACK 32
- DSP56600 Family Manuals 35
- 3.3 USING THE STACK EXTENSION 36
- Using the Stack Extension 37
- EXTENSION 39
- Conditional DALU Instructions 40
- 3.6 PC RELATIVE INSTRUCTIONS 42
- DSP56600 Family Manual 43
- 3.7 USING FAST INTERRUPTS 46
- Using Fast Interrupts 48
- USING THE DMA 50
- Using the DMA 51
- Using Slow, Low-Cost Memories 54
- 4.4 SERVICING A PERIPHERAL 55
- Servicing a Peripheral 56
- Section 5 62
- 5.1 THE INSTRUCTION CACHE 62
- 5.1.1 Cache Sectors 64
- The Instruction Cache 65
- 5.1.3 Cache Burst Mode 67
- 5.2 MEMORY SWITCH 70
- Memory Switch 71
- 5.3 USING THE BOOTSTRAP ROM 72
- Using the Bootstrap ROM 73
- PIPELINE INTERLOCKS 74
- Pipeline Interlocks 75
- Data ALU Pipeline Interlocks 75
- DSP56000 Family Manual 76
- INTERLOCKS 80
- Interlocks 80
- 6.3 STACK EXTENSION DELAYS 81
- Interlocks? 83
- COMPACT OPCODE USE 86
- Instructions 87
- Compact Opcode Use 89
- Cycle Count of an Instruction 89
- 7.2 ADDRESSING MODES 90
- 7.2.2 Short Addressing Mode 91
- 7.2.3 Short Immediate Mode 91
- 7.2.5 Register Addressing 92
- 7.2.6 Word Count 92
- 7.3 PERIPHERAL ADDRESSING 92
- 7.4 SPECIAL INSTRUCTIONS 93
- 7.4.1 Dual Data Spaces 93
- 7.4.3 Clearing Registers 94
- Special Instructions 95
- SAVING POWER 96
- A.1.2 Stop Standby Mode 97
- A.1.3 Low-Power Clock Divider 97
- Saving Power 98
- Disabling Functional Blocks 98
- DEBUG AND TEST SUPPORT 100
- B.2 JTAG PORT FEATURES 101
- B.3 ADDRESS TRACING 102
- Debug and Test Support 103
- Address Tracing 103
- USING THE PROFILER 104
- C.3 THE PROFILING REPORT 105
- C.3.1 Basic Report 105
- C.3.2 Symbol Report 106
- Using the Profiler 107
- C.3.4 Code Coverage Report 108
- C.3.5 Basic Subroutine Report 109
- C.3.8 Subroutine Call Report 111
- C.4 USING THE PROFILE REPORT 111
- How to reach us: 112
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