Motorola DSP56305 Manuel d'utilisateur Page 67
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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
5-6 Optimizing DSP56300/DSP56600 Applications MOTOROLA
Instruction Cache and Memory Features
The Instruction Cache
Notes:
1. Disabling the cache controller and enabling it again
implicitly flushes the cache. Data stored in the cache prior to
its activation cannot be accessed as “hits”. A program section
cannot be copied into the cacheable array for use as cached
instructions.
2. The user should refrain from using old data from the
cacheable array after the cache is disabled.
5.1.3 Cache Burst Mode
A cache miss usually results in a single external memory read. The
fetched word is passed to execution and also written into the cache.
When the Burst mode is enabled (BE bit in the OMR is set), a cache
miss may initiate up to four consecutive external memory reads.
The instructions that are fetched are stored into the cache in their
appropriate locations. Only the instruction that caused the miss is
executed. The program continues to execute and normally fetches
the next instruction. This instruction may now be in the cache (as a
result of the previous burst), and therefore it will be a cache hit.
The instructions that were fetched during the burst cause the
regular wait states as defined for that type of access. The Burst
mode is intended for working with DRAM external memory, where
an out-of-page access causes more wait states than an in-page
access. In an application that uses the same DRAM for both data
and program memory, the program's serial flow of fetches will be
interleaved with data accesses. Usually the program fetch after a
data access will be out-of-page, even if it is in the same page as the
previous instruction. When using the Burst mode, instructions
fetched during a burst will all be in the same page, and so the total
program stall will be lower.
The number of program words that are brought in a burst depends
only on the value of the last two bits of the address that caused the
cache miss. If the value of those bits is “00”, then four consecutive
words will be fetched, with the last bits of the addresses being “11”,
“10”, “01” and “00” (the instruction that caused the miss). For a miss
on an address with “01” LS bits, three words will be fetched (“11”,
“10”, “01”). For “10” only two words will be fetched (“11” and
“10”), and for an address with “11” LS bits, only the word that
caused the miss will be fetched. This mechanism is basically not
- DSP56300/DSP56600 1
- Digital Signal 1
- Processors 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 6
- LIST OF TABLES 7
- INTRODUCTION 8
- 1.2 DSP56600 CORE FAMILY 9
- Table 1-1 11
- Introduction 12
- Description and Use 13
- Application Note Structure 14
- 1.4.3 Appendixes 15
- DATA OPERATIONS 16
- DSP56300 Family Manual 21
- 2.3 THE MAX INSTRUCTION 22
- 2.4 USING THE BARREL SHIFTER 23
- Data Operations 24
- Using the barrel shifter 24
- DSP56300 26
- DSP56600 Family 26
- Double precision arithmetic 27
- INSTRUCTIONS 28
- PROGRAM CONTROL 30
- Program Control 31
- Hardware Loops 31
- 3.2 THE HARDWARE STACK 32
- DSP56600 Family Manuals 35
- 3.3 USING THE STACK EXTENSION 36
- Using the Stack Extension 37
- EXTENSION 39
- Conditional DALU Instructions 40
- 3.6 PC RELATIVE INSTRUCTIONS 42
- DSP56600 Family Manual 43
- 3.7 USING FAST INTERRUPTS 46
- Using Fast Interrupts 48
- USING THE DMA 50
- Using the DMA 51
- Using Slow, Low-Cost Memories 54
- 4.4 SERVICING A PERIPHERAL 55
- Servicing a Peripheral 56
- Section 5 62
- 5.1 THE INSTRUCTION CACHE 62
- 5.1.1 Cache Sectors 64
- The Instruction Cache 65
- 5.1.3 Cache Burst Mode 67
- 5.2 MEMORY SWITCH 70
- Memory Switch 71
- 5.3 USING THE BOOTSTRAP ROM 72
- Using the Bootstrap ROM 73
- PIPELINE INTERLOCKS 74
- Pipeline Interlocks 75
- Data ALU Pipeline Interlocks 75
- DSP56000 Family Manual 76
- INTERLOCKS 80
- Interlocks 80
- 6.3 STACK EXTENSION DELAYS 81
- Interlocks? 83
- COMPACT OPCODE USE 86
- Instructions 87
- Compact Opcode Use 89
- Cycle Count of an Instruction 89
- 7.2 ADDRESSING MODES 90
- 7.2.2 Short Addressing Mode 91
- 7.2.3 Short Immediate Mode 91
- 7.2.5 Register Addressing 92
- 7.2.6 Word Count 92
- 7.3 PERIPHERAL ADDRESSING 92
- 7.4 SPECIAL INSTRUCTIONS 93
- 7.4.1 Dual Data Spaces 93
- 7.4.3 Clearing Registers 94
- Special Instructions 95
- SAVING POWER 96
- A.1.2 Stop Standby Mode 97
- A.1.3 Low-Power Clock Divider 97
- Saving Power 98
- Disabling Functional Blocks 98
- DEBUG AND TEST SUPPORT 100
- B.2 JTAG PORT FEATURES 101
- B.3 ADDRESS TRACING 102
- Debug and Test Support 103
- Address Tracing 103
- USING THE PROFILER 104
- C.3 THE PROFILING REPORT 105
- C.3.1 Basic Report 105
- C.3.2 Symbol Report 106
- Using the Profiler 107
- C.3.4 Code Coverage Report 108
- C.3.5 Basic Subroutine Report 109
- C.3.8 Subroutine Call Report 111
- C.4 USING THE PROFILE REPORT 111
- How to reach us: 112
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