Motorola DSP56305 Manuel d'utilisateur Page 72
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Instruction Cache and Memory Features
Using the Bootstrap ROM
MOTOROLA Optimizing DSP56300/DSP56600 Applications 5-11
Possible advantages for using the Memory Switch mode:
1. A program may dynamically change it's internal memory
map according to need.
2. A system may be developed with the intention of using
Program and data ROM in the end product. Using a ROM
allows much more data to be placed on chip. Development is
done with a RAM-based emulation version, which can hold
much smaller internal memory. Using external memory is
not always an adequate solution due the different timing of
external accesses. Using a RAM-based chip with Memory
Switch mode may help solving the problem—large program
sections may be tested using more program memory, and
sections using large data tables could be tested separately
using more data memory.
The MS (Memory Switch) bit in the OMR selects between the two
alternate memory configurations. In chips without the Memory
Switch mode, this bit is reserved. Enabling or disabling the Memory
Switch mode should be done with care—the user may not use
memory addresses that change their locations while executing the
switch instruction at least six instructions afterwards. The cache
must also be disabled. A proper switching sequence should be run
from program memory addresses that do not change their physical
mapping during the switch, when the cache is disabled, and
without data accesses to the data areas that change their physical
mapping. In the example of the DSP56302, the switching routine
may be run from program memory addresses lower than $4C00, or
higher than $6000, with the cache disabled.
5.3 USING THE BOOTSTRAP ROM
Most DSP56300 family members have a short ROM program for
downloading a program from an external device to the program
RAM. This program is coded in the core, and is mapped to the
internal program memory space. At the user's choice, this program
may be executed immediately after a hardware reset. The program
chooses the device that is used for the download by studying the
operating mode bits in the OMR. The operating mode bits are
latched from the interrupt request pins during the hardware reset,
and thus are user-controlled. According to these bits, program data
may be downloaded from the SCI, Host Interface, the external
- DSP56300/DSP56600 1
- Digital Signal 1
- Processors 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 6
- LIST OF TABLES 7
- INTRODUCTION 8
- 1.2 DSP56600 CORE FAMILY 9
- Table 1-1 11
- Introduction 12
- Description and Use 13
- Application Note Structure 14
- 1.4.3 Appendixes 15
- DATA OPERATIONS 16
- DSP56300 Family Manual 21
- 2.3 THE MAX INSTRUCTION 22
- 2.4 USING THE BARREL SHIFTER 23
- Data Operations 24
- Using the barrel shifter 24
- DSP56300 26
- DSP56600 Family 26
- Double precision arithmetic 27
- INSTRUCTIONS 28
- PROGRAM CONTROL 30
- Program Control 31
- Hardware Loops 31
- 3.2 THE HARDWARE STACK 32
- DSP56600 Family Manuals 35
- 3.3 USING THE STACK EXTENSION 36
- Using the Stack Extension 37
- EXTENSION 39
- Conditional DALU Instructions 40
- 3.6 PC RELATIVE INSTRUCTIONS 42
- DSP56600 Family Manual 43
- 3.7 USING FAST INTERRUPTS 46
- Using Fast Interrupts 48
- USING THE DMA 50
- Using the DMA 51
- Using Slow, Low-Cost Memories 54
- 4.4 SERVICING A PERIPHERAL 55
- Servicing a Peripheral 56
- Section 5 62
- 5.1 THE INSTRUCTION CACHE 62
- 5.1.1 Cache Sectors 64
- The Instruction Cache 65
- 5.1.3 Cache Burst Mode 67
- 5.2 MEMORY SWITCH 70
- Memory Switch 71
- 5.3 USING THE BOOTSTRAP ROM 72
- Using the Bootstrap ROM 73
- PIPELINE INTERLOCKS 74
- Pipeline Interlocks 75
- Data ALU Pipeline Interlocks 75
- DSP56000 Family Manual 76
- INTERLOCKS 80
- Interlocks 80
- 6.3 STACK EXTENSION DELAYS 81
- Interlocks? 83
- COMPACT OPCODE USE 86
- Instructions 87
- Compact Opcode Use 89
- Cycle Count of an Instruction 89
- 7.2 ADDRESSING MODES 90
- 7.2.2 Short Addressing Mode 91
- 7.2.3 Short Immediate Mode 91
- 7.2.5 Register Addressing 92
- 7.2.6 Word Count 92
- 7.3 PERIPHERAL ADDRESSING 92
- 7.4 SPECIAL INSTRUCTIONS 93
- 7.4.1 Dual Data Spaces 93
- 7.4.3 Clearing Registers 94
- Special Instructions 95
- SAVING POWER 96
- A.1.2 Stop Standby Mode 97
- A.1.3 Low-Power Clock Divider 97
- Saving Power 98
- Disabling Functional Blocks 98
- DEBUG AND TEST SUPPORT 100
- B.2 JTAG PORT FEATURES 101
- B.3 ADDRESS TRACING 102
- Debug and Test Support 103
- Address Tracing 103
- USING THE PROFILER 104
- C.3 THE PROFILING REPORT 105
- C.3.1 Basic Report 105
- C.3.2 Symbol Report 106
- Using the Profiler 107
- C.3.4 Code Coverage Report 108
- C.3.5 Basic Subroutine Report 109
- C.3.8 Subroutine Call Report 111
- C.4 USING THE PROFILE REPORT 111
- How to reach us: 112
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