Motorola DSP56305 Manuel d'utilisateur télécharger pdf (Page 8)

MOTOROLA Optimizing DSP56300/DSP56600 Applications 1-1

This application

note describes how

to optimize an

application for the

DSP56300 and

DSP56600 new

DSP cores

Section 1

INTRODUCTION

The DSP56300 and DSP56600 are the new high-performance 24-bit

and 16-bit cores in Motorola’s family of Digital Signal Processors.

They are based on the same pipeline structure. This structure is

capable of executing an instruction on every clock cycle. At the

same time these cores maintain a Harvard architecture and

programming model similar to the older 24-bit DSP56000 core.

Code written for the DSP56300 or the DSP56600 may be based on

previously developed code written for the DSP56000, or it may be

new code that was developed initially for these new DSP cores. The

intent of this document is to describe the new and the

DSP56000-based features of the DSP56300 and DSP56600 cores in

order to help the DSP software engineer to fully utilize the

processor resources and generate an optimized application.

The document is a supplement to the detailed DSP56300 and

DSP56600 Family Manuals.

1.1 DSP56300 CORE FAMILY

The DSP56300 core consists of the Expansion Port and DRAM

Controller, Data ALU, Address Generation Unit, Instruction Cache

Controller, Program Control Unit, DMA Controller, PLL Clock

Oscillator, On-Chip Emulation (OnCE™) module, JTAG Test Access

Port (TAP), and the Peripheral and Memory Expansion Busses. The

main features of this high performance CPU include:

• Object code compatibility with the DSP56000 core

• Harvard Architecture with 24-bit instruction width and

24-bit data width

• Fully pipelined 24

24-bit parallel Multiplier-Accumulator

(MAC)

• 56-bit parallel barrel shifter

• 16-bit Arithmetic mode of operation

• Highly parallel instruction set

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Motorola DSP56305 Manuel d'utilisateur Page 8