Motorola DSP56305 Manuel d'utilisateur Page 9

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1-2 Optimizing DSP56300/DSP56600 Applications MOTOROLA
Introduction
DSP56600 Core Family
Position Independent Code (PIC) instruction-set support
Unique DSP addressing modes
On-chip memory-expandable hardware stack
Nested hardware DO loops
Fast auto-return interrupts
On-chip instruction cache
On-chip concurrent six-channel DMA controller
On-chip Phase Lock Loop (PLL)
On-Chip Emulation (OnCE) module
Program address tracing support
JTAG port compatible with the
IEEE 1149.1 Standard
The first members of DSP chips that use the DSP56300 core are the
DSP56301, DSP56302, DSP56303, and DSP56305. The main
differences between these derivatives are the size of the on-chip
memory and the types of on-chip peripherals and hardware
accelerators.
1.2 DSP56600 CORE FAMILY
The DSP56600 core consists of the External Memory Interface port,
Data ALU, Address Generation Unit, Program Control Unit, PLL
Clock Oscillator, On-Chip Emulation module, and the Peripheral
and Memory Expansion Busses. The main differences between the
DSP56300 and the DSP56600 cores are:
The DSP56600 uses a 16-bit data bus, while the DSP56300
uses a 24-bit data bus.
The Multiplier-Accumulator in the DSP56600 is 16
×
16 bit
while the DSP56300 is 24
×
24 bit.
The DSP56600’s barrel shifter is 40 bits wide, while the
DSP56300’s barrel shifter is 56 bits wide.
The DSP56600 does not include an instruction cache
controller.
The DSP56600 does not include a six-channel DMA
controller.
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