Motorola DSP56305 Manuel d'utilisateur télécharger pdf (Page 93)

7-8 Optimizing DSP56300/DSP56600 Applications MOTOROLA

Compact Opcode Use

Special Instructions

7.4 SPECIAL INSTRUCTIONS

7.4.1 Dual Data Spaces

The Harvard architecture of the DSP56300/DSP56600 cores includes

two data memory spaces: X and Y. An efficient structure of the

application’s data segment can improve the code performance by

being able to use instructions that support this architecture. For

example, the following code:

move x:(r0),x0

move x:(r4),y0

In this code, two data arrays were put into the same memory space,

while the code had to access an item from each array one after the

other. Instead, if one of the arrays can be put into the other data

memory space (Y in this example) then the two items can be

accessed on the same instruction:

move x:(r0),x0 y:(r4),y0

7.4.2 Using the TFR instructions

The TFR instruction is unique by giving the ability to combine two

move operations into a single instruction in a way that is not

supported by the usual parallel opcodes. Example:

move x0,a

move r1,r2

This example can be optimized by combining the two move

instructions into a single TFR instruction:

tfr x0,a r1,r2

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Motorola DSP56305 Manuel d'utilisateur Page 93