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SEMICONDUCTOR PRODUCT INFORMATION

DSP96002

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DSP96002P/D

32-BIT IEEE FLOATING-POINT DUAL-PORT DSP

The DSP96002 is a single-chip, dual port, HCMOS, low-power, general purpose IEEE

floating-point Digital Signal Processor (DSP) that features 1024 words of data RAM (equally

divided into X data and Y data memory), 1024 words of full speed on-chip program RAM,

two preprogrammed data ROMs, a dual channel DMA controller, special on-chip bootstrap

hardware, and On-Chip Emulation (OnCE™) debug circuitry. The Central Processing Unit

(CPU) consists of three 32-bit execution units operating in parallel. The DSP96002 has two

identical memory expansion ports with control lines that facilitate interfacing to SRAMs,

fast-access DRAMs, and Video RAMs (VRAMs). Each port can be transformed into a Host

Interface (HI), which facilitates easy interfacing to other processors for multiprocessor

applications. Linear arrays of DSP96002s can be implemented without glue logic. The MPU-

style programming model and instruction set allow straightforward generation of efficient,

compact code. The high speed of the DSP96002 makes it well-suited for high bandwidth and

numerically intensive applications such as graphics, image, and numeric processing.

Figure 1

DSP96002 Block Diagram

Internal

Switch And Bit

Manipulation

Unit

Program Controller

Data

YAB

XAB

PAB

YDB

XDB

PDB

GDB

Program

Decode

Controller

Program

Address

Generator

Program

Interrupt

Controller

Clock

Generator

DDB

Dual Channel

DMA

Controller

Debug

Controller

Serial Debug

Port

MODB/IRQB

MODA/IRQA

RESET

External

Address

Switch

Address

Generation

Unit (AGU)

• IEEE Floating Point

• 32 x 32 Integer ALU

CLK

Memory

512 x 32

RAM

Memory

512 x 32

RAM

Program

1024 x32

RAM and

64 x 32

Bootstrap

ROM

512 x 32†

ROM

512 x 32†

ROM

Data ALU

32-bit Buses

Address

External

Address

Switch

Bus

Control

External

Data

Switch

Port B

Memory

X Data Y Data

MODC/IRQC

Bus

Control

Host

Interface

Data

Dual Access (DMA/Core)

1818

Instruction

Cache

TimerTimer

Port A

Address

1024 x 32 Virtual Locations

†

32-bit

Host

Interface

32-bit

OnCE

AA0306

Bus

External

Data

Switch

Bus

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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Résumé du contenu

Page 1 - DSP96002

Page 2 - Freescale Semiconductor, Inc

DSP96002DSP96002 Features 2 DSP96002P/D MOTOROLA DSP96002 FEATURES • Digital signal processing core– Efficient 32-bit DSP engine– Conforms to IEEE 7

Page 3 - PRODUCT DOCUMENTATION

DSP96002Product Documentation MOTOROLA DSP96002P/D 3 – Off-chip expansion to 2 x 2 32 32-bit words of data memory– Off-chip expansion to 2 32 32-b

Page 4

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee re

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Motorola DSP96002 Manuel d'utilisateur

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