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MC68302/D

Rev. 3

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

Product Brief

Integrated Multiprotocol Processor (IMP)

MC68302



MOTOROLA, 1994

Microprocessor and Memory

Technologies Group

SEMICONDUCTOR PRODUCT INFORMATION

The IMP is a VLSI device incorporating the main building blocks needed for the design of a wide variety of

controllers. The device is especially suited to applications in the communications industry. The IMP is the first

device to offer the benefits of a closely coupled, industry-standard, MC68000/MC68008 microprocessor core

and a flexible communications architecture. This multichannel communications device may be configured to

support a number of popular industry-standard interfaces, including those for the Integrated Services Digital

Network (ISDN) basic rate and terminal adapter applications. Through a combination of architectural and

programmable features, concurrent operation of different protocols is easily achieved using the IMP. Data

concentrators, modems, line cards, bridges, and gateways are examples of suitable applications for this

versatile device. The IMP is an HCMOS device consisting of an MC68000/MC68008 microprocessor core, a

system integration block (SIB), and a communications processor (CP).

The main features of the IMP are as follows:

• MC68000/MC68008 Microprocessor Core (May Be Disabled to Use the IMP As a Peripheral)

• SIB Including:

— Independent Direct Memory Access (IDMA) Controller

— Interrupt Controller with Two Modes of Operation

— Parallel I/O Ports, Some with Interrupt Capability

— On-Chip 1152 Bytes of Dual-Port RAM

— Three Timers, Including a Software Watchdog Timer

— Four Programmable Chip-Select Lines with Wait-State Logic

— Programmable Address Mapping of Dual-Port RAM and IMP Registers

— On-Chip Clock Generator with an Output Clock Signal

— System Control

–System Control Register

–Bus Arbitration Logic with Low Interrupt Latency Support

–Hardware Watchdog for Monitoring Bus Activity

–Low Power (Standby) Modes

–Disable CPU Logic (M68000)

–Freeze Control for Debugging Selected On-Chip Peripherals

–DRAM Refresh Controller

• CP Including:

— Main Controller (RISC Processor)

— Three Full-Duplex Serial Communication Controllers (SCCs) with the Following Protocols:

–HDLC/SDLC

–Bisync

–UART

–DDCMP

–Totally Transparent

–V.110

Thi d d i h F M k 4 0 4

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

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Page 1 - Product Brief

Order this document byMC68302/DRev. 3 This document contains information on a product under development. Motorola reserves the right to change or dis

Page 2 - Freescale Semiconductor, Inc

2 MC68302 PRODUCT INFORMATION MOTOROLA — Six Serial DMA Channels Dedicated to the Three SCCs— Capability To Send /Receive Up to Eight Buffers/Frames

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MOTOROLA MC68302 PRODUCT INFORMATION 3 The MC68302 uses a microprocessor architecture that has serial channels connected to the system busthrough a d

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4 MC68302 PRODUCT INFORMATION MOTOROLA six wait states to avoid using board space for cycle-termination logic. The four signals may each support four

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MOTOROLA MC68302 PRODUCT INFORMATION 5 The following table identifies the packages and operating frequencies available for the MC68302.The documents

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