Motorola MC68VZ328 Manuel d'utilisateur

MC68VZ328UM/DRev. 0, 02/2000MC68VZ328 Integrated ProcessorUser’s Manual

x MC68VZ328 User’s Manual 13.4 SPI 2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-12 MC68VZ328 User’s Manual Programming ModelCSC Chip-Select Register C 0x(FF)FFF114 BIT 1514 13 12 11 10 9 8 7 6 5 4 3 2 1BIT 0RO SOP ROP UPSIZFLAS

Programming Model Chip-Select Logic 6-13WS3–1Bits 6–4Wait State—This field determines the number of wait states added before an internal DTACK signal

6-14 MC68VZ328 User’s Manual Programming ModelCSD Chip-Select Register D 0x(FF)FFF116BIT 1514 13 12 11 10 9 8 7 6 5 4 3 2 1BIT 0RO SOP ROP UPSIZ COMB

Programming Model Chip-Select Logic 6-15FLASHBit 8 Flash Memory Support—When enabled, this bit provides support for flash memory by forcing the LWE/U

6-16 MC68VZ328 User’s Manual Programming Model6.3.4 Emulation Chip-Select RegisterIn addition to the eight general-purpose chip-select signals, the

Programming Model Chip-Select Logic 6-17CSCTRL1 Chip-Select Control Register 1 0x(FF)FFF10ABIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0EUPENSR16EWS0

6-18 MC68VZ328 User’s Manual Programming ModelThe unprotected memory size is calculated according to the chip-select addressing space and the UPSIZ v

Programming Model Chip-Select Logic 6-19ECDSBit 14Early Cycle Detection for Static Memory—This bit advances the chip-select signals for SRAM, ROM, or

6-20 MC68VZ328 User’s Manual Programming Model6.3.7 Chip-Select Control Register 3This register controls minor timing trims for static memory access

Programming Model Chip-Select Logic 6-21Example 6-2. Programming Example************************************************* Chip-Select registers**

 Table of Contents xi15.2 PWM 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-22 MC68VZ328 User’s Manual Programming Model

 DRAM Controller 7-1Chapter 7DRAM ControllerThis chapter describes the DRAM controller for the MC68VZ328. The operation of the DRAM controller is clo

7-2 MC68VZ328 User’s Manual Introduction to the DRAM ControllerFigure 7-1. DRAM Controller Block DiagramDataSYSCLKControlAddressCLK32CSD0CSD1MD[15:

DRAM Controller Operation DRAM Controller 7-37.2 DRAM Controller OperationThis section describes the DRAM controller’s operation.7.2.1 Address Mul

7-4 MC68VZ328 User’s Manual DRAM Controller OperationTable 7-1. DRAM Address Multiplexing OptionsA1/MD0 A2/MD1 A3/MD2 A4/MD3 A5/MD4 A6/MD5 A7/MD6 A

DRAM Controller Operation DRAM Controller 7-5Table 7-2 through Table 7-5 on page 7-6 provide recommendations for MC68VZ328–to–SDRAM connections and f

7-6 MC68VZ328 User’s Manual DRAM Controller OperationTable 7-4. 128 Mbit SDRAM—512 (16-Bit) and 1024 (8-Bit) Page SizeSDRAM PinsA0 A1 A2 A3 A4 A5 A

DRAM Controller Operation DRAM Controller 7-77.2.2 DTACK GenerationIn a 16 MHz system frequency, 60 ns DRAM can support a zero wait state (4 clocks

7-8 MC68VZ328 User’s Manual DRAM Controller Operation7.2.4 LCD InterfaceFigure 7-2 illustrates the LCD controller and DRAM controller interface. The

DRAM Controller Operation DRAM Controller 7-97.2.5 8-Bit Mode From the system integration module (SIM), 8-bit operation on the fly can be selected u

xii MC68VZ328 User’s Manual 17.1.3 Setting Up the RS-232 Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31

7-10 MC68VZ328 User’s Manual DRAM Controller Operation7.2.7 Data Retention During ResetDRAM needs to retain data during reset, whether it is an exte

DRAM Controller Operation DRAM Controller 7-117.2.8 Data Retention SequenceData is retained in the following sequence:1. The external RESET signal i

7-12 MC68VZ328 User’s Manual Programming Model7.3 Programming ModelThis section describes the programming model for the DRAM controller.7.3.1 DRAM

Programming Model DRAM Controller 7-13The REF value is the time of 1 refresh cycle.Example 7-1. Calculating REF Field Values for Refresh TimesWhen

7-14 MC68VZ328 User’s Manual Programming Model7.3.2 DRAM Control RegisterThe DRAM control (DRAMC) register is used to control the operation of the D

Programming Model DRAM Controller 7-15LSPBit 4Light Sleep—Setting this bit enables the core or LCD controller to access the DRAM when the RM bit is s

7-16 MC68VZ328 User’s Manual Programming Model7.3.3 SDRAM Control RegisterThis register controls operation when SDRAM is being used. The bit positio

Programming Model DRAM Controller 7-17BNKADDLBits 3–2SDRAM Low Order Bank Address Line Selection—A 2-bit bank register selection address is generated

7-18 MC68VZ328 User’s Manual Programming Model7.3.4 SDRAM Power-down RegisterThis register controls how the SDRAM and the MC68VZ328 operate during a

 LCD Controller 8-1Chapter 8LCD ControllerThis chapter describes the operation of the liquid crystal display (LCD) controller and supplies the progra

 Table of Contents xiii19.3.23 Page-Miss at Starting of LCD DMA for SDRAM (CAS Latency = 1) . . . . . . . . 19-2819.3.24 Page-Miss at Start and in M

8-2 MC68VZ328 User’s Manual LCD Controller OperationFigure 8-1. LCD Controller Block Diagram8.2 LCD Controller OperationThe LCD controller consis

LCD Controller Operation LCD Controller 8-3The LCD interface logic is used to pack the display data into the correct size and output it to the LCD pa

8-4 MC68VZ328 User’s Manual LCD Controller OperationFigure 8-2. LCD Interface Timing for 4-, 2-, and 1-Bit Data Widths8.2.2 Controlling the Displa

LCD Controller Operation LCD Controller 8-5Figure 8-3. LCD Screen FormatThe LCD screen width (LXMAX) and LCD screen height (LYMAX) registers are wh

8-6 MC68VZ328 User’s Manual LCD Controller Operation8.2.2.3 Mapping the Display DataThe LCD controller supports 1 or 2 bits per pixel graphics mode

LCD Controller Operation LCD Controller 8-7Since crystal formulations and driving voltages vary, the visual grayscale effect may or may not be linear

8-8 MC68VZ328 User’s Manual LCD Controller Operation8.2.3 Using Low-Power ModeSome panels may have a PANEL_OFF signal, which is used to turn off the

LCD Controller Operation LCD Controller 8-9During the same period, the line buffer must be filled. The following TDMA duration is how long the DMA cy

8-10 MC68VZ328 User’s Manual Programming Model8.3 Programming ModelThe remaining sections of this chapter provide detailed descriptions of the regi

Programming Model LCD Controller 8-118.3.2 LCD Virtual Page Width RegisterThe LCD virtual page width (LVPW) register contains the width of the displ

xiv MC68VZ328 User’s Manual 

8-12 MC68VZ328 User’s Manual Programming Model8.3.4 LCD Screen Height RegisterThe LCD screen height register (LYMAX) is used to define the height of

Programming Model LCD Controller 8-138.3.6 LCD Cursor Y Position RegisterThe LCD cursor Y position (LCYP) register is used to determine the vertical

8-14 MC68VZ328 User’s Manual Programming Model8.3.7 LCD Cursor Width and Height RegisterThe LCD cursor width and height (LCWCH) register is used to

Programming Model LCD Controller 8-15LBLKC LCD Blink Control Register 0x(FF)FFFA1F8.3.9 LCD Panel Interface Configuration RegisterThe LCD panel inte

8-16 MC68VZ328 User’s Manual Programming Model8.3.10 LCD Polarity Configuration RegisterThe LCD polarity configuration (LPOLCF) register controls th

Programming Model LCD Controller 8-17LACDRC LACD Rate Control Register 0x(FF)FFFA238.3.12 LCD Pixel Clock Divider RegisterThe LCD pixel clock divide

8-18 MC68VZ328 User’s Manual Programming Model8.3.13 LCD Clocking Control RegisterThe LCD clocking control (LCKCON) register is used to enable the L

Programming Model LCD Controller 8-198.3.15 LCD Panning Offset RegisterThe LCD panning offset register (LPOSR) is used to control how many pixels th

8-20 MC68VZ328 User’s Manual Programming Model8.3.17 LCD Gray Palette Mapping RegisterFor four-level grayscale displays, full black and full white a

Programming Model LCD Controller 8-218.3.19 Refresh Mode Control RegisterOnly a single bit in this register is used to enable or disable LCD self-re

 List of Figures xvFigure 1-1 MC68VZ328 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2Figure 1-2 Us

8-22 MC68VZ328 User’s Manual Programming Example8.3.20 DMA Control RegisterThe LCD controller contains an 8 × 16 pixel buffer, which stores DMA-in d

 Interrupt Controller 9-1 Chapter 9Interrupt Controller This chapter describes the interrupt controller and all of the signals associated with it. Th

9-2 MC68VZ328 User’s Manual  Interrupt Processing9.1 Interrupt Processing Interrupts on the MC68VZ328 are processed as illustrated in the flowchart

Exception Vectors Interrupt Controller 9-3 programmable, but the lower 3 bits reflect the interrupt level that is being serviced. All interrupts are

9-4 MC68VZ328 User’s Manual  ResetNOTE:The MC68VZ328 does not provide autovector interrupts. At systemstartup, the user interrupt vector must be prog

Interrupt Controller Operation Interrupt Controller 9-5 NOTE:The MC68VZ328 supports the reset instruction. However, it only resets theCPU, and the RE

9-6 MC68VZ328 User’s Manual  Vector Generation9.4.2 Interrupt VectorsThe MC68VZ328 provides one interrupt vector for each of the seven user interrup

Programming Model Interrupt Controller 9-7 9.6 Programming Model This section describes registers that you may need to configure so that the interr

9-8 MC68VZ328 User’s Manual  Programming Model9.6.2 Interrupt Control Register The interrupt control register (ICR) controls the behavior of the ext

Programming Model Interrupt Controller 9-9 ET2Bit 10IRQ2 Edge Trigger Select—When this bit is set, the IRQ2 signal is an edge-triggered interrupt. In

xvi MC68VZ328 User’s Manual Figure 15-1 PWM 1 and PWM 2 System Configuration Diagram . . . . . . . . . . . . . . . . . . . 15-1Figure 15-2 PWM 1 Bl

9-10 MC68VZ328 User’s Manual  Programming Model9.6.3 Interrupt Mask Register The interrupt mask register (IMR) can mask out a particular interrupt i

Programming Model Interrupt Controller 9-11 MIRQ2Bit 17Mask IRQ2 Interrupt—When set, this bit indicates that IRQ2 is masked. It is set to 1 after res

9-12 MC68VZ328 User’s Manual  Programming Model9.6.4 Interrupt Status Register During the interrupt service, the interrupt handler determines the so

Programming Model Interrupt Controller 9-13 RTIBit 22Real-Time Interrupt Status (Real-Time Clock)—When set, this bit indicates that the real-time tim

9-14 MC68VZ328 User’s Manual  Programming ModelUART2Bit 12UART 2 Interrupt Request—When set, this bit indicates that the UART 2 module needs service.

Programming Model Interrupt Controller 9-15 UART1Bit 2UART 1 Interrupt Request—When set, this bit indicates that the UART 1 module needs service. Thi

9-16 MC68VZ328 User’s Manual  Programming Model9.6.5 Interrupt Pending Register The read-only interrupt pending register (IPR) indicates which inter

Programming Model Interrupt Controller 9-17 IRQ5Bit 20Interrupt Request Level 5—This bit, when set, indicates that an external device is requesting a

9-18 MC68VZ328 User’s Manual  Programming ModelINT2Bit 10External INT2 Interrupt—This bit, when set, indicates that a level 4 interrupt has occurred.

Programming Model Interrupt Controller 9-19 9.6.6 Interrupt Level RegisterTIMER 2, UART 2, PWM 2, and SPI 1 are new modules to the MC68VZ328 compare

 List of Figures xviiFigure 19-28 SPI 1 Master Using DATA_READY Edge Trigger Timing Diagram . . . . . . 19-32Figure 19-29 SPI 1 Master Using DATA_RE

9-20 MC68VZ328 User’s Manual  Pen Interrupts9.7 Keyboard Interrupts Keyboard interrupt features provide a smart power-management capability. The CP

 I/O Ports 10-1Chapter 10I/O PortsThis chapter describes the 10 multipurpose ports of the MC68VZ328. It also describes how to use the ports for exter

10-2 MC68VZ328 User’s Manual Status of I/O Ports During Reset10.2 Status of I/O Ports During ResetTwo types of resets affect the states of the MC68

Status of I/O Ports During Reset I/O Ports 10-3Figure 10-1. I/O Port Warm Reset TimingAs shown in Figure 10-1, resets for Ports A, C–G, J, and K ar

10-4 MC68VZ328 User’s Manual I/O Port Operation10.2.3 Summary of Port Behavior During ResetTable 10-2 summarizes the behavior of all MC68VZ328 I/O p

I/O Port Operation I/O Ports 10-5Figure 10-2. I/O Port OperationFor example, if Figure 10-2 represents the D0 bit of Port E, when the SEL0 in the s

10-6 MC68VZ328 User’s Manual Programming Model10.3.4 Port Pull-up and Pull-down ResistorsThe pull-up and pull-down resistors are enabled by setting

Programming Model I/O Ports 10-710.4.1.1 Port A Direction RegisterThe Port A direction register controls the direction (input or output) of the lin

10-8 MC68VZ328 User’s Manual Programming Model10.4.1.3 Port A Pull-up Enable RegisterThe Port A pull-up enable register (PAPUEN) controls the pull-

Programming Model I/O Ports 10-9PBDIR Port B Direction Register 0x(FF)FFF40810.4.2.2 Port B Data RegisterThe settings for the PBDATA bit positions

xviii MC68VZ328 User’s Manual 

10-10 MC68VZ328 User’s Manual Programming Model10.4.2.3 Port B Dedicated I/O FunctionsThe eight PBDATA lines are multiplexed with the chip-select,

Programming Model I/O Ports 10-11PBPUEN Port B Pull-up Enable Register 0x(FF)FFF40A10.4.2.5 Port B Select RegisterThe Port B select register (PBSEL

10-12 MC68VZ328 User’s Manual Programming Model10.4.3.1 Port C Direction RegisterThe Port C direction register controls the direction (input or out

Programming Model I/O Ports 10-13accept the data, but the data written to each cannot be accessed until the corresponding pin is configured as an out

10-14 MC68VZ328 User’s Manual Programming Model10.4.3.5 Port C Select RegisterThe Port C select register (PCSEL) determines if a bit position in th

Programming Model I/O Ports 10-1510.4.4 Port D OperationPort D has the same functionality as other GPIO ports, except that it also has interrupt cap

10-16 MC68VZ328 User’s Manual Programming Model10.4.5 Port D RegistersUnlike the other ports, Port D is unique in that it is comprised of eight 8-bi

Programming Model I/O Ports 10-1710.4.5.2 Port D Data RegisterThe settings for the PDDATA bit positions are shown in Table 10-18.PDDATA Port D Data

10-18 MC68VZ328 User’s Manual Programming Model10.4.5.3 Port D Interrupt OptionsInterrupt bits 3–0 (INT[3:0]), interrupt request bits 3–1 (IRQ[3:1]

Programming Model I/O Ports 10-1910.4.5.5 Port D Select RegisterThe Port D select register (PDSEL) determines if a bit position in the Port D data

 List of Tables xixTable 1-1 Address Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6Ta

10-20 MC68VZ328 User’s Manual Programming Model10.4.5.7 Port D Interrupt Request Enable RegisterThe interrupt enable bits (IQEN[3:0]) determine whi

Programming Model I/O Ports 10-21PDIRQEG Port D Interrupt Request Edge Register 0x(FF)FFF41F10.4.6 Port E RegistersPort E is composed of the followi

10-22 MC68VZ328 User’s Manual Programming Model10.4.6.2 Port E Data RegisterThe settings for the bit positions of the PEDATA register are shown in

Programming Model I/O Ports 10-2310.4.6.4 Port E Pull-up Enable RegisterThe Port E pull-up enable register (PEPUEN) controls the pull-up resistors

10-24 MC68VZ328 User’s Manual Programming Model10.4.7 Port F RegistersPort F is composed of the following 8-bit general-purpose I/O registers:• Port

Programming Model I/O Ports 10-2510.4.7.2 Port F Data RegisterThe settings for the bit positions of the PFDATA register are shown in Table 10-32.PF

10-26 MC68VZ328 User’s Manual Programming Model10.4.7.3 Port F Dedicated I/O FunctionsThe eight PFDATA lines are multiplexed with the dedicated I/O

Programming Model I/O Ports 10-2710.4.7.4 Port F Pull-up/Pull-down Enable RegisterThe Port F pull-up/pull-down enable register (PFPUEN) controls th

10-28 MC68VZ328 User’s Manual Programming Model10.4.8 Port G RegistersPort G is comprised of the following 8-bit general-purpose I/O registers:• Por

Programming Model I/O Ports 10-29PGDATA Port G Data Register 0x(FF)FFF431Port G is multiplexed with address line A0 and several dedicated I/O functio

MFAX and DragonBall are trademarks of Motorola, Inc.This document contains information on a new product. Specifications and information herein are sub

xx MC68VZ328 User’s Manual Table 7-7 DRAM Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14Table 7-8

10-30 MC68VZ328 User’s Manual Programming ModelBUSW is the default bus width for the CSA0 signal. The DTACK signal is the external input data acknowl

Programming Model I/O Ports 10-31PGSEL Port G Select Register 0x(FF)FFF43310.4.9 Port J RegistersPort J is composed of the following four general-pu

10-32 MC68VZ328 User’s Manual Programming Model10.4.9.2 Port J Data RegisterThe bit settings for the PJDATA register are shown in Table 10-42.PJDAT

Programming Model I/O Ports 10-33Bits 0–3 are control signals connected to SPI 1. Their operation is detailed in Section 13.2.4, “SPI 1 Signals,” on

10-34 MC68VZ328 User’s Manual Programming Model10.4.10 Port K RegistersPort K is composed of the following 8-bit general-purpose I/O registers:• Por

Programming Model I/O Ports 10-35PKDATA Port K Data Register 0x(FF)FFF441Port K is multiplexed with the IrDA, SPI, and LCD controller signals. These

10-36 MC68VZ328 User’s Manual Programming ModelWhen bit 0 is set as DATA_READY, it can be used in master mode to signal the SPI master to clock out d

Programming Model I/O Ports 10-3710.4.11 Port M RegistersPort M is composed of the following four general-purpose I/O registers:• Port M direction r

10-38 MC68VZ328 User’s Manual Programming Model10.4.11.2 Port M Data RegisterThe settings for the PMDATA register bit positions are shown in Table

Programming Model I/O Ports 10-3910.4.11.3 Port M Dedicated I/O FunctionsThe six PMDATA lines are multiplexed with the dedicated I/O signals whose

 List of Tables xxiTable 10-8 Port B Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9Table 10-9

10-40 MC68VZ328 User’s Manual Programming Model10.4.11.5 Port M Select RegisterThe select register (PMSEL) determines if a bit position in the data

 Real-Time Clock 11-1Chapter 11Real-Time ClockThis chapter describes the real-time clock (RTC) module, which is composed of six blocks as shown in Fi

11-2 MC68VZ328 User’s Manual RTC Overview11.1 RTC OverviewThe prescaler uses the CLK32 clock to create a 1 Hz clock used by all of the blocks in th

RTC Overview Real-Time Clock 11-3The prescaler stages are tapped to support real-time interrupt features. A periodic interrupt at 1 Hz is available,

11-4 MC68VZ328 User’s Manual RTC Overview11.1.4 Watchdog TimerThe watchdog timer is an added check that a program is running and sequencing properly

Programming Model Real-Time Clock 11-511.2 Programming ModelSection 11.2.1, “RTC Time Register,” through Section 11.2.9, “Stopwatch Minutes Registe

11-6 MC68VZ328 User’s Manual Programming Model11.2.2 RTC Day Count RegisterThe real-time clock day count register (DAYR) contains the data from the

Programming Model Real-Time Clock 11-711.2.3 RTC Alarm RegisterThe real-time clock alarm (RTCALRM) register is used to configure the alarm. The hour

11-8 MC68VZ328 User’s Manual Programming Model11.2.4 RTC Day Alarm RegisterThe real-time clock day alarm (DAYALRM) register contains the numerical v

Programming Model Real-Time Clock 11-911.2.5 Watchdog Timer RegisterThe watchdog timer (WATCHDOG) register provides all of the control of the watchd

xxii MC68VZ328 User’s Manual Table 10-47 Port K Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35T

11-10 MC68VZ328 User’s Manual Programming Model11.2.6 RTC Control RegisterThe real-time clock control (RTCCTL) register is used to enable the real-t

Programming Model Real-Time Clock 11-11RTCISR RTC Interrupt Status Register 0x(ff)FFFB0EBIT 1514 13 12 11 10 9 8 7 6 5 4 3 2 1BIT 0RIS7 RIS6 RIS5 RIS

11-12 MC68VZ328 User’s Manual Programming Model11.2.8 RTC Interrupt Enable RegisterThe RTC interrupt enable register (RTCIENR) is used to enable the

Programming Model Real-Time Clock 11-13RTCIENR RTC Interrupt Enable Register 0x(ff)FFFB10BIT 1514 13 12 11 10 9 8 7 6 5 4 3 2 1BIT 0RIE7 RIE6 RIE5 RI

11-14 MC68VZ328 User’s Manual Programming Model11.2.9 Stopwatch Minutes RegisterThe stopwatch minutes (STPWCH) register contains the current stopwat

 General-Purpose Timers 12-1Chapter 12General-Purpose TimersThis chapter describes in detail the operation of the general-purpose timer modules of th

12-2 MC68VZ328 User’s Manual GP Timer Overview12.1.1 Clock Source and PrescalerThe clock source for each timer is individually selectable through so

GP Timer Overview General-Purpose Timers 12-312.1.3 Timer Capture RegisterEach timer has a 16-bit capture register that takes a “snapshot” of the ti

12-4 MC68VZ328 User’s Manual GP Timer Overview12.1.5 Cascaded TimersBoth timers can be cascaded together to create a 32-bit counter. The cascade con

GP Timer Overview General-Purpose Timers 12-5Figure 12-2. Compare Routine for 32-Bit Cascaded TimersWait on MSW MSW status bit set?No LSW status bi

 List of Tables xxiiiTable 14-5 UART 1 Baud Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 14-12Table 14-6 UART 1 Re

12-6 MC68VZ328 User’s Manual Programming Model12.2 Programming ModelThe following sections provide programming information about the settings of th

Programming Model General-Purpose Timers 12-7CAPBits 7–6Capture Edge—This field selects the type of transition on the TIN input that triggers a cap-t

12-8 MC68VZ328 User’s Manual Programming Model12.2.2 Timer Prescaler Registers 1 and 2Each timer prescaler register (TPRERx) controls the divide rat

Programming Model General-Purpose Timers 12-912.2.3 Timer Compare Registers 1 and 2Each timer compare (TCMPx) register contains the value that is co

12-10 MC68VZ328 User’s Manual Programming Model12.2.4 Timer Capture Registers 1 and 2Each timer capture register (TCRx) stores the counter value whe

Programming Model General-Purpose Timers 12-1112.2.5 Timer Counter Registers 1 and 2Each read-only timer counter (TCNx) register contains the curren

12-12 MC68VZ328 User’s Manual Programming Model12.2.6 Timer Status Registers 1 and 2Each timer status (TSTATx) register indicates the corresponding

 Serial Peripheral Interface 1 and 2 13-1Chapter 13Serial Peripheral Interface 1 and 2The MC68VZ328 contains two serial peripheral interface (SPI) mo

13-2 MC68VZ328 User’s Manual SPI 1 Operation13.2 SPI 1 OperationThe SPI 1 signal pins are multiplexed with bit 0 (DATA_READY) of the Port K registe

SPI 1 Operation Serial Peripheral Interface 1 and 2 13-313.2.3 SPI 1 Phase and Polarity ConfigurationsWhen SPI 1 is used as master, the SPICLK1 sign

xxiv MC68VZ328 User’s Manual Table 19-12 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access Timing Parameters . . 19-14Table 19-13 LCD DRAM DMA Cycle 16-Bit

13-4 MC68VZ328 User’s Manual SPI 1 Programming Model13.3 SPI 1 Programming ModelThis section provides information for programming SPI 1.13.3.1 SPI

SPI 1 Programming Model Serial Peripheral Interface 1 and 2 13-513.3.2 SPI 1 Transmit Data RegisterThis write-only data register is the top of the 8

13-6 MC68VZ328 User’s Manual SPI 1 Programming Model13.3.3 SPI 1 Control/Status RegisterThis register controls the configuration and operation of th

SPI 1 Programming Model Serial Peripheral Interface 1 and 2 13-7SSCTLBit 6SS Waveform Select—In master mode, this bit selects the output wave form fo

13-8 MC68VZ328 User’s Manual SPI 1 Programming Model13.3.4 SPI 1 Interrupt Control/Status RegisterThis register is used to provide interrupt control

SPI 1 Programming Model Serial Peripheral Interface 1 and 2 13-9TEENBit 8TxFIFO Empty Interrupt Enable—This bit, when set, causes an interrupt to be

13-10 MC68VZ328 User’s Manual SPI 1 Programming Model13.3.5 SPI 1 Test RegisterThe configurable SPI test (SPITEST) register indicates the state mach

SPI 2 Overview Serial Peripheral Interface 1 and 2 13-11SPISPC SPI 1 Sample Period Control Register 0x(FF)FFF70A13.4 SPI 2 OverviewThis section dis

13-12 MC68VZ328 User’s Manual SPI 2 Operation13.5 SPI 2 OperationThe serial peripheral interface 2 operates as a master-mode-only SPI module using

SPI 2 Operation Serial Peripheral Interface 1 and 2 13-1313.5.1 SPI 2 Phase and Polarity ConfigurationsThe SPI 2 module uses the SPICLK2 signal to t

 List of Examples xxvExample 4-1 Configuring the PLLCLK Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7Example 4-2 Sh

13-14 MC68VZ328 User’s Manual SPI 2 Programming Model13.6 SPI 2 Programming ModelThis section provides information for programming SPI 2.13.6.1 SP

SPI 2 Programming Model Serial Peripheral Interface 1 and 2 13-1513.6.3 SPI 2 Control/Status RegisterThe SPI 2 control/status (SPICONT2) register co

13-16 MC68VZ328 User’s Manual SPI 2 Programming ModelIRQENBit 6Interrupt Request Enable—This bit enables an interrupt to be generated when an SPI 2 m

 Universal Asynchronous Receiver/Transmitter 1 and 2 14-1Chapter 14Universal Asynchronous Receiver/Transmitter 1 and 2This chapter describes both UAR

14-2 MC68VZ328 User’s Manual Serial OperationThe UART 2 module is an enhanced version of the UART 1. The features listed above are enhanced by the fo

Serial Operation Universal Asynchronous Receiver/Transmitter 1 and 2 14-3Figure 14-2. NRZ ASCII “A” Character with Odd Parity14.2.2 IrDA ModeInfra

14-4 MC68VZ328 User’s Manual UART Operation• RXD1/RXD2—The Receive Data signal, which is multiplexed with PE4 (PJ4 in UART 2), is the receiver serial

UART Operation Universal Asynchronous Receiver/Transmitter 1 and 2 14-5If the driver software has excessive interrupt service latency time, use the F

14-6 MC68VZ328 User’s Manual UART Operation14.3.2 Receiver OperationThe receiver block of the UART accepts a serial data stream, converting it into

UART Operation Universal Asynchronous Receiver/Transmitter 1 and 2 14-7Figure 14-4. Baud Rate Generator Block DiagramThe baud rate generator’s mast

xxvi MC68VZ328 User’s Manual 

14-8 MC68VZ328 User’s Manual UART Operation Example 14-1 provides a sample divisor calculation.Example 14-1. Sample Divisor Calculation33.16 MHz sy

UART Operation Universal Asynchronous Receiver/Transmitter 1 and 2 14-914.3.3.3 Integer PrescalerThe baud rate generator can provide standard baud

14-10 MC68VZ328 User’s Manual Programming Model14.4 Programming ModelSection 14.4.1, “UART 1 Status/Control Register,” through Section 14.4.14, “FI

Programming Model Universal Asynchronous Receiver/Transmitter 1 and 2 14-11STOPBit 9Stop Bit Transmission—This bit controls the number of stop bits t

14-12 MC68VZ328 User’s Manual Programming Model14.4.2 UART 1 Baud Control RegisterThe UART 1 baud control (UBAUD1) register controls the operation o

Programming Model Universal Asynchronous Receiver/Transmitter 1 and 2 14-1314.4.3 UART 1 Receiver RegisterThe UART 1 receiver (URX1) register indica

14-14 MC68VZ328 User’s Manual Programming Model14.4.4 UART 1 Transmitter RegisterThe UART 1 transmitter (UTX1) register controls how the transmitter

Programming Model Universal Asynchronous Receiver/Transmitter 1 and 2 14-15FIFOHALFBit 14FIFO Half (FIFO Status)—This read-only bit indicates that th

14-16 MC68VZ328 User’s Manual Programming Model14.4.5 UART 1 Miscellaneous RegisterThe UART 1 miscellaneous (UMISC1) register contains miscellaneous

Programming Model Universal Asynchronous Receiver/Transmitter 1 and 2 14-17RTS1 CONTBit 7RTS1 Control—This bit selects the function of the RTS1 pin.

 About This Book xxvii About This BookThis user’s manual describes the features and operation of the MC68VZ328 (DragonBall™ VZ) microprocessor, the t

14-18 MC68VZ328 User’s Manual Programming Model14.4.6 UART 1 Non-Integer Prescaler RegisterThe UART 1 non-integer prescaler register (NIPR1) contain

Programming Model Universal Asynchronous Receiver/Transmitter 1 and 2 14-1914.4.7 Non-Integer Prescaler Programming ExampleThe following steps show

14-20 MC68VZ328 User’s Manual Programming Model14.4.8 UART 2 Status/Control RegisterThe UART 2 status/control register (USTCNT2) controls the overal

Programming Model Universal Asynchronous Receiver/Transmitter 1 and 2 14-21ODENBit 7Old Data Enable—This bit enables an interrupt when the OLD DATA b

14-22 MC68VZ328 User’s Manual Programming Model14.4.9 UART 2 Baud Control RegisterThe UART 2 baud control (UBAUD2) register controls the operation o

Programming Model Universal Asynchronous Receiver/Transmitter 1 and 2 14-2314.4.10 UART 2 Receiver RegisterThe UART 2 receiver (URX2) register indic

14-24 MC68VZ328 User’s Manual Programming Model14.4.11 UART 2 Transmitter RegisterThe UART 2 transmitter (UTX2) register controls how the transmitte

Programming Model Universal Asynchronous Receiver/Transmitter 1 and 2 14-25FIFO HALFBit 14FIFO Half (FIFO Status)—This read-only bit indicates that t

14-26 MC68VZ328 User’s Manual Programming Model14.4.12 UART 2 Miscellaneous RegisterThe UART 2 miscellaneous (UMISC2) register contains miscellaneou

Programming Model Universal Asynchronous Receiver/Transmitter 1 and 2 14-27RTS2 CONTBit 7RTS2 Control—This bit selects the function of the RTS2 pin.

xxviii MC68VZ328 User’s Manual  Chapter 9 Interrupt Controller: This chapter provides a description and operational considerations for interrupt cont

14-28 MC68VZ328 User’s Manual Programming Model14.4.13 UART 2 Non-Integer Prescaler RegisterThe UART 2 non-integer prescaler register (NIPR2) contai

Programming Model Universal Asynchronous Receiver/Transmitter 1 and 2 14-2914.4.14 FIFO Level Marker Interrupt RegisterThe UART FIFO level marker re

14-30 MC68VZ328 User’s Manual Programming ModelTable 14-17. FIFO Level Marker SettingsTx FIFO Level MarkerNumber of Slots EmptyRx FIFO Level Marker

 Pulse-Width Modulator 1 and 2 15-1Chapter 15Pulse-Width Modulator 1 and 2This chapter describes the DragonBall VZ’s two pulse-width modulators (PWMs

15-2 MC68VZ328 User’s Manual PWM 115.1.1 PWM Clock SignalsFigure 15-2 shows a simplified block diagram of PWM 1. The prescaler and divider generate

PWM Operation Pulse-Width Modulator 1 and 2 15-315.3 PWM OperationThe pulse-width modulator has three modes of operation—playback, tone, and D/A.15

15-4 MC68VZ328 User’s Manual Programming Model15.4 Programming ModelThis section contains programming information about both PWM 1 and PWM 2. 15.4.

Programming Model Pulse-Width Modulator 1 and 2 15-5FIFOAVBit 5FIFO Available—This bit indicates that the FIFO is available for at least 1 byte of sa

15-6 MC68VZ328 User’s Manual Programming Model15.4.2 PWM 1 Sample RegisterThis register serves as the input to the FIFO. When successive audio sampl

Programming Model Pulse-Width Modulator 1 and 2 15-715.4.3 PWM 1 Period RegisterThis register controls the pulse-width modulator period. When the co

 About This Book xxix Suggested ReadingThe following documents are required for a complete description of the MC68VZ328 and are necessary to design p

15-8 MC68VZ328 User’s Manual PWM 215.5 PWM 2PWM 2 is a 16-bit PWM module that is compatible with the one used in the original DragonBall processor,

PWM 2 Pulse-Width Modulator 1 and 2 15-915.5.2 PWM 2 Period RegisterThis register controls the period of PWM 2. When the counter value matches the v

15-10 MC68VZ328 User’s Manual PWM 215.5.3 PWM 2 Pulse Width RegisterThis register controls the pulse width of PWM 2. The register bit assignments ar

 In-Circuit Emulation 16-1Chapter 16In-Circuit EmulationThis chapter describes the in-circuit emulation (ICE) module of the MC68VZ328 and provides de

16-2 MC68VZ328 User’s Manual ICE Operation16.1 ICE OperationThe in-circuit emulation module’s operation consists of the following tasks:• Entering

ICE Operation In-Circuit Emulation 16-316.1.2.1 Execution Breakpoints vs. Bus BreakpointsAn execution breakpoint is a breakpoint at which the curre

16-4 MC68VZ328 User’s Manual Programming Model16.2 Programming ModelThis section contains information about the ICE registers and programming infor

Programming Model In-Circuit Emulation 16-5ICEMACR ICE Module Address Compare Register 0x(FF)FFFFFD00ICEMAMR ICE Module Address Mask Register 0x(FF)F

16-6 MC68VZ328 User’s Manual Programming Model16.2.2 In-Circuit Emulation Module Control Compare and Mask RegisterThe in-circuit emulation module co

Programming Model In-Circuit Emulation 16-7RWMBit 1Read or Write Cycle Mask—This bit masks the RW bit of the ICEMCCR. 0 = Enable the comparator to co

 Table of Contents iii About This BookAudience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxx MC68VZ328 User’s Manual  Definitions, Acronyms, and AbbreviationsThe following list defines the acronyms and abbreviations used in this document.

16-8 MC68VZ328 User’s Manual Programming Model16.2.3 In-Circuit Emulation Module Control RegisterThe in-circuit emulation module control register (I

Programming Model In-Circuit Emulation 16-9CENBit 0Compare Enable—This bit is used to activate the compari-son logic. It is recommended that the addr

16-10 MC68VZ328 User’s Manual Typical Design Programming Example16.2.4 In-Circuit Emulation Module Status RegisterThe in-circuit emulation module st

Typical Design Programming Example In-Circuit Emulation 16-11Figure 16-2. Typical Emulator Design Example16.3.1 Host InterfaceThe host interface c

16-12 MC68VZ328 User’s Manual Plug-in Emulator Design Example16.3.3 Emulation Memory Mapping FPGA and Emulation MemorySince the memory on the target

Plug-in Emulator Design Example In-Circuit Emulation 16-13Figure 16-3. Plug-in Emulator Design ExampleAlthough there is only one hardware breakpoin

16-14 MC68VZ328 User’s Manual Application Development Design Example16.5 Application Development Design ExampleFigure 16-4 displays an example of a

 Bootstrap Mode 17-1Chapter 17Bootstrap ModeThis chapter describes the operation and programming information of the bootstrap mode of the MC68VZ328.

17-2 MC68VZ328 User’s Manual Bootstrap Mode Operation17.1.1 Entering Bootstrap ModeBootstrap mode is one of the three operation modes (normal, emula

Bootstrap Mode Operation Bootstrap Mode 17-317.1.3 Setting Up the RS-232 TerminalTo set up communication between your target system and the PC, set

 Introduction 1-1 Chapter 1IntroductionThis chapter describes the overall system architecture of the MC68VZ328 (DragonBall™ VZ) integrated processor.

17-4 MC68VZ328 User’s Manual Bootstrap Mode Operation17.1.5 System Initialization Programming ExampleBefore downloading a program to system memory,

Bootstrap Mode Operation Bootstrap Mode 17-517.1.6 Application Programming ExampleThe code shown in Example 17-2 can be used to calculate a CRC valu

17-6 MC68VZ328 User’s Manual Bootloader Flowchart17.1.7 Example of Instruction Buffer Usage Example 17-3 demonstrates how to run a 68000 instruction

Bootloader Flowchart Bootstrap Mode 17-7Figure 17-2. Bootloader Program OperationStartTest receive FIFO;Initialize appropriate UARTReceive a bootst

17-8 MC68VZ328 User’s Manual Special Notes17.3 Special NotesThe following information may be useful when the MC68VZ328 is in bootstrap mode.• A b-r

 Application Guide 18-1Chapter 18Application GuideThis chapter contains helpful information that will assist with integrating the MC68VZ328 into new

18-2 MC68VZ328 User’s Manual Application Guide18.1.3 Clock and Layout ConsiderationsThis section covers layout considerations affecting DragonBall t

 Electrical Characteristics 19-1Chapter 19Electrical CharacteristicsThis chapter documents electrical characteristics and provides timing information

19-2 MC68VZ328 User’s Manual AC Electrical Characteristics19.2 DC Electrical CharacteristicsTable 19-2 contains both maximum and minimum DC charact

AC Electrical Characteristics Electrical Characteristics 19-3Figure 19-1. CLKO Reference to Chip-Select Signals Timing Diagram19.3.2 Chip-Select R

1-2 MC68VZ328 User’s Manual  Features of the MC68VZ328Figure 1-1. MC68VZ328 Block Diagram1.1 Features of the MC68VZ328The features of the DragonB

19-4 MC68VZ328 User’s Manual AC Electrical CharacteristicsFigure 19-2. Chip-Select Read Cycle Timing DiagramTable 19-4. Chip-Select Read Cycle Ti

AC Electrical Characteristics Electrical Characteristics 19-519.3.3 Chip-Select Write Cycle TimingFigure 19-3 shows the write cycle timing used by c

19-6 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.4 Chip-Select Flash Write Cycle TimingFigure 19-4 on page 19-7 shows the flash write

AC Electrical Characteristics Electrical Characteristics 19-7Figure 19-4. Chip-Select Flash Write Cycle Timing DiagramTable 19-6. Chip-Select Fla

19-8 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.5 Chip-Select Timing TrimFigure 19-5 shows the timing diagram for the chip-select tim

AC Electrical Characteristics Electrical Characteristics 19-9Figure 19-6. DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing DiagramTable 19-8.

19-10 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.7 DRAM Write Cycle 16-Bit Access (CPU Bus Master)Figure 19-7 shows the DRAM write cy

AC Electrical Characteristics Electrical Characteristics 19-1119.3.8 DRAM Hidden Refresh Cycle (Normal Mode)Figure 19-8 on page 19-12 shows the DRAM

19-12 MC68VZ328 User’s Manual AC Electrical CharacteristicsFigure 19-8. DRAM Hidden Refresh Cycle (Normal Mode) Timing Diagram19.3.9 DRAM Hidden R

AC Electrical Characteristics Electrical Characteristics 19-1319.3.10 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access (1 Wait State)Figure 19-10 shows the

Features of the MC68VZ328 Introduction 1-3 — Five general-purpose, programmable edge/level/polarity interrupt IRQs — Other programmable I/O, multiple

19-14 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.11 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)Figure 19-11 shows

AC Electrical Characteristics Electrical Characteristics 19-15Table 19-13. LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master) Timing Pa

19-16 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)Figure 19-12 show

AC Electrical Characteristics Electrical Characteristics 19-1719.3.13 LCD Controller TimingFigure 19-13 shows the LCD controller timing diagram for

19-18 MC68VZ328 User’s Manual AC Electrical CharacteristicsFigure 19-14. LCD Controller Timing Diagram (Self-Refresh Mode)Table 19-15. LCD Contro

AC Electrical Characteristics Electrical Characteristics 19-1919.3.14 Page-Miss SDRAM CPU Read Cycle (CAS Latency = 1)Figure 19-15 shows the timing

19-20 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.15 Page-Hit SDRAM CPU Read Cycle (CAS Latency = 1)Figure 19-16 shows the timing diag

AC Electrical Characteristics Electrical Characteristics 19-2119.3.16 Page-Hit CPU Read Cycle for 8-Bit SDRAM (CAS Latency = 1)Figure 19-17 shows th

19-22 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.17 Page-Miss SDRAM CPU Write Cycle (CAS Latency = 1)Figure 19-18 shows the timing di

AC Electrical Characteristics Electrical Characteristics 19-2319.3.18 Page-Hit SDRAM CPU Write Cycle (CAS Latency = 1)Figure 19-19 shows the timing

1-4 MC68VZ328 User’s Manual  CPU• Built-in emulation function — Dedicated memory space for emulator debug monitor with chip-select — Dedicated interr

19-24 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.19 Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM (CAS Latency = 1)Figure 19-20 shows

AC Electrical Characteristics Electrical Characteristics 19-2519.3.20 Page-Hit CPU Read Cycle in Power-down Mode (CAS Latency = 1, Bit APEN of SDRAM

19-26 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.21 Exit Self-Refresh Due to CPU Read Cycle (CAS Latency = 1, Bit RM of DRAM Control

AC Electrical Characteristics Electrical Characteristics 19-2719.3.22 Enter Self-Refresh Due to No Activity for 64 Clocks (Bit RM of DRAM Control Re

19-28 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.23 Page-Miss at Starting of LCD DMA for SDRAM (CAS Latency = 1)Figure 19-24 shows th

AC Electrical Characteristics Electrical Characteristics 19-2919.3.24 Page-Miss at Start and in Middle of LCD DMA (CAS Latency = 1)Figure 19-25 show

19-30 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.25 Page-Hit LCD DMA Cycle for SDRAM (CAS Latency = 1)Figure 19-26 shows the timing d

AC Electrical Characteristics Electrical Characteristics 19-31Table 19-16. Timing Parameters for Figure 19-15 Through Figure 19-26Number Characteri

19-32 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.26 SPI 1 and SPI 2 Generic TimingFigure 19-27 shows the timing diagram for SPI 1 and

AC Electrical Characteristics Electrical Characteristics 19-3319.3.28 SPI 1 Master Using DATA_READY Level TriggerFigure 19-29 shows the timing diagr

CPU Introduction 1-5 1.2.1 CPU Programming ModelThe CPU has 32-bit registers and a 32-bit program counter, which are shown in Figure 1-2. The first

19-34 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.31 SPI 1 Slave FIFO Advanced by SS Rising EdgeFigure 19-32 shows the timing diagram

AC Electrical Characteristics Electrical Characteristics 19-3519.3.32 Normal Mode TimingFigure 19-33 shows the timing diagram for normal mode timing

19-36 MC68VZ328 User’s Manual AC Electrical Characteristics19.3.34 Bootstrap Mode TimingFigure 19-35 shows the timing diagram for bootstrap mode tim

 Mechanical Data and Ordering Information 20-1Chapter 20Mechanical Data and Ordering InformationThis chapter provides mechanical data, including illu

20-2 MC68VZ328 User’s Manual TQFP Pin Assignments20.2 TQFP Pin AssignmentsFigure 20-1 provides a top view of TQFP pin assignments.Figure 20-1. MC

TQFP Package Dimensions Mechanical Data and Ordering Information 20-320.3 TQFP Package DimensionsFigure 20-2 illustrates the TQFP 20 mm × 20 mm pac

20-4 MC68VZ328 User’s Manual MAPBGA Pin Assignments20.4 MAPBGA Pin AssignmentsFigure 20-3 provides a top view of the MAPBGA pin assignments.Figure

MAPBGA Package Dimensions Mechanical Data and Ordering Information 20-520.5 MAPBGA Package DimensionsFigure 20-4 illustrates the MAPBGA 13 mm × 13

20-6 MC68VZ328 User’s Manual PCB Finish Requirement20.6 PCB Finish RequirementFor a more reliable BGA assembly process, use HASL finish on PCB. EMN

 Index Index-iNumerics16-Bit SRAM enable bit, see SR16 bit32-bit counter, see cascaded timers8- or 7-bit bit, see 8/7 bit8/7 bitUSTCNT1 register, 14-

1-6 MC68VZ328 User’s Manual  CPU1.2.2 Data and Address Mode TypesThe CPU supports five types of data and six main types of address modes. The five t

Index-ii MC68VZ328 User’s Manual reset timing diagram, 17-2setting up RS-232 terminal, 17-3Break (character status) bit, see BREAK bitBREAK bitURX1 r

 Index Index-iiiCLK32 bit, 4-10CLK32 clock signalcrystal frequency range, 4-4crystal oscillator circuit example, 4-4crystal ramp-up time, 4-4descript

Index-iv MC68VZ328 User’s Manual CTSD bitUSTCNT1 register, 14-11USTCNT2 register, 14-21CTSx pin, programming to post interrupt, 14-3CUPS2 bit, 6-18Cu

 Index Index-vPCDATA register, 10-12PDDATA register, 10-17PEDATA register, 10-22PFDATA register, 10-25PGDATA register, 10-29PJDATA register, 10-32PKD

Index-vi MC68VZ328 User’s Manual Frame marker polarity bit, see FLMPOL bitFrame rate modulation, absence of control function, 8-7Free-running/restart

 Index Index-viiICEMCR register, 16-8ICEMSR register, 16-10ICR register, 9-8Ignore CTS1 (Tx control) bit, see NOCTS1 bitIgnore CTS2 (Tx control) bit,

Index-viii MC68VZ328 User’s Manual ISR register, 9-13IRQ6/PD[7:0] pin, 2-6IRQEN bitPWMC1 register, 15-4PWMC2 register, 15-8SPICONT2 register, 13-16TC

 Index Index-ixLCD screen width register, see LXMAX registerLCD self-refresh on bit, see REF_ON bitLCD shift clock polarity bit, see LCKPOL bitLCD so

Index-x MC68VZ328 User’s Manual MUART1 bit, 9-11MUART2 bit, 9-11multiplexing options for SDRAM, selecting, 7-5 to 7-6MWDT bit, 9-11NNIPR1 register, 1

 Index Index-xiPGSZ field, 7-14PHA bitSPICONT1 register, 13-7SPICONT2 register, 13-16Phase bit, see PHA bitPhase-locked loop, see PLLCLK output frequ

CPU Introduction 1-7 Table 1-2. Instruction SetMnemonic Description Mnemonic DescriptionABCD Add decimal with extend MOVEM Move multiple registersA

Index-xii MC68VZ328 User’s Manual bit 4, see RXD1/PE4 pinbit 5, see TXD1/PE5 pinbit 6, see RTS1/PE6 pindedicated I/O functions, 10-22registersdata re

 Index Index-xiiiinterrupt controller, 9-7 to 9-19LCD controller, 8-10 to 8-22PWM 1, 15-4 to 15-7PWM 2, 15-8 to 15-10SPI 1, 13-4 to 13-11SPI 2, 13-14

Index-xiv MC68VZ328 User’s Manual Refresh cycle field, see REF fieldRefresh cycle, calculation of REF field values, 7-13Refresh mode bit, see RM bitR

 Index Index-xvSB bit, 16-8SCR register, 5-2Screen starting address 31–1 field, see SSAx fieldSDRAM interface signals, 2-10SDRAM, selecting multiplex

Index-xvi MC68VZ328 User’s Manual programming with ENABLE bitdisabling writes, 13-14setting before changing other bits, 13-12registerscontrol/status

 Index Index-xviiUART clock I/O, see UCLK/DWE/PE3 pinTimer status register 1, see TSTAT1 registerTimer status register 2, see TSTAT2 registerTIN pina

Index-xviii MC68VZ328 User’s Manual signal nomenclature conventions, 14-1signalsUART 1 clear to send, see CTS1/PE7 pinUART 1 receive data, see RXD1/P

1-8 MC68VZ328 User’s Manual  Modules of the MC68VZ3281.3 Modules of the MC68VZ328In addition to the powerful 68000 processor, the DragonBall VZ con

Modules of the MC68VZ328 Introduction 1-9 and sleep. When in sleep mode, the CGM wakes up automatically when any unmasked external or internal interr

iv MC68VZ328 User’s Manual 2.7 Interrupt Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-10 MC68VZ328 User’s Manual  Modules of the MC68VZ3281.3.8 General-Purpose I/O (GPIO) LinesThe MC68VZ328 supports a maximum of 76 GPIO lines groupe

Modules of the MC68VZ328 Introduction 1-11 1.3.13 Pulse-Width Modulators (PWM)The MC68VZ328 has two pulse-width modulators (PWMs). Each of the pulse

1-12 MC68VZ328 User’s Manual  Modules of the MC68VZ328

 Signal Descriptions 2-1Chapter 2Signal DescriptionsThis chapter describes the MC68VZ328’s input and output signals, which are organized into functio

2-2 MC68VZ328 User’s Manual Signals Grouped by FunctionFigure 2-1. Signals Grouped by Function2.1 Signals Grouped by FunctionTable 2-1 on page 2-

Signals Grouped by Function Signal Descriptions 2-3Table 2-1. Signal Function GroupsFunction Group SignalsNumber of PinsTQFP PBGAPower VDD95Ground

2-4 MC68VZ328 User’s Manual Clock and System Control Signals2.2 Power and Ground SignalsThe MC68VZ328 microprocessor has three types of power pins.

Data Bus Signals Signal Descriptions 2-51.2 s before its voltage is higher than 1.2 V to ensure that the crystal oscillator starts and stabilizes. Se

2-6 MC68VZ328 User’s Manual Interrupt Controller Signals2.6 Bus Control SignalsThe bus control signals are used for both the configuration and oper

LCD Controller Signals Signal Descriptions 2-7•IRQ5/PF1—Interrupt Request 5 or Port F bit 1. This signal can be programmed as GPIO or as an interrupt

 Table of Contents v5.2.2 Peripheral Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45.2.

2-8 MC68VZ328 User’s Manual Timer Signals• LCONTRAST/PF0—LCD Contrast and Port F bit 0. This output is generated by the pulse-width modulator (PWM) i

Serial Peripheral Interface 2 Signals Signal Descriptions 2-92.11 Pulse-Width Modulator SignalsThere are two pulse-width modulator (PWM) modules in

2-10 MC68VZ328 User’s Manual SDRAM Interface Signals2.14 Chip-Select and EDO RAM Interface SignalsChip-select logic is used to provide maximum comp

In-Circuit Emulation (ICE) Signals Signal Descriptions 2-112.16 In-Circuit Emulation (ICE) SignalsThe ICE module is designed to support low-cost em

2-12 MC68VZ328 User’s Manual In-Circuit Emulation (ICE) Signals

 Memory Map 3-1 Chapter 3Memory MapThe memory map is a guide to all on-chip resources. When you configure your chip, refer to Figure 3-1 and either T

3-2 MC68VZ328 User’s Manual Programmer’s Memory Map3.1 Programmer’s Memory MapOn reset the base address used in the table is 0xFFFFF000 (or 0xXXFFF

Programmer’s Memory Map Memory Map 3-3 0xFFFFF310 IPR 32 Interrupt pending register 0x00000000 9-160xFFFFF314 ILCR 16 Interrupt level control registe

3-4 MC68VZ328 User’s Manual Programmer’s Memory Map0xFFFFF42A PFPUEN 8 Port F pull-up/pull-down enable register0xFF 10-270xFFFFF42B PFSEL 8 Port F se

Programmer’s Memory Map Memory Map 3-5 0xFFFFF600 TCTL1 16 Timer unit 1 control register 0x0000 12-60xFFFFF602 TPRER1 16 Timer unit 1 prescaler regi

vi MC68VZ328 User’s Manual 8.2.2.1 Format of the LCD Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48.2

3-6 MC68VZ328 User’s Manual Programmer’s Memory Map0xFFFFF912 UBAUD2 16 UART unit 2 baud control register 0x003F 14-120xFFFFF914 URX2 16 UART unit 2

Programmer’s Memory Map Memory Map 3-7 0xFFFFFB00 RTCTIME 32 RTC time of day register 0xXXXX00XX 11-30xFFFFFB04 RTCALRM 32 RTC alarm register 0x00000

3-8 MC68VZ328 User’s Manual Programmer’s Memory MapTable 3-2. Programmer’s Memory Map (Sorted by Register Name)Name Address Width Description Reset

Programmer’s Memory Map Memory Map 3-9 IODCR 0xFFFFF008 16 I/O drive control register 0x1FFF 5-6IPR 0xFFFFF310 32 Interrupt pending register 0x000000

3-10 MC68VZ328 User’s Manual Programmer’s Memory MapPBDIR 0xFFFFF408 8 Port B direction register 0x00 10-8PBPUEN 0xFFFFF40A 8 Port B pull-up enable

Programmer’s Memory Map Memory Map 3-11 PGSEL 0xFFFFF433 8 Port G select register 0x08 10-31PJDATA 0xFFFFF439 8 Port J data register 0xFF 10-32PJDIR

3-12 MC68VZ328 User’s Manual Programmer’s Memory MapRES 0xFFFFFA2B 8 Reserved ——RES 0xFFFFFC80 — Reserved — —RMCR 0xFFFFFA38 8 Refresh mode control r

Programmer’s Memory Map Memory Map 3-13 TPRER1 0xFFFFF602 16 Timer unit 1 prescaler register 0x0000 12-8TPRER2 0xFFFFF612 16 Timer unit 2 prescaler

3-14 MC68VZ328 User’s Manual Programmer’s Memory Map

 Clock Generation Module and Power Control Module 4-1Chapter 4Clock Generation Module and Power Control ModuleThis chapter describes the clock genera

 Table of Contents vii9.6.3 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-109

4-2 MC68VZ328 User’s Manual Introduction to the Clock Generation Module4.1 Introduction to the Clock Generation ModuleThe CGM produces four clock s

CGM Operational Overview Clock Generation Module and Power Control Module 4-34.2 CGM Operational OverviewThe CGM consists of six major parts, as sh

4-4 MC68VZ328 User’s Manual Detailed CGM Clock Descriptions4.3 Detailed CGM Clock DescriptionsSection 4.3.1, “CLK32 Clock Signal,” and Section 4.3.

Detailed CGM Clock Descriptions Clock Generation Module and Power Control Module 4-54.3.2.1 PLLCLK Initial Power-up Sequence Refer to Figure 4-3 fo

4-6 MC68VZ328 User’s Manual Detailed CGM Clock Descriptions4.3.2.2 PLL Frequency SelectionUsing the default settings for the PC and QC fields of th

Detailed CGM Clock Descriptions Clock Generation Module and Power Control Module 4-7Example 4-1. Configuring the PLLCLK FrequencyNEWFREQ equ someva

4-8 MC68VZ328 User’s Manual CGM Programming Model4.4 CGM Programming ModelThis section describes the two registers that enable and control the freq

CGM Programming Model Clock Generation Module and Power Control Module 4-9DISPLLBit 3Disable PLL—This bit, when set, disables the output of the PLL,

4-10 MC68VZ328 User’s Manual Introduction to the Power Control Module4.4.2 PLL Frequency Select RegisterThe PLL frequency select register (PLLFSR) c

Introduction to the Power Control Module Clock Generation Module and Power Control Module 4-114.5.1 Operating the PCMThe power control module has fo

viii MC68VZ328 User’s Manual 10.4.6 Port E Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-12 MC68VZ328 User’s Manual Introduction to the Power Control Module4.5.1.4 Sleep ModeUnlike burst or doze mode, sleep mode disables all of the cl

Introduction to the Power Control Module Clock Generation Module and Power Control Module 4-13Figure 4-4. Power Control Module Block DiagramIf a wa

4-14 MC68VZ328 User’s Manual Introduction to the Power Control Module4.5.4 Power Control RegisterThe power control register (PCTLR) enables the powe

 System Control 5-1Chapter 5System ControlThis chapter describes the system control register of the MC68VZ328 microprocessor. The system control regi

5-2 MC68VZ328 User’s Manual Programming Model5.2 Programming ModelThe following sections provide detailed programming information about the system

Programming Model System Control 5-3DMAPBit 2Double Map—This control bit controls the double-mapping function.0 = The on-chip registers are mapped at

5-4 MC68VZ328 User’s Manual Programming Model5.2.2 Peripheral Control RegisterThis register controls the PWM logical block operation, timer TIN/TOUT

Programming Model System Control 5-55.2.3 ID RegisterThis 32-bit read-only register shows the chip identification. The bit assignments for the regis

5-6 MC68VZ328 User’s Manual Programming Model5.2.4 I/O Drive Control RegisterThis register controls the driving strength of all I/O signals. By defa

 Chip-Select Logic 6-1Chapter 6Chip-Select Logic This chapter describes the chip-select logic’s function and operation and provides programming infor

 Table of Contents ix11.1.6.1 Minute Stopwatch Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-411.2 Programming Mo

6-2 MC68VZ328 User’s Manual Chip-Select OperationThe basic chip-select model allows the chip-select output signal to assert in response to an address

Chip-Select Operation Chip-Select Logic 6-3chip-select–controlled area can be programmed as read/write, which provides optimal memory use, as shown i

6-4 MC68VZ328 User’s Manual Programming Model6.2.3 Overlapping Chip-Select RegistersDo not program group address and chip-select registers to overla

Programming Model Chip-Select Logic 6-5CSGBB Chip-Select Group B Base Address Register 0x(FF)FFF102CSGBC Chip-Select Group C Base Address Register

6-6 MC68VZ328 User’s Manual Programming ModelCSGBD Chip-Select Group D Base Address Register 0x(FF)FFF1066.3.2 Chip-Select Upper Group Base Address

Programming Model Chip-Select Logic 6-7ReservedBit 11Reserved This bit is reserved and should be set to 0.BGBA[31:29]Bits 10–8MSB for Chip-Select B—

6-8 MC68VZ328 User’s Manual Programming Model6.3.3 Chip-Select RegistersThere are four 16-bit chip-select (CSA, CSB, CSC, and CSD) registers for eac

Programming Model Chip-Select Logic 6-9SIZBits 3–1Chip-Select Size—This field determines the memory range of the chip-select. For CSAx and CSBx, the

6-10 MC68VZ328 User’s Manual Programming ModelCSB Chip-Select Register B 0x(FF)FFF112BIT 1514 13 12 11 10 9 8 7 6 5 4 3 2 1BIT 0RO SOP ROP UPSIZFLASH

Programming Model Chip-Select Logic 6-11WS3–1Bits 6–4Wait State—This field determines the number of wait states added before an internal DTACK signal