Motorola MVME2300 Series Manuel d'utilisateur

MVME2300 SeriesVME Processor ModuleProgrammer’s ReferenceGuideV2300A/PG5Edition of June 2001

xNesting of Interrupt Events ...2-62Spurious Vector Generation...

2-30 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2When the FLBRD bit is set, Raven will handle read transactions originating from th

Raven Registershttp://www.motorola.com/computer/literature 2-312Table 2-7. Raven MPC Register MapBit --->01234567891011121314151617181920212223242

2-32 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Vendor ID/Device ID RegistersVENID Vendor ID. Identifies the manufacturer of the d

Raven Registershttp://www.motorola.com/computer/literature 2-332Revision ID RegisterREVID Revision ID. Identifies the Raven revision level. This regis

2-34 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2FLBRD Flush Before Read. If set, the Raven will guarantee that all PCI-initiated p

Raven Registershttp://www.motorola.com/computer/literature 2-352MIDx Master ID. Encoded as shown below to indicate who is currently the MPC bus master

2-36 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2MPC Arbiter Control RegisterThis register is not used in MVME2300 series boards.Pr

Raven Registershttp://www.motorola.com/computer/literature 2-372MPC Error Enable RegisterDFLT Default MPC Master ID. This bit determines which MCHK∗ p

2-38 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2SMAM PCI Signalled Master Abort Machine Check Enable. When this bit is set, the SM

Raven Registershttp://www.motorola.com/computer/literature 2-392MPC Error Status RegisterOVF Error Status Overflow. This bit is set when an error is d

xi8259 Mode...2-90Current Task Priority Level...

2-40 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2SERR PCI System Error. This bit is set when the PCI SERR∗ pin is asserted. The bit

Raven Registershttp://www.motorola.com/computer/literature 2-412MERAD MPC Error Address. This register captures the MPC address when the MATO bit is s

2-42 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2If the SMA or RTA bits are set, the register is defined by the following figure:WP

Raven Registershttp://www.motorola.com/computer/literature 2-432PCI Interrupt Acknowledge RegisterPIACK PCI Interrupt Acknowledge. Performing a read f

2-44 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2START Start Address. Determines the start address of a particular memory area on t

Raven Registershttp://www.motorola.com/computer/literature 2-452START Start Address. Determines the start address of a particular memory area on the M

2-46 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2WPEN Write-Post Enable. If set, write-posting is enabled for the corresponding MPC

Raven Registershttp://www.motorola.com/computer/literature 2-472REN Read Enable. If set, the corresponding MPC slave is enabled for read transactions.

2-48 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2All write operations to reserved registers will be treated as no-ops. That is, the

Raven Registershttp://www.motorola.com/computer/literature 2-492Table 2-9. Raven PCI I/O Register MapVendor ID/ Device ID RegistersVENID Vendor ID. I

xiiDRAM Attributes Register ...3-33DRAM Base Register...

2-50 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2PCI Command/ Status RegistersIOSP IO Space Enable. If set, the Raven will respond

Raven Registershttp://www.motorola.com/computer/literature 2-512DPAR Data Parity Detected. This bit is set when three conditions are met: 1) the Raven

2-52 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Revision ID/ Class Code RegistersREVID Revision ID. Identifies the Raven revision

Raven Registershttp://www.motorola.com/computer/literature 2-532RES Reserved. This bit is hard-wired to 0.IOBA I/O Base Address. These bits define the

2-54 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2PCI Slave Address (0,1,2 and 3) RegistersTo initiate an MPC cycle from the PCI bus

Raven Registershttp://www.motorola.com/computer/literature 2-552PCI Slave Attribute/ Offset (0,1,2 and 3) RegistersINV Invalidate Enable. If set, the

2-56 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2CONFIG_ADDRESS RegisterThe description of the CONFIG_ADDRESS register is presented

Raven Registershttp://www.motorola.com/computer/literature 2-572Perspective from the MPC bus in Little-Endian modeThe register fields are defined as f

2-58 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2BUS Bus Number. Configuration Cycles: Identifies a targeted bus number. If written

Raven Registershttp://www.motorola.com/computer/literature 2-592Conceptual perspective from the PCI busPerspective from the MPC bus in Big-Endian mode

xiiiUniverse Chip Problems after PCI Reset...4-14Description...

2-60 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Raven Interrupt ControllerThis section describes the general implementation of the

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-612The RavenMPIC receives interrupt inputs from:❏ 16 external sources❏ Four in

2-62 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Nesting of Interrupt EventsA processor is guaranteed never to have an in-service i

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-632passed directly to processor 0. If the pass-through mode is disabled, the 8

2-64 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Interrupt Delivery ModesThe direct and distributed interrupt delivery modes are su

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-652Block Diagram DescriptionThe description of the block diagram focuses on th

2-66 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Program-Visible RegistersThese are the registers which software can access. They a

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-672Interrupt Request Register (IRR)There is an Interrupt Request register (IRR

2-68 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Then one of these bits is delivered to each Interrupt Selector. Since this interru

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-692There is the possibility of a priority tie between the two processors when

2-70 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2IPI0 VECTOR-PRIORITY REGISTER $010A0IPI1 VECTOR-PRIORITY REGISTER $010B0IPI2 VECTO

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-712INT. SRC. 2 VECTOR-PRIORITY REGISTER $10040INT. SRC. 2 DESTINATION REGISTER

2-72 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2INT. SRC. 15 VECTOR-PRIORITY REGISTER $101E0INT. SRC. 15 DESTINATION REGISTER $101

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-732Feature Reporting RegisterNIRQ NUMBER OF IRQs. The number of the highest ex

2-74 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Global Configuration RegisterR Reset Controller. Writing a 1 to this bit forces t

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-752Vendor Identification RegisterTwo of the fields in the Vendor Identificatio

2-76 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2The Soft Reset input to the MPC603 or MPC604 is negative-edge-sensitive.IPI Vector

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-772Spurious Vector RegisterVECTOR Interrupt Vector. This vector is returned wh

2-78 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Timer Current Count RegistersT Toggle. This bit toggles when ever the current coun

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-792CI Count Inhibit. Setting this bit to 1 inhibits counting for this timer. S

xvList of FiguresFigure 1-1. MVME2300 Series System Block Diagram ...1-5Figure 1-2. VMEbus Master Mapping...

2-80 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2PRIOR Interrupt Priority. Priority 0 is the lowest and 15 is the highest. Note tha

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-812External Source Vector/Priority RegistersMASK Mask. Setting this bit disabl

2-82 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2PRIOR Interrupt Priority. Priority 0 is the lowest and 15 is the highest. Note tha

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-832Raven-Detected Errors Vector/Priority RegisterMASK Mask. Setting this bit d

2-84 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Raven-Detected Errors Destination RegisterThis register indicates the possible des

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-852Dispatch register has two addresses. These registers are considered to be p

2-86 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Interrupt Acknowledge RegistersOn PowerPC-based systems, Interrupt Acknowledge is

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-872processing for the highest-priority interrupt currently in service by the a

2-88 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2interrupt source was the 8259, the interrupt handler issues an EOI request to the

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-892Interprocessor InterruptsFour interprocessor interrupt (IPI) channels are p

2-90 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2EOI RegisterEach processor has a private EOI register which is used to signal the

Raven Interrupt Controllerhttp://www.motorola.com/computer/literature 2-912Architectural NotesThe hardware and software overhead required to update th

3-133Falcon ECC Memory ControllerChip SetIntroductionThe Falcon DRAM controller ASIC is designed for the MVME2300 family of boards. It is used in sets

3-2 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Block DiagramsFigure 3-1 depicts a Falcon pair as it would be conne

Block Diagramshttp://www.motorola.com/computer/literature 3-33Figure 3-2. Falcon Internal Data Paths (Simplified)1901 9609(64 Bits)PowerPCSideRD[0:63

3-4 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Figure 3-3. Overall DRAM ConnectionsDRAMBLOCK AUPPERDRAMBLOCK BUPP

Functional Descriptionhttp://www.motorola.com/computer/literature 3-53Functional DescriptionThe following sections describe the logical function of th

3-6 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3the access time. Further savings come when the new address cycle is

Functional Descriptionhttp://www.motorola.com/computer/literature 3-73Notes1. These numbers assume that the PowerPC 60x bus master is doing address pi

xviiList of TablesTable 1-1. Features: MVME2300 Series...1-2Table 1-2. Default Proces

3-8 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Table 3-3. PowerPC 60x Bus to DRAM Access Timing — 60ns Page Devic

Functional Descriptionhttp://www.motorola.com/computer/literature 3-93Table 3-4. PowerPC Bus to DRAM Access Timing — 50ns Hyper DevicesNotes1. These

3-10 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3ROM/Flash SpeedsThe Falcon pair provides the interface for two blo

Functional Descriptionhttp://www.motorola.com/computer/literature 3-113PowerPC 60x Bus InterfaceThe Falcon pair has a PowerPC slave interface only. It

3-12 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Cache Coherency RestrictionsThe PowerPC 60x GBL_ signal must not b

Functional Descriptionhttp://www.motorola.com/computer/literature 3-133Error ReportingThe Falcon pair checks data from the DRAM during single- and fou

3-14 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Error LoggingECC error logging is facilitated by the Falcon becaus

Functional Descriptionhttp://www.motorola.com/computer/literature 3-1532. The base address for each block is software programmable. At reset, Block A’

3-16 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Table 3-8. PowerPC 60x to ROM/Flash Address Mapping — ROM/Flash 1

Functional Descriptionhttp://www.motorola.com/computer/literature 3-173Table 3-9. PowerPC 60x to ROM/Flash Address Mapping — ROM/Flash64 Bits Wide (

xviiiTable 3-4. PowerPC Bus to DRAM Access Timing — 50ns Hyper Devices ...3-9Table 3-5. PowerPC 60x Bus to ROM/Flash Access Timing — 64 Bits(3

3-18 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Refresh/ScrubThe Refresh/Scrub operation varies according to which

Functional Descriptionhttp://www.motorola.com/computer/literature 3-193Blocks A and/or B Present, Blocks C and/or D PresentThe Falcon pair performs re

3-20 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3DRAM ArbitrationThe Falcon pair has 3 different entities that can

Programming Modelhttp://www.motorola.com/computer/literature 3-213External Register SetEach chip in the Falcon pair has an external register chip sele

3-22 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Accesses to the CSR are mapped differently depending on whether th

Programming Modelhttp://www.motorola.com/computer/literature 3-233Figure 3-5. Data Path for Writes to the Falcon Internal CSRsExternal register data

3-24 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Figure 3-6. Memory Map for Byte Reads to CSR1905 9609Upper Falcon

Programming Modelhttp://www.motorola.com/computer/literature 3-253Figure 3-7. Memory Map for Byte Writes to Internal Register Set and Test SRAM1906 9

3-26 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Figure 3-8. Memory Map for 4-Byte Reads to CSRFigure 3-9. Memory

Programming Modelhttp://www.motorola.com/computer/literature 3-273Register SummaryTable 3-10 shows a summary of the CSR. Note that the table shows onl

xixAbout This ManualThe MVME2300 Series VME Processor Module Programmer’s Reference Guide provides board-level information and detailed ASIC informati

3-28 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Table 3-10. Register SummaryBIT # ---->01234567891011121314151

Programming Modelhttp://www.motorola.com/computer/literature 3-293FEF800A0FEF800A8TEST D1 (Upper 8 Bits)FEF800B0TEST D1 (Middle 32 Bits)FEF800B8TEST D

3-30 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Notes 1. All shaded bit fields are reserved and read as zeros.2. A

Programming Modelhttp://www.motorola.com/computer/literature 3-313Revision ID/ General Control RegisterREVID The REVID bits are hard-wired to indicate

3-32 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3ram fref Some DRAMs require that they be refreshed at the rate of

Programming Modelhttp://www.motorola.com/computer/literature 3-333DRAM Attributes Register!CautionTo satisfy DRAM component requirements before the me

3-34 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3 It is important that all of the ram a/b/c/d siz0-2 bits be set to

Programming Modelhttp://www.motorola.com/computer/literature 3-353DRAM Base RegisterRAM A/B/C/D BASEThese control bits define the base address for the

3-36 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3The output of the chip prescale counter is used by the refresher/s

Programming Modelhttp://www.motorola.com/computer/literature 3-373So, for example, the check-bits that correspond to the 64 bits of data found in norm

© Copyright 2001 Motorola, Inc.All rights reserved.Printed in the United States of America.Motorola® and the Motorola logo are registered trademarks o

xxThis manual is intended for anyone who designs OEM systems, adds capability to an existing compatible system, or works in a lab environment for expe

3-38 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set31. Disable scrub writes by clearing the swen bit if it is set.2. S

Programming Modelhttp://www.motorola.com/computer/literature 3-393tien When tien is set, the setting of the tpass or the tfail bit causes the INT_ sig

3-40 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Unlike most of the other registers, however, it is normal for this

Programming Modelhttp://www.motorola.com/computer/literature 3-413DRAM. If escb is 0, it indicates that the PowerPC 60x bus master was accessing DRAM.

3-42 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3bit error (independent of the state of the elog bit). It is cleare

Programming Modelhttp://www.motorola.com/computer/literature 3-433Scrub/Refresh Registerscb0,scb1 These bits increment every time the scrubber complet

3-44 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Refresh/Scrub Address RegisterROW ADDRESSThese bits form the row a

Programming Modelhttp://www.motorola.com/computer/literature 3-453ROM A Base/Size RegisterROM A BASEThese control bits define the base address for ROM

3-46 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3bits wide, where each Falcon interfaces to 32 bits. rom_a_64 match

Programming Modelhttp://www.motorola.com/computer/literature 3-473rom a en When rom a en is set, accesses to Block A ROM/Flash in the address range se

xxiOverview of ContentsChapter 1, Board Description and Memory Maps, describes the board-level hardware features of MVME2300 series VME processor modu

3-48 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3ROM B Base/Size RegisterROM B BASEThese control bits define the ba

Programming Modelhttp://www.motorola.com/computer/literature 3-493rom_b_64 matches the inverse of the value that was on the CKD3 pin at power-up reset

3-50 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3DRAM Tester Control Registers!CautionThe tester should not be used

Programming Modelhttp://www.motorola.com/computer/literature 3-513Power-Up Reset Status Register 1PR_STAT1PR_STAT1 (power-up reset status) reflects th

3-52 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3External Register SetEXTERNAL REGISTER SETThe EXTERNAL REGISTER SE

Software Considerationshttp://www.motorola.com/computer/literature 3-533Software ConsiderationsThis section contains information that may be helpful i

3-54 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3As with DRAM, software should not change control register bits tha

Software Considerationshttp://www.motorola.com/computer/literature 3-55310. Make sure that no other devices respond in the range from $00000000 to $40

3-56 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Each size that is checked has a specific set of locations that mus

Software Considerationshttp://www.motorola.com/computer/literature 3-573ECC CodesWhen the Falcon reports a single-bit error, software can use the synd

xxiiIn all your correspondence, please list your name, position, and company. Be sure to include the title and part number of the manual and tell how

3-58 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3rd8 $25 rd24 $49 rd40 $52 rd56 $94rd9 $26 rd25 $89 rd41 $62 rd57 $

Software Considerationshttp://www.motorola.com/computer/literature 3-593Table 3-21. Single-Bit Errors Ordered by Syndrome CodeSyn-dromeBit Syn-dromeB

3-60 Computer Group Literature Center Web SiteFalcon ECC Memory Controller Chip Set3Data PathsBecause of the Falcon “pair” architecture, data paths ca

Software Considerationshttp://www.motorola.com/computer/literature 3-613Table 3-22. PowerPC Data to DRAM Data MappingPowerPC DRAM ArrayA[27] A[28] Da

4-144Universe (VMEbus to PCI) ChipIntroductionThis chapter describes the VMEbus interface on MVME2300 series boards, the CA91C042 Universe ASIC. The U

4-2 Computer Group Literature Center Web SiteUniverse (VMEbus to PCI) Chip4The following table summarizes the characteristics of the Universe ASIC.Tab

Block Diagramhttp://www.motorola.com/computer/literature 4-34Block DiagramThe descriptions in the following sections make reference to the functional

4-4 Computer Group Literature Center Web SiteUniverse (VMEbus to PCI) Chip4Figure 4-1. Architectural Diagram for the UniverseVMEbus InterfaceThis sec

Functional Descriptionhttp://www.motorola.com/computer/literature 4-54the Universe. Write data is transferred to the PCI resource from the RXFIFO with

xxiiiFor example, “12” is the decimal number twelve, and “$12” is the decimal number eighteen. Unless otherwise specified, all address references are

4-6 Computer Group Literature Center Web SiteUniverse (VMEbus to PCI) Chip4Universe as PCI SlaveRead transactions from the PCI bus are always processe

Functional Descriptionhttp://www.motorola.com/computer/literature 4-74Interrupt sources mapped to PCI bus interrupts are generated on one of the INT∗[

4-8 Computer Group Literature Center Web SiteUniverse (VMEbus to PCI) Chip4Following specific rules of DMAFIFO operation (refer to FIFO Operation and

Functional Descriptionhttp://www.motorola.com/computer/literature 4-94Figure 4-2 summarizes the supported register access mechanisms.Figure 4-2. UCSR

4-10 Computer Group Literature Center Web SiteUniverse (VMEbus to PCI) Chip4Address offsets in Table 4-2 below apply to accesses from the PCI bus and

Functional Descriptionhttp://www.motorola.com/computer/literature 4-11411C PCI Slave Image 1 Bound Address Register LSI1_BD120 PCI Slave Image 1 Trans

4-12 Computer Group Literature Center Web SiteUniverse (VMEbus to PCI) Chip4218 DMA Command Packet Pointer DCPP21C Universe Reserved220 DMA General Co

Functional Descriptionhttp://www.motorola.com/computer/literature 4-134F08 VMEbus Slave Image 0 Bound Address Register VSI0_BDF0C VMEbus Slave Image 0

4-14 Computer Group Literature Center Web SiteUniverse (VMEbus to PCI) Chip4!CautionRegister space marked as “Reserved” should not be overwritten. Uni

Functional Descriptionhttp://www.motorola.com/computer/literature 4-154The Configuration Space enables are not the only things enabled after a PCI res

xxivindicate that the bit is in the state that disables the function it controls. In all tables, the terms 0 and 1 are used to describe the actual val

4-16 Computer Group Literature Center Web SiteUniverse (VMEbus to PCI) Chip4"Following are the most recently discovered bugs which will be addres

Functional Descriptionhttp://www.motorola.com/computer/literature 4-1741. Manually call each Universe initialization word, to duplicate typical operat

4-18 Computer Group Literature Center Web SiteUniverse (VMEbus to PCI) Chip4CTL BS BD TO800000 0 0 02. Run the i

Functional Descriptionhttp://www.motorola.com/computer/literature 4-19480821000 3000000 23000000 3d0000007. Do a bye.The values before the init code r

4-20 Computer Group Literature Center Web SiteUniverse (VMEbus to PCI) Chip4LSI0_CTL register: EN, VAS, LASLSI0_BS register: Bits [31:28]LSI0_BD regis

5-155Programming DetailsIntroductionThis chapter discusses details of several programming functions that are not tied to any specific ASIC chip.PCI Ar

5-2 Computer Group Literature Center Web SiteProgramming Details5Interrupt HandlingThe interrupt architecture of the MVME2300 series VME processor mod

Interrupt Handlinghttp://www.motorola.com/computer/literature 5-35RavenMPICThe Raven ASIC has a built-in interrupt controller that meets the Multi-Pro

5-4 Computer Group Literature Center Web SiteProgramming Details5Notes1. Interrupt from the PCI/ISA Bridge.2. Interrupt from the Falcon chip set for a

Interrupt Handlinghttp://www.motorola.com/computer/literature 5-55interrupt can be routed to the same ISA IRQ line. The PIB can be programmed to handl

1-111Board Description and MemoryMapsIntroductionThis manual provides programming information for MVME2300 and MVME2300SC VME processor modules. Exten

5-6 Computer Group Literature Center Web SiteProgramming Details5The assignments of the PCI and ISA interrupts supported by the PIB are as follows:Tab

ISA DMA Channelshttp://www.motorola.com/computer/literature 5-75Notes1. Internally generated by the PIB.2. After a reset, all ISA IRQ interrupt lines

5-8 Computer Group Literature Center Web SiteProgramming Details5ExceptionsSources of ResetThere are eight potential sources of reset on MVME2300 seri

Exceptionshttp://www.motorola.com/computer/literature 5-95The following table shows which devices are affected by the various reset sources:Soft Reset

5-10 Computer Group Literature Center Web SiteProgramming Details5Error Notification and HandlingThe Raven ASIC and Falcon chip set can detect certain

Endian Issueshttp://www.motorola.com/computer/literature 5-115Endian IssuesThe MVME2300 series supports both little-endian and big-endian software. Be

5-12 Computer Group Literature Center Web SiteProgramming Details5Figure 5-4. Little-Endian ModeEA Modification (XOR)1899 9609RavenUniverseFalconsDRA

Endian Issueshttp://www.motorola.com/computer/literature 5-135Processor/Memory DomainThe MPC603 and MPC604 processors can operate in both big-endian a

5-14 Computer Group Literature Center Web SiteProgramming Details5big-endian mode, there should be no endian issues for Ethernet data. Big-endian soft

ROM/Flash Initializationhttp://www.motorola.com/computer/literature 5-155ROM/Flash InitializationThere are two methods of injecting code into the Flas

1-2 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Summary of FeaturesThere are many models based on the MVME2300 series a

AA-1ARelated DocumentationMotorola Computer Group DocumentsThe Motorola publications listed below are referenced in this manual. You can obtain paper

A-2 Computer Group Literature Center Web SiteRelated DocumentationAManufacturers’ DocumentsFor additional information, refer to the following table fo

Manufacturers’ Documentshttp://www.motorola.com/computer/literature A-3APowerPC® Microprocessor Family: The Programming Environments for 32-Bit Microp

A-4 Computer Group Literature Center Web SiteRelated DocumentationARelated SpecificationsFor additional information, refer to the following table for

Related Specificationshttp://www.motorola.com/computer/literature A-5APeripheral Component Interconnect (PCI) Local Bus Specification, Revision 2.0PCI

GL-1Glossary10Base-5 An Ethernet implementation in which the physical medium is a doubly shielded, 50-ohm coaxial cable capable of carrying data at 10

GlossaryGL-2 Computer Group Literature Center Web SiteGLOSSARYbig-endian A byte-ordering method in memory where the address n of a word corresponds to

http://www.motorola.com/computer/literature GL-3GLOSSARYEIDE Enhanced Integrated Drive Electronics. An improved version of IDE, with faster data rates

System Block Diagramhttp://www.motorola.com/computer/literature 1-31System Block DiagramThe MVME2300 series does not provide any look-aside external c

GlossaryGL-4 Computer Group Literature Center Web SiteGLOSSARYISA (bus) Industry Standard Architecture (bus). The de facto standard system bus for IBM

http://www.motorola.com/computer/literature GL-5GLOSSARYPHB PCI Host Bridgephysical address A binary address that refers to the actual location of inf

GlossaryGL-6 Computer Group Literature Center Web SiteGLOSSARYSCSA Signal Computing System Architecture. A hardware model for computer telephony serve

http://www.motorola.com/computer/literature GL-7GLOSSARYthin Ethernet See 10base-2.twisted-pair Ethernet See 10Base-T.UART Universal Asynchronous Rec

IN-1IndexNumerics16550 UART registers 1-318259 mode (Raven interrupt controller) 2-90,5-4Aaccess timingDRAM 3-7, 3-8, 3-9ROM/Flash 3-10address mapping

IndexIN-2 Computer Group Literature Center Web SiteINDEXCONFIG_DATA register 2-58configuration registers (Raven PCI BridgeASIC) 2-11connectors, MVME23

http://www.motorola.com/computer/literature IN-3INDEXreading internal CSRs 3-22single-beat reads/writes 3-6software considerations 3-53writing to inte

IndexIN-4 Computer Group Literature Center Web SiteINDEXMemory Base register 2-53Memory Configuration register (MEMCR)1-27memory mapsbyte reads to CSR

http://www.motorola.com/computer/literature IN-5INDEXSlave Attribute/ Offset (0,1,2 and 3) reg-isters 2-55slave command types 2-15slave function (Rave

1-4 Computer Group Literature Center Web SiteBoard Description and Memory Maps1slots. Standard I/O functions are provided by the UART device which res

IndexIN-6 Computer Group Literature Center Web SiteINDEXLM/SIG Status 1-39Location Monitor Lower Base Address1-41Location Monitor Upper Base Address1-

http://www.motorola.com/computer/literature IN-7INDEXPCI Slave Address (0,1,2 and 3) 2-54PCI Slave Attribute/ Offset (0,1,2 and 3)2-55Prescaler Adjust

IndexIN-8 Computer Group Literature Center Web SiteINDEXstatus bit, definition of xxiiisymbols, use of xxiisyndrome codes, ECC (Falcon chip set) 3-57S

System Block Diagramhttp://www.motorola.com/computer/literature 1-51Figure 1-1. MVME2300 Series System Block DiagramSYSTEMREGISTERS2067 9708PMC FRONT

Safety SummaryThe following general safety precautions must be observed during all phases of operation, service, and repair of thisequipment. Failure

1-6 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Functional DescriptionThe MVME2300 series is a family of single-slot VM

Programming Modelhttp://www.motorola.com/computer/literature 1-71PCI interfaceMVME2300 and MVME2300SC boards are equipped with two IEEE 1386.1 PCI Mez

1-8 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Default Processor Memory MapAfter a reset, the Raven ASIC and the Falco

Programming Modelhttp://www.motorola.com/computer/literature 1-91Processor CHRP Memory MapThe following table shows a recommended CHRP memory map from

1-10 Computer Group Literature Center Web SiteBoard Description and Memory Maps13. Programmable via Raven ASIC.4. CHRP requires the starting address f

Programming Modelhttp://www.motorola.com/computer/literature 1-111Processor PREP Memory MapThe Raven/Falcon chip set can be programmed for PREP-compat

1-12 Computer Group Literature Center Web SiteBoard Description and Memory Maps14. The first Megabyte of ROM/Flash bank A appears at this range after

Programming Modelhttp://www.motorola.com/computer/literature 1-131PCI Memory MapsThe PCI memory map is controlled by the Raven ASIC and the Universe A

1-14 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Notes1. Programmable via the Raven’s PCI Configuration registers. For

Programming Modelhttp://www.motorola.com/computer/literature 1-151The following table shows the programmed values for the associated Raven PCI registe

FlammabilityAll Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers.EMI Caution!

1-16 Computer Group Literature Center Web SiteBoard Description and Memory Maps1PCI PREP Memory MapThe following table shows a PCI memory map of the M

Programming Modelhttp://www.motorola.com/computer/literature 1-171Notes1. Programmable via the Raven’s PCI Configuration registers. For the MVME2300 s

1-18 Computer Group Literature Center Web SiteBoard Description and Memory Maps1The following table shows the programmed values for the associated Rav

Programming Modelhttp://www.motorola.com/computer/literature 1-191The next table shows the programmed values for the associated Universe PCI registers

1-20 Computer Group Literature Center Web SiteBoard Description and Memory Maps1VMEbus MappingThe processor can access any address range in the VMEbus

Programming Modelhttp://www.motorola.com/computer/literature 1-211Notes1. Programmable mapping done by the Raven ASIC.2. Programmable mapping via the

1-22 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Figure 1-3. VMEbus Slave MappingNotes1. Programmable mapping via the

Programming Modelhttp://www.motorola.com/computer/literature 1-231The following table shows the programmed values for the associated Universe register

1-24 Computer Group Literature Center Web SiteBoard Description and Memory Maps1The register values in the table yield the following VMEbus slave map:

Programming Modelhttp://www.motorola.com/computer/literature 1-251System Configuration Register (SYSCR)The states of the RD[0:31] DRAM data pins, whic

CE Notice (European Community)Motorola Computer Group products with the CE marking comply with the EMC Directive (89/336/EEC). Compliance with this di

1-26 Computer Group Literature Center Web SiteBoard Description and Memory Maps1SYSXC System External Cache Size. The MVME2300 series does not offer a

Programming Modelhttp://www.motorola.com/computer/literature 1-271Memory Configuration Register (MEMCR)The states of the RD[00:31] DRAM data pins, whi

1-28 Computer Group Literature Center Web SiteBoard Description and Memory Maps1M_SPD[0:1] Memory Speed. This field relays the memory speed informatio

Programming Modelhttp://www.motorola.com/computer/literature 1-291L2_PLL[0:3]L2 Core Frequency to L2 Frequency divider. This field is encoded as follo

1-30 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Processor 0 External Cache Control Register (P0XCCR)The MVME2300 and M

ISA Local Resource Bushttp://www.motorola.com/computer/literature 1-311ISA Local Resource BusW83C553 PIB RegistersThe PIB contains ISA Bridge I/O regi

1-32 Computer Group Literature Center Web SiteBoard Description and Memory Maps1General-Purpose Readable JumpersHeaders J10 (on the MVME2300SC) and J1

ISA Local Resource Bushttp://www.motorola.com/computer/literature 1-331The NVRAM/RTC Address Strobe 0 register latches the lower 8 bits of the address

1-34 Computer Group Literature Center Web SiteBoard Description and Memory Maps1The following subsections describe the configuration and status regist

ISA Local Resource Bushttp://www.motorola.com/computer/literature 1-351Base Module Feature RegisterThe Base Module Feature register is an 8-bit regist

Limited and Restricted Rights LegendIf the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following n

1-36 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Base Module Status Register (BMSR)The Base Module Status register is a

ISA Local Resource Bushttp://www.motorola.com/computer/literature 1-371Seven-Segment Display RegisterNote This register is NOT USED on the MVME2300-se

1-38 Computer Group Literature Center Web SiteBoard Description and Memory Maps1These registers are described in the following subsections.LM/SIG Cont

ISA Local Resource Bushttp://www.motorola.com/computer/literature 1-391SET_LM1Writing a 1 to this bit will set the LM1 status bit.SET_LM0Writing a 1 t

1-40 Computer Group Literature Center Web SiteBoard Description and Memory Maps1EN_LM1 When the EN_LM1 bit is set, an LM/SIG Interrupt 1 is generated

ISA Local Resource Bushttp://www.motorola.com/computer/literature 1-411Location Monitor Upper Base Address RegisterThe Location Monitor Upper Base Add

1-42 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Semaphore Register 1Semaphore Register 1 is an 8-bit register located

ISA Local Resource Bushttp://www.motorola.com/computer/literature 1-431VME Geographical Address Register (VGAR)The VME Geographical Address register i

1-44 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Z8536 CIO Port PinsThe following table shows the signal function and p

ISA Local Resource Bushttp://www.motorola.com/computer/literature 1-451ISA DMA ChannelsNo ISA DMA channels are implemented on MVME2300 series boards.P

viiContentsAbout This ManualSummary of Changes... xxOve

2-122Raven PCI Bridge ASICIntroductionThis chapter describes the architecture and usage of the Raven ASIC, a PowerPC-to-PCI-Local-Bus bridge controlle

2-2 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Block DiagramFigure 2-1 shows a functional block diagram of the Raven ASIC. The Rav

Block Diagramhttp://www.motorola.com/computer/literature 2-32Figure 2-1. Raven Block Diagram1914 9702Data Path ‘B’MuxFIFOEndianMuxFIFOEndianData Path

2-4 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Functional DescriptionThe Raven data path logic is subdivided into the following fu

Functional Descriptionhttp://www.motorola.com/computer/literature 2-52Figure 2-2. MPC-to-PCI Address DecodingThe Raven ASIC imposes no limits on how

2-6 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2Figure 2-3. MPC to PCI Address TranslationYou should take care to assure that all

Functional Descriptionhttp://www.motorola.com/computer/literature 2-72Table 2-2. Command Types — MPC Slave ResponseMPC Transfer TypeTransfer Encoding

2-8 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2MPC Write PostingThe MPC write FIFO stores up to eight data beats in any combinatio

Functional Descriptionhttp://www.motorola.com/computer/literature 2-92Notes1. Read-ahead mode should not be used when data coherency may be a problem,

viiiCPU Control Register ... 1-30ISA Local Resource Bus...

2-10 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2enabled, the MPC master will structure its bus request actions according to the re

Functional Descriptionhttp://www.motorola.com/computer/literature 2-112The PCI interface may operate at any clock speed up to 33MHz. The PCLK input mu

2-12 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2MPC Bus Address SpaceThe Raven will map MPC address space into PCI Memory space us

Functional Descriptionhttp://www.motorola.com/computer/literature 2-132Figure 2-5. PCI to MPC Address TranslationAll Raven address decoders are prior

2-14 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2PCI SlaveThe PCI slave provides the control logic needed to interface the PCI bus

Functional Descriptionhttp://www.motorola.com/computer/literature 2-152Command TypesTable 2-4 shows which types of PCI cycles the slave has been desig

2-16 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2The slave will honor only the Linear Incrementing addressing mode. The slave will

Functional Descriptionhttp://www.motorola.com/computer/literature 2-172ParityThe PCI slave supports address parity error detection, data parity genera

2-18 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2The PCI master can support Critical Word First (CWF) burst transfers. The PCI mast

Functional Descriptionhttp://www.motorola.com/computer/literature 2-192AddressingThe PCI master will generate all memory transactions using the linear

ixPCI Master...2-17Generating PCI Cycles ...

2-20 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2ArbitrationThe PCI master can support parking on the PCI bus. If the PCI master st

Functional Descriptionhttp://www.motorola.com/computer/literature 2-212Generating PCI CyclesFour basic types of bus cycles can be generated on the PCI

2-22 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2The Raven will perform spread I/O addressing when the MEM bit is clear and the IOM

Functional Descriptionhttp://www.motorola.com/computer/literature 2-232Configuration mechanism #1 uses an address register/data register format. Perfo

2-24 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2IDSEL connected to the address bit being asserted will be selected for a configura

Functional Descriptionhttp://www.motorola.com/computer/literature 2-252Generating PCI Interrupt Acknowledge CyclesPerforming a read from the PIACK reg

2-26 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2.Figure 2-7. Big- to Little-Endian Data Swap1916 9610DH07-00DH15-08DH23-16DH31-24

Functional Descriptionhttp://www.motorola.com/computer/literature 2-272When MPC Devices are Little-EndianWhen all MPC devices are operating in little-

2-28 Computer Group Literature Center Web SiteRaven PCI Bridge ASIC2With respect with the PCI bus, the RavenMPIC registers and the configuration regis

Functional Descriptionhttp://www.motorola.com/computer/literature 2-292When any bit in the MPC Error Status register is set, the Raven ASIC will attem