Motorola MVME2400 Series Manuel de service

MVME2400-SeriesVME Processor ModuleProgrammer’sReference GuideV2400A/PG1

xHeader Type Register... 2-99MPIC I/O Base Address Register ...

2-42 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Each timer is composed of a prescaler an

Functional Descriptionhttp://www.mcg.mot.com/literature 2-432The WDTxCNTL register will always become unarmed after the second write regardless of byt

2-44 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2PCI/PPC Contention HandlingThe PHB has a

Functional Descriptionhttp://www.mcg.mot.com/literature 2-452The PCI Master must make the determination to perform the resolution function since it mu

2-46 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Speculative PCI RequestThere is a case w

Functional Descriptionhttp://www.mcg.mot.com/literature 2-472All PCI Configuration cycles intended for internal PHB registers will also be delayed if

2-48 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2❏ Write posted transactions originated f

Multi-Processor Interrupt Controller (MPIC) Functional Descriptionhttp://www.mcg.mot.com/literature 2-492Multi-Processor Interrupt Controller (MPIC) F

2-50 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2❏ Direct/Multicast interrupt delivery fo

Multi-Processor Interrupt Controller (MPIC) Functional Descriptionhttp://www.mcg.mot.com/literature 2-512Figure 2-8. Serial Mode Interrupt ScanUsing

xiPage Holding ...3-8SDRAM Speeds...

2-52 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Processor’s Current Task PriorityEach pr

Multi-Processor Interrupt Controller (MPIC) Functional Descriptionhttp://www.mcg.mot.com/literature 2-532Interprocessor Interrupts (IPI)Processor 0 an

2-54 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2TimersThere is a divide by eight pre-sca

Multi-Processor Interrupt Controller (MPIC) Functional Descriptionhttp://www.mcg.mot.com/literature 2-552In the distributed delivery mode, the interru

2-56 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Figure 2-9. MPIC Block DiagramProgram V

Multi-Processor Interrupt Controller (MPIC) Functional Descriptionhttp://www.mcg.mot.com/literature 2-572Program Visible RegistersThese are the regist

2-58 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Interrupt Request Register (IRR)There is

Multi-Processor Interrupt Controller (MPIC) Functional Descriptionhttp://www.mcg.mot.com/literature 2-592Then one of these bits are delivered to each

2-60 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2There is a possibility for a priority ti

Multi-Processor Interrupt Controller (MPIC) Functional Descriptionhttp://www.mcg.mot.com/literature 2-612the 8259. If none of the nested interrupt mod

xiiROM B Base/Size Register...3-57ROM Speed Attributes Registers...

2-62 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2OperationInterprocessor InterruptsFour i

Multi-Processor Interrupt Controller (MPIC) Functional Descriptionhttp://www.mcg.mot.com/literature 2-632EOI RegisterEach processor has a private EOI

2-64 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2overhead, the interrupt controller archi

Registershttp://www.mcg.mot.com/literature 2-652RegistersThis section provides a detailed description of all PHB registers. The section is divided int

2-66 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2 Table 2-16. PPC Register Map for PHBBi

Registershttp://www.mcg.mot.com/literature 2-672$FEFF0064 WDT1STAT$FFEF0068 WDT2CNTL$FEFF006C WDT2STAT$FEFF0070 GPREG0(Upper)$FEFF0074 GPREG0(Lower)$F

2-68 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Vendor ID/Device ID RegistersVENID Vendo

Registershttp://www.mcg.mot.com/literature 2-692General Control-Status/Feature RegistersThe General Control-Status Register (GCSR) provides miscellane

2-70 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2enabled, the PPC master will request the

Registershttp://www.mcg.mot.com/literature 2-712.PPC Arbiter/PCI Arbiter Control RegistersThe PPC Arbiter Register (XARB) provides control and status

xiiiDMA Controller ...4-7Registers - Universe II Control and St

2-72 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2FSWx Flatten Single Write. This field is

Registershttp://www.mcg.mot.com/literature 2-732The PCI Arbiter Register (PARB) provides control and status for the PCI Arbiter. Refer to the section

2-74 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2HIERx Hierarchy. This field is used by t

Registershttp://www.mcg.mot.com/literature 2-752POL Park on lock. If set, the PCI Arbiter will park the bus on the master that successfully obtains a

2-76 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2SPRQ Speculative PCI Request. If set, th

Registershttp://www.mcg.mot.com/literature 2-772RLRTx Read Lock Resolution Threshold. This field is used by the PHB to determine a PPC bound read FIFO

2-78 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2PPC Error Test/Error Enable RegisterThe

Registershttp://www.mcg.mot.com/literature 2-792DFLT Default PPC Master ID. This bit determines which MCHK_ pin will be asserted for error conditions

2-80 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2XBTOI PPC Address Bus Time-out Interrupt

Registershttp://www.mcg.mot.com/literature 2-812PPC Error Status RegisterThe Error Status Register (ESTAT) provides an array of status bits pertaining

xivExample VPD SROM ... B-8GlossaryAbbreviations, Acronyms, and Te

2-82 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2field in the EATTR register. When the XD

Registershttp://www.mcg.mot.com/literature 2-832EATTR register. When the PRTAI bit in the EENAB register is set, the assertion of this bit will assert

2-84 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2PPC Error Attribute RegisterThe Error At

Registershttp://www.mcg.mot.com/literature 2-852If the PSMA or PRTA bit are set the register is defined by the following figure:WP Write Post Completi

2-86 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2PCI Interrupt Acknowledge RegisterThe PC

Registershttp://www.mcg.mot.com/literature 2-872START Start Address. This field determines the start address of a particular memory area on the PPC bu

2-88 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2The PPC Slave Attributes Registers (XSAT

Registershttp://www.mcg.mot.com/literature 2-892The PPC Slave Address Register3 (XSADD3) contains address information associated with the mapping of P

2-90 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2XSOFFx PPC Slave Offset. This register c

Registershttp://www.mcg.mot.com/literature 2-912WDTxCNTL RegistersThe Watchdog Timer Control Registers (WDT1CNTL and WDT2CNTL) are used to provide con

xvList of FiguresFigure 1-1. MVME2400 Series System Block Diagram ...1-6Figure 1-2. VMEbus Master Mapping...

2-92 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2ENAB ENAB. This field determines whether

Registershttp://www.mcg.mot.com/literature 2-932RELOAD Reload. This field is written with a value that will be used to reload the timer. The RELOAD fi

2-94 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2The General Purpose Registers (GPREG0, G

Registershttp://www.mcg.mot.com/literature 2-952PCI RegistersThe PCI Configuration Registers are compliant with the configuration register set describ

2-96 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Table 2-18. PCI I/O Register MapVendor

Registershttp://www.mcg.mot.com/literature 2-972PCI Command/ Status RegistersThe Command Register (COMMAND) provides course control over the PHB abili

2-98 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2P66M PCI66 MHz. This bit indicates the P

Registershttp://www.mcg.mot.com/literature 2-992Revision ID/ Class Code RegistersREVID Revision ID. This register identifies the PHB revision level. T

2-100 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2MPIC I/O Base Address RegisterThe MPIC

Registershttp://www.mcg.mot.com/literature 2-1012The MPIC Memory Base Address Register (MMBAR) controls the mapping of the MPIC control registers in P

xvi

2-102 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2START Start Address. This field determi

Registershttp://www.mcg.mot.com/literature 2-1032GBL Global Enable. If set, the PPC master will assert the GBL_ pin for each PPC transaction originate

2-104 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2CONFIG_ADDRESS RegisterThe description

Registershttp://www.mcg.mot.com/literature 2-1052Perspective from the PPC bus in Little Endian mode:The register fields are defined as follows:REG Reg

2-106 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2EN Enable. Configuration Cycles: Writin

Registershttp://www.mcg.mot.com/literature 2-1072Conceptual perspective from the PCI bus:Perspective from the PPC bus in Big Endian mode:Perspective f

2-108 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2MPIC RegistersThe following conventions

Registershttp://www.mcg.mot.com/literature 2-1092SP REGISTER $010e0TIMER FREQUENCY REPORTING REGISTER $010f0TIMER 0 CURRENT COUNT REGISTER $01100TIMER

2-110 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2INT. SRC. 4 DESTINATION REGISTER $10090

Registershttp://www.mcg.mot.com/literature 2-1112IPI 1 DISPATCH REGISTER PROC. 0 $20050IPI 2 DISPATCH REGISTER PROC. 0 $20060IPI 3 DISPATCH REGISTER P

xviiList of TablesTable 1-1. MVME240x Features ...1-3Table 1-2. Default Pro

2-112 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Feature Reporting RegisterNIRQ NUMBER O

Registershttp://www.mcg.mot.com/literature 2-1132Global Configuration RegisterR RESET CONTROLLER. Writing a one to this bit forces the controller logi

2-114 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2TIE Tie Mode. Writing a one to this reg

Registershttp://www.mcg.mot.com/literature 2-1152STP STEPPING.The stepping or silicon revision number is initially 0.Processor Init RegisterP1 PROCESS

2-116 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2IPI Vector/Priority RegistersMASK MASK.

Registershttp://www.mcg.mot.com/literature 2-1172Spurious Vector RegisterVECTOR This vector is returned when the Interrupt Acknowledge register is rea

2-118 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Timer Current Count RegistersT TOGGLE.

Registershttp://www.mcg.mot.com/literature 2-1192Timer Basecount RegistersCI COUNT INHIBIT. Setting this bit to one inhibits counting for this timer.

2-120 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Timer Vector/Priority RegistersMASK MAS

Registershttp://www.mcg.mot.com/literature 2-1212Timer Destination RegistersThis register indicates the destinations for this timer’s interrupts. Time

xviiiTable 2-16. PPC Register Map for PHB ... 2-66Table 2-17. PCI Configuration Register

2-122 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2MASK MASK. Setting this bit disables an

Registershttp://www.mcg.mot.com/literature 2-1232External Source Destination RegistersThis register indicates the possible destinations for the extern

2-124 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2ACT ACTIVITY. The activity bit indicate

Registershttp://www.mcg.mot.com/literature 2-1252Interprocessor Interrupt Dispatch RegistersThere are four Interprocessor Interrupt Dispatch Registers

2-126 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Interrupt Task Priority RegistersThere

Registershttp://www.mcg.mot.com/literature 2-1272Interrupt Acknowledge RegistersOn PowerPC-based systems, Interrupt Acknowledge is implemented as a re

2-128 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2service by the associated processor. Th

3-133System Memory Controller(SMC)IntroductionThe SMC in the Hawk ASIC is equivalent to the former Falcon Pair portion of a Falcon/Raven chipset. As w

3-2 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3❏ Error Notification for SDRAM– Software programmable Interrupt on Single/

Block Diagramshttp://www.mcg.mot.com/literature 3-33Figure 3-1. Hawk Used with Synchronous DRAM in a SystemPowerPC 60x BusDRAMSynchHAWKCheckDataPowe

xixTable A-3. Related Specifications ...A-5Table B-1. VPD Packet Types ...

3-4 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Figure 3-2. Hawk’s System Memory Controller Internal Data PathsCKD[0:7]RD

Block Diagramshttp://www.mcg.mot.com/literature 3-53Figure 3-3. Overall SDRAM Connections (4 Blocks using Register Buffers)HAWKSDRAMBLOCK ASDRAMBLOCK

3-6 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Figure 3-4. Hawk’s System Memory Controller Block DiagramSDRAM SDRAMDATAJ

Functional Descriptionhttp://www.mcg.mot.com/literature 3-73Functional DescriptionThe following sections describe the logical function of the SMC. The

3-8 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Page HoldingFurther savings comes when the new address is close enough to

Functional Descriptionhttp://www.mcg.mot.com/literature 3-934-Beat Write after 4-Beat Write,SDRAM Bank Active - Page Miss6-1-1-14-Beat Write after 4-B

3-10 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Notes SDRAM speed attributes are programmed for the following: CAS_latenc

Functional Descriptionhttp://www.mcg.mot.com/literature 3-113ROM/Flash SpeedsThe SMC provides the interface for two blocks of ROM/Flash. Access times

3-12 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Notes The information in Table 3-3 applies to access timing when configur

Functional Descriptionhttp://www.mcg.mot.com/literature 3-133Note The information in Table 3-4 applies to access timing when configured for devices wi

NoticeWhile reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omission

xx

3-14 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3asserts AACK_ coincident with the uncompleted data transfer’s last data b

Functional Descriptionhttp://www.mcg.mot.com/literature 3-153PPC60x Address ParityThe Hawk has 4 AP pins for generating and checking PPC60x address bu

3-16 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3ECCThe SMC performs single-bit error correction and double-bit error dete

Functional Descriptionhttp://www.mcg.mot.com/literature 3-173Notes:1. No opportunity for error since no read of SDRAM occurs during a four-beat write.

3-18 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3ROM/Flash InterfaceThe SMC provides the interface for two blocks of ROM/F

Functional Descriptionhttp://www.mcg.mot.com/literature 3-193b. all reads are allowed (multiple accesses are performed to the ROM/Flash devices when t

3-20 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Table 3-7. PowerPC 60x to ROM/Flash (16 Bit Width) Address MappingPowerP

Functional Descriptionhttp://www.mcg.mot.com/literature 3-213Table 3-8. PowerPC 60x to ROM/Flash (64 Bit Width) Address MappingPowerPC 60x A0-A31 RO

3-22 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3$X3FFFFFA $7FFFFF Upper$X3FFFFFB $7FFFFF Upper$X3FFFFFC $7FFFFF Lower$X3F

Functional Descriptionhttp://www.mcg.mot.com/literature 3-233I2C InterfaceThe ASIC has an I2C (Inter-Integrated Circuit) two-wire serial interface bus

1-111Board Description andMemory MapsIntroductionThis manual provides programming information for the MVME240x VME Processor Modules. Extensive progra

3-24 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3I2C Byte WriteThe I2C Status Register contains the i2_cmplt bit which is

Functional Descriptionhttp://www.mcg.mot.com/literature 3-253Figure 3-5. Programming Sequence for I2C Byte WriteREAD I2C STATUS REGCMPLT=1? NYLOAD “W

3-26 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3I2C Random ReadThe I2C random read begins in the same manner as the I2C b

Functional Descriptionhttp://www.mcg.mot.com/literature 3-273Figure 3-6. Programming Sequence for I2C Random ReadREAD I2C STATUS REGCMPLT=1? NYLOAD “

3-28 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3I2C Current Address ReadThe I2C slave device should maintain the last add

Functional Descriptionhttp://www.mcg.mot.com/literature 3-293Figure 3-7. Programming Sequence for I2C Current Address ReadREAD I2C STATUS REGCMPLT=1?

3-30 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3I2C Page WriteThe I2C page write is initiated the same as the I2C byte wr

Functional Descriptionhttp://www.mcg.mot.com/literature 3-313Figure 3-8. Programming Sequence for I2C Page WriteREAD I2C STATUS REGCMPLT=1? NYLOAD “W

3-32 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3I2C Sequential ReadThe I2C sequential read can be initiated by either an

Functional Descriptionhttp://www.mcg.mot.com/literature 3-333before receiving the last data word. A stop sequence then must be transmitted to the slav

1-2 Computer Group Literature Center Web SiteBoard Description and Memory Maps1An asterisk (*) following the signal name for signals which are level s

3-34 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Figure 3-9. Programming Sequence for I2C Sequential ReadREAD I2C STATUS

Functional Descriptionhttp://www.mcg.mot.com/literature 3-353Refresh/ScrubThe SMC performs refresh by doing a burst of 4 CAS-Before-RAS (CBR) refresh

3-36 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3after the rising edge of the PURST_ signal pin. A recommended way to cont

Programming Modelhttp://www.mcg.mot.com/literature 3-373Table 3-9. Register SummaryBIT # ---->0123456789101112131415161718192021222324252627282930

3-38 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3FEF80068dpelogDPE_TT DPE_DPdpe_ckalldpe_meGWDPFEF80070DPE_AFEF80078DPE_DH

Programming Modelhttp://www.mcg.mot.com/literature 3-393Notes 1. All empty bit fields are reserved and read as zeros.2. All status bits are shown in i

3-40 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Vendor/Device RegisterVENDID This read-only register contains the value $

Programming Modelhttp://www.mcg.mot.com/literature 3-413Software should only set the tben_en bit when there is no external L2 cache connected to the I

3-42 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3SDRAM Enable and Size Register (Blocks A, B, C, D)Writes to this register

Programming Modelhttp://www.mcg.mot.com/literature 3-433siz0-ram siz3. Note that ram e/f/g/h size0-3 are located at $FEF800C0. They operate identicall

Overviewhttp://www.mcg.mot.com/literature 1-31bit is used to describe a bit in a register that reflects a specific condition. The status bit can be re

3-44 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)300000 if their corresponding blocks are not present. Failure to do so wil

Programming Modelhttp://www.mcg.mot.com/literature 3-453Note that RAM_E/F/G/H_BASE are located at $FEF800C8 (refer to the section on SDRAM Base Addres

3-46 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3possible after power-up reset so that SDRAM refresh does not get behind.

Programming Modelhttp://www.mcg.mot.com/literature 3-473Figure 3-10. Read/Write Check-bit Data PathsNote that if test software wishes to force a sing

3-48 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)35. Clear the derc and rwcb bits in the Data Control register.6. Perform t

Programming Modelhttp://www.mcg.mot.com/literature 3-493sien When sien is set, the logging of a single-bit error causes the int bit to be set if it is

3-50 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Error Logger RegisterelogWhen set, elog indicates that a single- or a mul

Programming Modelhttp://www.mcg.mot.com/literature 3-513esbt esbt is set by the logging of a single-bit error. It is cleared by the logging of a multi

3-52 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Error_Address RegisterERROR_ADDRESS These bits reflect the value that cor

Programming Modelhttp://www.mcg.mot.com/literature 3-533Note that when this register is all 0’s, the scrub prescale counter does not increment, disabl

1-4 Computer Group Literature Center Web SiteBoard Description and Memory Maps1System Block DiagramThe MVME2400 is a VMEbus-based single-slot Single B

3-54 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3ROM A Base/Size RegisterWrites to this register must be enveloped by a pe

Programming Modelhttp://www.mcg.mot.com/literature 3-553When rom_a_64 is set, Block A is 64 bits wide, where each half of the SMC interfaces to 32 bit

3-56 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3rom_a_rv is initialized at power-up reset to match the value on the RD0 p

Programming Modelhttp://www.mcg.mot.com/literature 3-573ROM B Base/Size RegisterWrites to this register must be enveloped by a period of time in which

3-58 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3rom_b_64 rom_b_64 indicates the width of ROM/Flash device/devices being u

Programming Modelhttp://www.mcg.mot.com/literature 3-593rom b we When rom b we is set, writes to Block B ROM/Flash are enabled. When rom b we is clear

3-60 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3rom_b_spd0,1 rom_b_spd0,1 determine the access timing used for ROM/Flash

Programming Modelhttp://www.mcg.mot.com/literature 3-613DPE_DP DPE_DP is the value that was on the DP0-DP7 signals when the dpelog bit was set.dpe_cka

3-62 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Data Parity Error Upper Data RegisterDPE_DH DPE_DH is the value on the up

Programming Modelhttp://www.mcg.mot.com/literature 3-633I2C Clock Prescaler RegisterI2_PRESCALE_VALI2_PRESCALE_VAL is a 16-bit register value that wil

System Block Diagramhttp://www.mcg.mot.com/literature 1-51two PMC slots. Standard I/O functions are provided by the UART device which resides on the I

3-64 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3contents have been transmitted, the I2C master controller will automatica

Programming Modelhttp://www.mcg.mot.com/literature 3-653i2_err This bit is set when both i2_start and i2_stop bits in the I2C Control Register are set

3-66 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3responding slave device to transmit data to the I2C Receiver Data Registe

Programming Modelhttp://www.mcg.mot.com/literature 3-673should begin until after the write is done. A simple way to do this is to perform at least two

3-68 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3should begin until after the write is done. A simple way to do this is to

Programming Modelhttp://www.mcg.mot.com/literature 3-693SDRAM Speed Attributes RegisterThe SDRAM Speed Attributes Register should be programmed based

3-70 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3trc0,1,2 Together trc0,1,2 determine the minimum number of clock cycles t

Programming Modelhttp://www.mcg.mot.com/literature 3-713tdp tdp determines the minimum number of clock cycles that the SMC assumes the SDRAM requires

3-72 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Address Parity Error Address RegisterAPE_A APE_A is the address of the la

Programming Modelhttp://www.mcg.mot.com/literature 3-73332-Bit CounterCTR32CTR32 is a 32-bit, free-running counter that increments once per microsecon

1-6 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Figure 1-1. MVME2400 Series System Block Diagram2067 970833MHz 32/64-b

3-74 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3The tben register (which is internal to Hawk) responds only when tben_en

Programming Modelhttp://www.mcg.mot.com/literature 3-753tben RegisterThe tben Register is only enabled when the tben_en bit in the Revision ID/General

3-76 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Software ConsiderationsThis section contains information that will be use

Software Considerationshttp://www.mcg.mot.com/literature 3-773Initializing SDRAM Related Control RegistersIn order to establish proper SDRAM operation

3-78 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Board designers can implement one EEPROM for each of Hawk’s SDRAM blocks

Software Considerationshttp://www.mcg.mot.com/literature 3-793c. Test the first 1Mbyte of the block.d. If the test fails, disable the block, clear its

3-80 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3Use the following table to convert SPD bytes 27, 29 and 30 to the correct

Software Considerationshttp://www.mcg.mot.com/literature 3-813Note1. Use tRAS from the SDRAM block that has the slowest tRAS.2. tRAS_CLK is tRAS expre

3-82 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3a. Remember that CLK is the Hawk’s 60x clock input pin.9. Determine the s

Software Considerationshttp://www.mcg.mot.com/literature 3-833Notes 1. Total Number of block Locations (L) is 2R x 2C x 4 where R is the value in SPD

Functional Descriptionhttp://www.mcg.mot.com/literature 1-71Functional DescriptionOverviewThe MVME2400 series is a family of single-slot VME processor

3-84 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3information). Note that the refdis control bit must not be set in the ECC

Software Considerationshttp://www.mcg.mot.com/literature 3-853a. Clear the isa_hole bit (refer to the section titled “Vendor/Device Register” for more

3-86 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3a. Set the block’s base address to $00000000. Refer to the sections title

Software Considerationshttp://www.mcg.mot.com/literature 3-873Notes 1. 16Mx8 and 16Mx4 are the same. If the real size is either one of these, this alg

3-88 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3ECC CodesWhen the Hawk reports a single-bit error, software can use the s

ECC Codeshttp://www.mcg.mot.com/literature 3-893Table 3-22. Single Bit Errors Ordered by Syndrome CodeSyn-dromeBit Syn-dromeBit Syn-dromeBit Syn-drom

3-90 Computer Group Literature Center Web SiteSystem Memory Controller (SMC)3

4-144Universe II (VMEbus to PCI)ChipNote All of the information in this chapter (except the section Universe II Chip Problems after a PCI Reset) is ta

4-2 Computer Group Literature Center Web SiteUniverse II (VMEbus to PCI) Chip4– A32/A24/A16 master and slave– D64 (MBLT)/D32/D16/D08 master and slave–

Functional Descriptionhttp://www.mcg.mot.com/literature 4-34❏ PCI Bus Interface❏ Interrupter and Interrupt Handler❏ DMA ControllerThese sections descr

1-8 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Programming ModelMemory MapsThe following sections describe the memory

4-4 Computer Group Literature Center Web SiteUniverse II (VMEbus to PCI) Chip4VMEbus InterfaceUniverse II as VMEbus SlaveThe Universe II VME Slave Cha

Functional Descriptionhttp://www.mcg.mot.com/literature 4-54The Universe II is also compatible with all VMEbus modules conforming to pre-VME64 specifi

4-6 Computer Group Literature Center Web SiteUniverse II (VMEbus to PCI) Chip4Interrupter and Interrupt HandlerInterrupterThe Universe II interrupt ch

Registers - Universe II Control and Status Registers (UCSR)http://www.mcg.mot.com/literature 4-74DMA ControllerThe Universe II provides an internal DM

4-8 Computer Group Literature Center Web SiteUniverse II (VMEbus to PCI) Chip4Figure 4-2 below summarizes the supported register access mechanisms.Fig

Registers - Universe II Control and Status Registers (UCSR)http://www.mcg.mot.com/literature 4-94Table 4-1. Universe II Register MapOffset Register N

4-10 Computer Group Literature Center Web SiteUniverse II (VMEbus to PCI) Chip4120 PCI Slave Image 1 Translation Offset LSI1_TO124 Universe II Reserve

Registers - Universe II Control and Status Registers (UCSR)http://www.mcg.mot.com/literature 4-11420C Universe II Reserved210 DMA VMEbus Address Regis

4-12 Computer Group Literature Center Web SiteUniverse II (VMEbus to PCI) Chip4400 Master Control MAST_CTL404 Miscellaneous Control MISC_CTL408 Miscel

Registers - Universe II Control and Status Registers (UCSR)http://www.mcg.mot.com/literature 4-134F70 VMEbus Register Access Image Control Register VR

Programming Modelhttp://www.mcg.mot.com/literature 1-91Default Processor Memory MapAfter a reset, the Hawk ASIC provides the default processor memory

4-14 Computer Group Literature Center Web SiteUniverse II (VMEbus to PCI) Chip4

5-155Programming DetailsIntroductionThis chapter contains details of several programming functions that are not tied to any specific ASIC chip.PCI Arb

5-2 Computer Group Literature Center Web SiteProgramming Details5Interrupt HandlingThe interrupt architecture of the MVME2400 series SBC is shown in t

Interrupt Handlinghttp://www.mcg.mot.com/literature 5-35Hawk MPICThe Hawk ASIC has a built-in interrupt controller that meets the Multi-Processor Inte

5-4 Computer Group Literature Center Web SiteProgramming Details5Notes:1. Interrupt from the PCI/ISA Bridge.2. The mapping of interrupt sources from t

Interrupt Handlinghttp://www.mcg.mot.com/literature 5-55The following figure shows the interrupt structure of the PIB.Figure 5-2. PIB Interrupt Handl

5-6 Computer Group Literature Center Web SiteProgramming Details5The assignments of the PCI and ISA interrupts supported by the PIB are as follows:Tab

ISA DMA Channelshttp://www.mcg.mot.com/literature 5-75Notes:1. Internally generated by the PIB.2. After a reset, all ISA IRQ interrupt lines default t

5-8 Computer Group Literature Center Web SiteProgramming Details5ExceptionsSources of ResetThere are nine potential sources of reset on the MVME2400 s

Exceptionshttp://www.mcg.mot.com/literature 5-95The following table shows which devices are affected by various reset sources:Soft ResetSoftware can a

PrefaceThe MVME2400-Series VME Processor Module Programmer’s Reference Guide provides brief board level information, complete memory maps, and detaile

1-10 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Processor CHRP Memory MapThe following table shows a recommended CHRP

5-10 Computer Group Literature Center Web SiteProgramming Details5Error Notification and HandlingThe Hawk ASIC can detect certain hardware errors and

Endian Issueshttp://www.mcg.mot.com/literature 5-115Endian IssuesThe MVME2400 series supports both little endian software and big-endian software. Bec

5-12 Computer Group Literature Center Web SiteProgramming Details5Figure 5-3. Big-Endian ModeBig-Endian PROGRAM1898 9609HawkUniverse IIHawkDRAMBig En

Endian Issueshttp://www.mcg.mot.com/literature 5-135Figure 5-4. Little-Endian ModeEA Modification (XOR)1899 9609HawkUniverse IIHawkDRAMBig EndianLitt

5-14 Computer Group Literature Center Web SiteProgramming Details5Processor/Memory DomainThe MPC604 processor can operate in both big-endian and littl

Endian Issueshttp://www.mcg.mot.com/literature 5-155and big-endian mode, there should be no endian issues for the Ethernet data. Big-endian software m

5-16 Computer Group Literature Center Web SiteProgramming Details5ROM/Flash InitializationThere are two methods used to inject code into the Flash in

AA-1AOrdering RelatedDocumentationMotorola Computer Group DocumentsThe publications listed below are on related products, and some may be referenced i

Manufacturers’ DocumentsA-2 Computer Group Literature Center Web SiteAManufacturers’ DocumentsFor additional information, refer to the following table

Ordering Related Documentationhttp://www.mcg.mot.com/literature A-3APowerPCTM Microprocessor Family: The Programming EnvironmentsLiterature Distributi

Programming Modelhttp://www.mcg.mot.com/literature 1-1113. Programmable via PHB.4. CHRP requires the starting address for the PCI memory space to be 2

Manufacturers’ DocumentsA-4 Computer Group Literature Center Web SiteAM48T559 CMOS 8K x 8 TIMEKEEPERTM SRAM Data SheetSGS-Thomson Microelectronics Gro

Ordering Related Documentationhttp://www.mcg.mot.com/literature A-5ARelated SpecificationsFor additional information, refer to the following table for

Related SpecificationsA-6 Computer Group Literature Center Web SiteAIEEE - PCI Mezzanine Card Specification (PMC)Institute of Electrical and Electroni

Ordering Related Documentationhttp://www.mcg.mot.com/literature A-7APowerPC Microprocessor Common Hardware Reference PlatformA System Architecture (CH

Related SpecificationsA-8 Computer Group Literature Center Web SiteA

BB-1BMVME2400 VPD ReferenceInformationVital Product Data (VPD) IntroductionThe data listed in the following tables are for general reference informati

Vital Product Data (VPD) IntroductionB-2 Computer Group Literature Center Web SiteBNotes:1. The data size is variable. Its actual size is dependent up

MVME2400 VPD Reference Informationhttp://www.mcg.mot.com/literature B-3B2. Integer values are formatted/stored in big-endian byte ordering.3. This pac

Vital Product Data (VPD) IntroductionB-4 Computer Group Literature Center Web SiteB14 PCO_EIDE2_CONN1IDE/EIDE device 2 connector 1 present15 PCO_EIDE2

MVME2400 VPD Reference Informationhttp://www.mcg.mot.com/literature B-5BVPD Data Definitions - FLASH Memory Configuration DataThe FLASH memory configu

1-12 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Processor PREP Memory MapThe Hawk ASIC can be programmed for PREP-comp

Vital Product Data (VPD) IntroductionB-6 Computer Group Literature Center Web SiteBVPD Data Definitions - L2 Cache Configuration DataThe L2 cache conf

MVME2400 VPD Reference Informationhttp://www.mcg.mot.com/literature B-7BIt is possible for a product to contain multiple L2 cache configuration packet

Vital Product Data (VPD) IntroductionB-8 Computer Group Literature Center Web SiteBExample VPD SROMOne MVME2400 board build configuration example is p

MVME2400 VPD Reference Informationhttp://www.mcg.mot.com/literature B-9B23 (0x17) 0C24 (0x18) 3025 (0x19) 3126 (0x1a) 2D27 (0x1b) 5728 (0x1c) 3329 (0x

Vital Product Data (VPD) IntroductionB-10 Computer Group Literature Center Web SiteB50 (0x32) 8051 (0x33) 0052 (0x34) B853 (0x35) 0054 (0x36) 0055 (0x

MVME2400 VPD Reference Informationhttp://www.mcg.mot.com/literature B-11B77 (0x4D) 3778 (0x4E) 3579 (0x4F) 3080 (0x50) 0APACKET INTEGEREPROM CRCWhen c

Vital Product Data (VPD) IntroductionB-12 Computer Group Literature Center Web SiteB100 (0x64)FF101 (0x65)FF102 (0x66)FF103 (0x67)FF104 (0x68)08105 (0

MVME2400 VPD Reference Informationhttp://www.mcg.mot.com/literature B-13B116 (0x74)20117 (0x75)02118 (0x76)02119 (0x77)20120 (0x78)00121 (0x79)00122 (

Vital Product Data (VPD) IntroductionB-14 Computer Group Literature Center Web SiteBNote *This data will change to reflect the specific configuration

GL-1GlossaryAbbreviations, Acronyms, and Terms to KnowThis glossary defines some of the abbreviations, acronyms, and key terms used in this document.1

Programming Modelhttp://www.mcg.mot.com/literature 1-1314. The first 1 Mbyte of ROM/FLASH Bank A appears at this range after a reset if the rom_b_rv c

GlossaryGL-2 Computer Group Literature Center Web SiteGLOSSARYAUI Attachment Unit InterfaceBBRAM Battery Backed-up Random Access Memorybi-endian Havin

http://www.mcg.mot.com/literature GL-3GLOSSARYCD-ROM Compact Disk Read-Only MemoryCFM Cubic Feet per MinuteCHRP See Common Hardware Reference Platform

GlossaryGL-4 Computer Group Literature Center Web SiteGLOSSARYDRAM Dynamic Random Access Memory. A memory technology that is characterized by extreme

http://www.mcg.mot.com/literature GL-5GLOSSARYfirmware The program or specific software instructions that have been more or less permanently burned in

GlossaryGL-6 Computer Group Literature Center Web SiteGLOSSARYIQ Signals Similar to the color difference signals (R-Y), (B-Y) but using different vect

http://www.mcg.mot.com/literature GL-7GLOSSARYMPC604 Motorola’s component designation for the PowerPC 604 microprocessor.MPIC Multi-Processor Interrup

GlossaryGL-8 Computer Group Literature Center Web SiteGLOSSARYPCI (local bus) Peripheral Component Interconnect (local bus) (Intel). A high-performanc

http://www.mcg.mot.com/literature GL-9GLOSSARYPowerPC 603™ The second implementation of the PowerPC family of microprocessors. This CPU incorporates a

GlossaryGL-10 Computer Group Literature Center Web SiteGLOSSARYRGB The three separate color signals: Red, Green, and Blue. Used with color displays, a

http://www.mcg.mot.com/literature GL-11GLOSSARYsoftware A computing system is normally spoken of as having two major components: hardware and software

1-14 Computer Group Literature Center Web SiteBoard Description and Memory Maps1PCI Memory MapsThe PCI memory map is controlled by the PHB portion of

GlossaryGL-12 Computer Group Literature Center Web SiteGLOSSARYVGA Video Graphics Array (IBM). The third and most common monitor standard used today.

IN-1IndexNumerics16550 access registers 1-2916550 UART 1-2932-Bit Counter 3-73SMC 3-738259 interruptsPIB 5-4AA0-A31 3-5AACKas used with PPC Slave 2-7a

IndexIN-2 Computer Group Literature Center Web SiteINDEXblock diagram 2-3SMC poriton of Hawk 3-2block diagramsHawk with SDRAMs 3-2board configuration

http://www.mcg.mot.com/literature IN-3INDEXSMC 3-14decimal number 1-1decoderpriorities 2-20decodersaddress PCI to PPC 2-5for PCI to PPC addressing 2-1

IndexIN-4 Computer Group Literature Center Web SiteINDEXexplained 2-4Flash (see ROM/Flash) 3-18four-beat reads/writes 3-7functional description 1-7Haw

http://www.mcg.mot.com/literature IN-5INDEXSMC 3-64I2C Transmitter Data RegisterSMC 3-65initializingSDRAM-related control registers 3-77Interprocessor

IndexIN-6 Computer Group Literature Center Web SiteINDEXMulti-Processor Interrupt Controller 2-1MVME2300 series system block diagram 1-6MVME2400endian

http://www.mcg.mot.com/literature IN-7INDEXas mapped within PCI Configurationspace 2-19PHB errorstypes described 2-40PHB PCI Register ValuesCHRP memor

IndexIN-8 Computer Group Literature Center Web SiteINDEXprocessor CHRP memory map 1-10Processor Init Register 2-115processor memory map 1-8processor m

http://www.mcg.mot.com/literature IN-9INDEXSMC Error Logger 3-50SMC External Register set 3-73SMC General Control Register 3-40SMC I2C Clock Prescaler

Programming Modelhttp://www.mcg.mot.com/literature 1-151Notes:1. Programmable via the PHB’s PCI Configuration registers. For the MVME2400 series, RAM

IndexIN-10 Computer Group Literature Center Web SiteINDEXScrub Write Enable control bit 3-52Scrub/Refresh RegisterSMC 3-52SDRAMOperational Method for

http://www.mcg.mot.com/literature IN-11INDEXSMC Scrub Address Register 3-53SMC tben Register 3-75soft resetMPIC 5-9software considerations 3-76Hawk 3-

IndexIN-12 Computer Group Literature Center Web SiteINDEXVendor Identification Register 2-114Vendor/Device RegisterSMC 3-40Vital Product Data (VPD) 1-

®™®™®™®™MVME2400-Series VME Processor ModuleProgrammer’s Reference GuideMVME2400-SeriesVME Processor ModuleProgrammer’sReference Guide34 pages1/8” spi

1-16 Computer Group Literature Center Web SiteBoard Description and Memory Maps1The following table shows the programmed values for the associated PHB

Programming Modelhttp://www.mcg.mot.com/literature 1-171$120 LSI1_TO XXXX 0000$128 LSI2_CTL 0000 0000$12C LSI2_BS XXXX XXXX$130 LSI2_BD XXXX XXXX$134

1-18 Computer Group Literature Center Web SiteBoard Description and Memory Maps1PCI PREP Memory MapThe following table shows a PCI memory map of the M

Programming Modelhttp://www.mcg.mot.com/literature 1-1913. Programmable mapping via the four PCI Slave Images in the Universe II ASIC.4. Programmable

is used for system output (e.g., screen displays, reports), examples, and systemprompts.<RETURN> or <CR>represents the carriage return or

1-20 Computer Group Literature Center Web SiteBoard Description and Memory Maps1The next table shows the programmed values for the associated Universe

Programming Modelhttp://www.mcg.mot.com/literature 1-211VMEbus MappingNote For the MVME2400 series, RAM size is limited to 256MB.VMEbus Master MapThe

1-22 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Figure 1-2. VMEbus Master MappingNotes:1. Programmable mapping done b

Programming Modelhttp://www.mcg.mot.com/literature 1-2312. Programmable mapping via the four PCI Slave Images in the Universe II ASIC.3. Programmable

1-24 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Figure 1-3. VMEbus Slave MappingNotes:1. Programmable mapping via the

Programming Modelhttp://www.mcg.mot.com/literature 1-251The following table shows the programmed values for the associated Universe II registers for t

1-26 Computer Group Literature Center Web SiteBoard Description and Memory Maps1The above register values yield the following VMEbus slave map:Table 1

Programming Modelhttp://www.mcg.mot.com/literature 1-271System Configuration InformationThe MVME2400 uses a 512 byte serial EEPROM to store Vital Prod

1-28 Computer Group Literature Center Web SiteBoard Description and Memory Maps1termination packet identifier marks the end of the VPD and must immedi

ISA Local Resource Bushttp://www.mcg.mot.com/literature 1-291ISA Local Resource BusW83C553 PIB RegistersThe PIB contains ISA Bridge I/O registers for

Safety SummarySafety Depends On YouThe following general safety precautions must be observed during all phases of operation, service, and repair of th

1-30 Computer Group Literature Center Web SiteBoard Description and Memory Maps1General-Purpose Software-Readable Header (SRH) Switch (S3)Switch S3 is

ISA Local Resource Bushttp://www.mcg.mot.com/literature 1-311NVRAM/RTC & Watchdog Timer RegistersThe MK48T59/559 provides the MVME2400 series with

1-32 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Slave Image 0 into the appropriate PCI I/O address range. Refer to the

ISA Local Resource Bushttp://www.mcg.mot.com/literature 1-331SET_SIG0 Writing a 1 to this bit will set the SIG0 status bit.SET_LM1 Writing a 1 to this

1-34 Computer Group Literature Center Web SiteBoard Description and Memory Maps1EN_LM0 When the EN_LM0 bit is set, a LM/SIG Interrupt 0 is generated a

ISA Local Resource Bushttp://www.mcg.mot.com/literature 1-351Location Monitor Lower Base Address RegisterThe Location Monitor Lower Base Address Regis

1-36 Computer Group Literature Center Web SiteBoard Description and Memory Maps1Semaphore Register 2The Semaphore Register 2 is an 8-bit register loca

ISA Local Resource Bushttp://www.mcg.mot.com/literature 1-371Emulated Z8536 CIO Registers and Port PinsAlthough the MVME2400 series does not use a Z85

1-38 Computer Group Literature Center Web SiteBoard Description and Memory Maps1ISA DMA ChannelsThe MVME2400 series does not implement any ISA DMA cha

2-122Hawk PCI Host Bridge & Multi-Processor Interrupt ControllerIntroductionOverviewThis chapter describes the architecture and usage of the Power

2-2 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2– Read-ahead buffer for reads from the PP

Block Diagramhttp://www.mcg.mot.com/literature 2-32Block DiagramFigure 2-1. Hawk’s PCI Host Bridge Block DiagramEndianMuxDataCommandFIFOFIFOEndianMux

2-4 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Functional DescriptionArchitectural Overv

Functional Descriptionhttp://www.mcg.mot.com/literature 2-52into the PCI FIFO. The PPC Master will draw this command information from the PCI FIFO whe

2-6 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller216 bits of the PPC address are compared w

Functional Descriptionhttp://www.mcg.mot.com/literature 2-72Each map decoder also includes a programmable 16-bit address offset. The offset is added t

2-8 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2AACK_ and TA_ allows the PPC Slave to ass

Functional Descriptionhttp://www.mcg.mot.com/literature 2-92PPC FIFOA 64-bit by 8 entry FIFO (2 cache lines total) is used to hold data between the PP

2-10 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2example, two burst transactions would ma

Functional Descriptionhttp://www.mcg.mot.com/literature 2-112While the PCI Slave is filling the PCI FIFO with write data, the PPC Master can be moving

viiContentsCHAPTER 1 Board Description and Memory MapsIntroduction...

2-12 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2threshold should be lowered to anticipat

Functional Descriptionhttp://www.mcg.mot.com/literature 2-132Upon completion of a prefetched read transaction, any residual read data left within the

2-14 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2The PPC master incorporates an optional

Functional Descriptionhttp://www.mcg.mot.com/literature 2-152The selection of either internal or external PPC arbitration mode is made by sampling an

2-16 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2❏ HAWK (Highest Priority)❏ EXTL❏ CPUx❏ C

Functional Descriptionhttp://www.mcg.mot.com/literature 2-172error is detected, then the PHB will latch address and attribute information within the E

2-18 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2If the transaction was an address only c

Functional Descriptionhttp://www.mcg.mot.com/literature 2-192Configuration Registers:The PHB Configuration registers are mapped within PCI Configurati

2-20 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2For each map, there is an independent se

Functional Descriptionhttp://www.mcg.mot.com/literature 2-212MPIC Control Registers:The MPIC control registers are located within either PCI Memory or

viiiBlock Diagram...2-3Functional Description

2-22 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Command Types:Table 2-7 shows which type

Functional Descriptionhttp://www.mcg.mot.com/literature 2-232The PCI Slave only honors the Linear Incrementing addressing mode. The PCI Slave performs

2-24 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Fast Back-to-Back Transactions:The PCI S

Functional Descriptionhttp://www.mcg.mot.com/literature 2-252Cache Support:The PCI Slave does not participate in the PCI caching protocol.PCI FIFOA 64

2-26 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2The PCI Master can support Critical Word

Functional Descriptionhttp://www.mcg.mot.com/literature 2-272Addressing:The PCI Master generates all memory transactions using the Linear Incrementing

2-28 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Arbitration:The PCI Master can support p

Functional Descriptionhttp://www.mcg.mot.com/literature 2-292Parity:The PCI Master supports address parity generation, data parity generation, and dat

2-30 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2The PHB performs contiguous I/O addressi

Functional Descriptionhttp://www.mcg.mot.com/literature 2-312Generating PCI Configuration CyclesThe PHB uses configuration Mechanism #1 as defined in

ixBlock Diagram Description ...2-55Program Visible Registers...

2-32 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2When performing a configuration cycle, t

Functional Descriptionhttp://www.mcg.mot.com/literature 2-332Generating PCI Interrupt Acknowledge CyclesPerforming a read from the PIACK register will

2-34 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2The Hawk’s PCI arbiter has various progr

Functional Descriptionhttp://www.mcg.mot.com/literature 2-352Notes “000” is the default setting in fixed mode.The HEIR setting only covers a smaLL sub

2-36 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2Notes “000” is the default setting in mi

Functional Descriptionhttp://www.mcg.mot.com/literature 2-372Notes 1. “1000” is the default setting.2. Parking disabled is a test mode only and should

2-38 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2.Figure 2-7. Big to Little Endian Data

Functional Descriptionhttp://www.mcg.mot.com/literature 2-392transaction originates from the PCI bus or the PPC bus. The three low order address bits

2-40 Computer Group Literature Center Web SiteHawk PCI Host Bridge & Multi-Processor Interrupt Controller2register with respect to the PPC bus is

Functional Descriptionhttp://www.mcg.mot.com/literature 2-412Each ESTAT error bit may be programmed to generate a machine check and/or a standard inte