Motorola MVME2400 Series Manuel de service télécharger pdf (Page 106)

2-48 Computer Group Literature Center Web Site

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

❏ Write posted transactions originated from the PPC60x bus are

flushed in the following manner. The PPC Slave will set a signal

called ‘xs_fbrabt’ anytime it has committed to performing a posted

write transaction. This signal will remain asserted until the PCI

bound FIFO count has reached zero.

The PCI Slave decode logic settles out several clocks after the assertion of

FRAME_, at which time the PCI Slave can determine the transaction type.

If it is a read and PFBR is enabled, the PCI Slave will look at the

‘xs_fbrabt’ signal. If this signal is active, the PCI Slave will retry the PCI

Master.

PHB Hardware Configuration

Hawk has the ability to perform custom hardware configuration to

accommodate different system requirements. The PHB has several

functions that may be optionally enabled or disabled using passive

hardware external to Hawk. The selection process occurs at the first rising

edge of CLK after RST_ has been released. All of the sampled pins are

cascaded with several layers of registers to eliminate problems with hold

time.

Table 2-15 summarizes the hardware configuration options that relate to

the PHB.

Table 2-15. PHB Hardware Configuration

Function Sample Pin(s) Sampled

State

Meaning

PCI 64-bit Enable REQ64_ 0 64-bit PCI Bus

1 32-bit PCI Bus

PPC Register Base RD[5] 0 Register Base = $FEFF0000

1 Register Base = $FEFE0000

MPIC Interrupt Type RD[7] 0 Parallel Interrupts

1 Serial Interrupts

1 2 ... 101 102 103 104 105 106 107 108 109 110 111 ... 353 354

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Motorola MVME2400 Series Manuel de service Page 106