Motorola MVME2400 Series Manuel de service télécharger pdf (Page 108)

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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

❏ Direct/Multicast interrupt delivery for Interprocessor and timer

interrupts

❏ Four Interprocessor Interrupt sources

❏ Four timers

❏ Processor initialization control

Architecture

The PCI Slave of the PHB implements two address decoders for placing

the MPIC registers in PCI IO or PCI Memory space. Access to these

registers require PPC and PCI bus mastership. These accesses include

interrupt and timer initialization and interrupt vector reads.

The MPIC receives interrupt inputs from 16 external sources, four

interprocessor sources, four timer sources, and one PHB internal error

detection source. The externally sourced interrupts 1 through 15 have two

modes of activation; low level or active high positive edge. External

interrupt 0 can be either level or edge activated with either polarity. The

PHB interrupt request is an active low level sensitive interrupt. The

Interprocessor and timers interrupts are event activated.

If the OPIC is enabled, the PHB detected errors will be passed on to MPIC.

If the OPIC is disabled PHB detected errors are passed directly to the

processor 0 interrupt pin.

External Interrupt Interface

The external interrupt interface functions as either a parallel or a serial

interface depending on the EINTT bit in the MPIC Global Configuration

operates in the parallel mode.

In the serial mode, all 16 external interrupts are serially scanned into MPIC

using the SI_STA and SI_DAT pins as shown in Figure 2-8

In the parallel mode, 16 external signal pins are used as interrupt inputs

(interrupts 0 through 15).

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Motorola MVME2400 Series Manuel de service Page 108