Motorola MVME2400 Series Manuel de service télécharger pdf (Page 109)

Multi-Processor Interrupt Controller (MPIC) Functional Description

http://www.mcg.mot.com/literature 2-51

Figure 2-8. Serial Mode Interrupt Scan

Using PCLK as a reference, external logic will pulse SI_STA one clock

period indicating the beginning of an interrupt scan period. On the same

clock period that SI_STA is asserted, external logic will feed the state of

EXT0 on the SI_DAT pin. External logic will continue to sequentially

place EXT1 through EXT15 on SI_DAT during the next 15 clock periods.

This process may be repeated at any rate, with the fastest possible next

assertion of SI_STA on the clock following the sampling of EXT15. Each

scan process must always scan exactly 16 external interrupts.

CSR’s Readability

Unless explicitly specified, all registers are readable and return the last

value written. The exceptions are the IPI dispatch registers and the EOI

registers which return zero’s on reads, the interrupt source ACT bit which

returns current interrupt source status, the interrupt acknowledge register

which returns the vector of the highest priority interrupt which is currently

pending, and reserved bits which returns zero’s. The interrupt

acknowledge register is also the only register which exhibits any read side-

effects.

Interrupt Source Priority

Each interrupt source is assigned a priority value in the range from 0 to 15

where 15 is the highest. In order for delivery of an interrupt to take place

the priority of the source must be greater than that of the destination

processor. Therefore setting a source priority to zero inhibits that interrupt.

PCLK

SI_STA

SI_DAT

EXT0

EXT1

EXT2

EXT13

EXT14

EXT15

Earliest possible assertion of SI_STA

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Motorola MVME2400 Series Manuel de service Page 109